7ac17ff2b6
Root cause of the deferred CALL/RET test: my chip was missing the 0xC6 / 0xC7 (Group 11 — MOV r/m, imm) opcodes. Bytes like the test's "MOV byte [0x8002], 0x55" (0xC6 0x06 0x02 0x80 0x55) fell through to the default NOP, then the chip decoded the residual 0x06 0x02 0x80 0x55 as PUSH ES + ADD r/m + ... taking SP into unpredictable territory. Implementation: - 0xC6 (8-bit) and 0xC7 (16-bit) variants added. - The encoding is opcode + modrm + disp + imm. Critically the disp bytes (consumed by calc_ea) come BEFORE the immediate, so we compute EA first, then fetch imm. Earlier draft had imm fetched before disp — that had imm winning the disp slot and disp becoming the next instruction's bytes. Caught only after wiring CALL+RET. Tests: 8086 10→11 passing. Total test_intel: 93→94 passing, 0 failed, 11 todo. CALL/RET integration test now active and green. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
||
|---|---|---|
| .. | ||
| autosearch | ||
| scripts | ||
| src | ||
| test_4004 | ||
| test_4040 | ||
| test_8080 | ||
| test_8086 | ||
| test_buses | ||
| test_z80 | ||
| .gitignore | ||
| 00_README.md | ||
| package-lock.json | ||
| package.json | ||
| vitest.config.js | ||