test_intel: phase A — 8080 INTA bus protocol
Replace the synthesised-RST-7 stub with a real INTA bus cycle. When int_pending && IME, the chip emits status byte 0x23 on D during T1 (M1+INTA+WO̅) and samples the RST opcode external hardware drives on the data bus during DBIN. Decodes RST n (0xC7..0xFF) and push+vectors. Multi-byte INTA opcodes (CALL nnn) deferred. Test rewrites the INT case to install a fixture INTA driver: snoop SYNC + status byte, latch a pending flag, drive RST 5 (0xEF) on the data bus during the next DBIN edge. Driver registers AFTER fake_rom so its late drive overrides fake_rom's program-byte drive on the same DBIN edge. Tests: 8080 17→18 passing; test_intel 63→64 passing. Adds master plan doc autosearch/18_complete_emulation_plan.md covering phases A-G (this commit completes phase A). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
David Montero
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# Complete Emulation Plan — Phases A-G
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This document is the master plan for taking the test_intel chip suite
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from "baseline silicon contracts validated" to "real-software emulation
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that runs CP/M, ZEXDOC, CPUDIAG, Busicom 141-PF, and DOS-era 8086
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programs". It is updated as each phase completes; the sentinel at the
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top of each phase reflects status.
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## Constraints
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- **No frontend or backend modifications.** Velxio core stays
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untouched; all work happens under `test/test_intel/`.
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- **Clean-room implementation.** No GPL code. Permissive references
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(MIT/BSD/zlib/Apache) only, used for cross-validation never copying.
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- **Test-first.** Every chip / feature gets a test before any
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permanent .c change.
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- **Internet research authorized.** Download datasheets, public-domain
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ROMs, permissive open-source emulators as references.
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- **Document each phase on completion.** Append a "Phase X completed"
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section below with: what was done, what was deferred, lessons
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learned, test count delta.
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## Phases at a glance
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| Phase | Scope | Effort | Status |
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| --- | --- | --- | --- |
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| **A** | 8080 INTA bus cycle | low | ✅ done 2026-04-30 |
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| **B** | Z80 ISA polish for ZEXDOC | high | ⏸️ pending |
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| **C** | Support chip ecosystem (4001, 4002, 8259, 8253, 8255, 8251, rom-1m) | high | ⏸️ pending |
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| **D** | 4004/4040 I/O completion (uses chips from C) | medium | ⏸️ pending |
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| **E** | 8086 ISA completion | high | ⏸️ pending |
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| **F** | Real software validation (CPUDIAG, ZEXDOC, Busicom, 8088 V2) | medium | ⏸️ pending |
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| **G** | Cycle accuracy (optional) | high | ⏸️ deferred |
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---
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## Phase A — 8080 INTA bus protocol
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### Goal
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Replace the current "synthesize RST 7 internally" hack in `8080.c`
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with a proper INT-acknowledge bus cycle. When the chip detects INT
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asserted (with IME=1), it should perform an INTA M1 cycle (status byte
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0x23), read the opcode from the data bus, and execute it. External
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hardware (an 8259 PIC, or a test fixture) drives the RST opcode onto
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the data bus during INTA.
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### Deliverables
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- Modify `test_8080/8080.c`: replace `if (G.int_pending && G.ime)` block
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with a real bus-cycle that emits ST_INTA and reads the data bus.
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- Test: drive INT high, drive RST 5 (0xEF) on the bus during INTA,
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observe PC = 0x0028 + observe ISR runs.
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- Update `test_8080/README.md` status.
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### Sources
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- [I8080-1975] User's Manual section on Interrupt Acknowledge
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- Cross-check against `superzazu/8080`'s INTA implementation
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---
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## Phase B — Z80 ISA polish for ZEXDOC
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### Goal
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Bring the Z80 chip from "passes our 11 active tests" to "passes
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ZEXDOC" (the documented-flags subset of Frank Cringle's ZEXALL test
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ROM). This requires implementing several features that real Z80
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software depends on but which our current chip stubs.
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### Sub-phases
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- **B.1** CB prefix (256 ops): BIT n,r / SET n,r / RES n,r and the
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rotates RLC/RRC/RL/RR/SLA/SRA/SLL/SRL on r ∈ B/C/D/E/H/L/(HL)/A.
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- **B.2** DDCB / FDCB indexed bit ops: e.g. `BIT 0, (IX+d)` — fetched
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as `DD CB d byteOpcode`.
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- **B.3** Undocumented X (bit 3) and Y (bit 5) flag bits — copies of
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result bits 3/5. ZEXALL fails without these. Apply to all
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flag-affecting instructions.
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- **B.4** MEMPTR (WZ) internal register — affects bits 3/5 of F after
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`BIT n,(HL)` and DD/FD-prefixed BIT. Update list per Sean Young §4.1.
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- **B.5** Z80-specific DAA — uses N flag to determine direction
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(additive vs subtractive); H-flag table per Sean Young §4.7.
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- **B.6** Block I/O exact flags (INI/IND/INIR/INDR/OUTI/OUTD/OTIR/OTDR)
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per Sean Young §4.3.
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- **B.7** CPI/CPD/CPIR/CPDR with H/PV/Z exactly per Sean Young §4.2.
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- **B.8** RLD/RRD instructions.
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- **B.9** 16-bit ADC HL,rr / SBC HL,rr with bit-12 half-carry +
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16-bit overflow flag.
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- **B.10** All 8 NEG aliases (ED 44/4C/54/5C/64/6C/74/7C).
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### Deliverables
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- ~600 LOC additions to `test_z80/z80.c`.
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- New tests under `test_z80/`: per-feature unit tests + ZEXDOC
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integration test (runs the 9 KB ROM to completion, verifies the
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printed result byte sequence).
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- Vendoring of ZEXDOC ROM (public domain, Frank Cringle 1994).
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### Sources
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- Sean Young, *The Undocumented Z80 Documented* v0.91 (in `pdfs/`)
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- Zilog UM008003-1202 (in `pdfs/`)
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- Cross-check: `floooh/chips/z80.h` for MEMPTR map
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---
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## Phase C — Support chip ecosystem
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### Goal
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Build the supporting chips that real systems used. Without these,
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none of our CPUs can run actual programs on the canvas. All chips
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follow the existing custom-chip API and have unit tests.
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### Sub-phases
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- **C.1** `4001` ROM (16-pin DIP, 256 bytes, 4-bit nibble bus matching
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4004 SRC protocol; CMROM-strobed; ROM image baked in like rom-32k)
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- **C.2** `4002` RAM (16-pin DIP, 80 nibbles + 4 output port lines,
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SRC-addressed, CMRAM-strobed)
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- **C.3** `8259` PIC — 28-pin, 8 IRQ inputs, INT/INTA cycle to CPU,
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programmable vector base. Used by 8080/Z80/8086 for real interrupt
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systems.
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- **C.4** `8253` PIT — 24-pin, 3 channels of 16-bit countdown timers.
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Essential for BIOS-style code (system tick, speaker frequency).
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- **C.5** `8255` PPI — 40-pin, three 8-bit ports (A, B, C), 4 modes.
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Generic peripheral interface used in many 8080/Z80/8086 systems.
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- **C.6** `8251` USART — 28-pin, async serial UART. Enables "hello
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world" via terminal emulation.
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- **C.7** `rom-1m` — variant of rom-32k with 20-bit address bus
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(A0..A19) so 8086 can fetch from CS:IP=0xFFFF0 on canvas.
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### Deliverables
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- ~1500 LOC across 7 chips.
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- Per-chip test file (pin contract + protocol behavior).
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- Per-chip README.md.
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- Updated `test_buses/README.md` chip table.
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### Sources
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- Each chip's Intel datasheet (download from bitsavers.org).
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---
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## Phase D — 4004/4040 I/O completion
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### Goal
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Wire up the I/O group instructions (WRM/RDM/ADM/SBM/WRR/RDR/WR0..3/
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RD0..3) so they actually access RAM/ROM ports through the SRC + CMRAM
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mechanism. Requires `4001` and `4002` from Phase C.
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### Sub-phases
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- **D.1** SRC instruction emits chip-select address on D bus during X2
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with appropriate CMROM/CMRAMᵢ strobing, latched by external chip
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- **D.2** Subsequent I/O instruction (WRM/RDM/etc.) re-asserts the
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selected CMROM/CMRAMᵢ during M2 + X2/X3 to drive R/W to that chip
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- **D.3** WRM/RDM/ADM/SBM hit 4002 RAM character cells
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- **D.4** WRR/RDR hit 4001 ROM I/O port lines
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- **D.5** WR0..WR3 / RD0..RD3 hit 4002 RAM status characters
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- **D.6** 4040's BBS reissues the saved SRC at the X2/X3 of the BBS
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cycle so the chip selected before the interrupt is re-armed
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### Deliverables
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- Updates to `test_4004/4004.c` and `test_4040/4040.c`.
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- Integration tests using `4001` + `4002` chips on the same board:
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4004 reads/writes RAM, drives output port, reads input port.
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### Sources
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- MCS-4 manual §III.B (in `pdfs/`)
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- MCS-40 manual §1 (in `pdfs/`)
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---
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## Phase E — 8086 ISA completion
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### Goal
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Bring the 8086 from ~50 opcodes (~30% of ISA) to substantially
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complete (~95%). Target: subset of 8088 V2 SingleStepTests passing.
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### Sub-phases
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- **E.1** Shifts and rotates: SHL/SHR/SAR/ROL/ROR/RCL/RCR with imm or
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CL count. Group 2 (0xD0..0xD3).
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- **E.2** String ops: MOVSB/MOVSW, CMPSB/CMPSW, SCASB/SCASW, LODSB/
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LODSW, STOSB/STOSW + REP/REPE/REPNE prefix handling.
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- **E.3** Multiplication / division: MUL r/m8, MUL r/m16, IMUL r/m8,
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IMUL r/m16, DIV r/m8, DIV r/m16, IDIV r/m8, IDIV r/m16. Group 3
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(0xF6/0xF7).
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- **E.4** BCD adjust: DAA, DAS, AAA, AAS, AAM imm8, AAD imm8.
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- **E.5** Port I/O: IN AL,imm8 / IN AX,imm8 / IN AL,DX / IN AX,DX
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+ OUT counterparts.
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- **E.6** Hardware interrupts: NMI vector 2, INTR + INTA cycle reading
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vector byte from data bus, INT imm8, INT 3, INTO, IRET.
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- **E.7** LDS/LES (load far pointer), LAHF/SAHF, XCHG, XLAT.
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- **E.8** Conditional flag-set: SAHF, LAHF.
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- **E.9** Group 4 (0xFE) — INC/DEC r/m8.
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- **E.10** Undocumented opcodes: POP CS (0x0F), SALC (0xD6).
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### Deliverables
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- ~800 LOC additions to `test_8086/8086.c`.
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- New tests under `test_8086/` for each instruction class.
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### Sources
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- Intel iAPX 86,88 User's Manual (in `pdfs/`)
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- Cross-check: 8086tiny, MartyPC
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---
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## Phase F — Real software validation
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### Goal
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Prove correctness by running historic public-domain test programs.
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### Sub-phases
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- **F.1** **CPUDIAG** on 8080: load Microcosm Associates CPU diagnostic
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(1980, public domain) + minimal CP/M-like BDOS jump table; run until
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it prints "CPU IS OPERATIONAL"; integration test asserts expected
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output sequence.
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- **F.2** **ZEXDOC** on Z80: load Frank Cringle's ZEXDOC (subset of
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ZEXALL — documented flags only); run for ~minutes of simulated time
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(it's a many-CRC test); assert all 67 sub-tests pass.
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- **F.3** **8088 V2 SingleStepTests subset** on 8086: load JSON test
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cases (initial state + bus trace + final state) for selected
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opcodes; verify our chip matches.
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- **F.4** **Busicom 141-PF** on 4004: load the original Busicom
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calculator firmware; verify display sequence for a known
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calculation. (Requires 4001/4002 chips from Phase C.)
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### Deliverables
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- Integration test files under `test_<chip>/` that wire the CPU + ROM
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+ RAM and run the test ROM to completion.
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- Vendored public-domain ROMs under `test/test_intel/roms/`:
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- `cpudiag.bin` (~2 KB)
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- `zexdoc.bin` (~9 KB)
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- `busicom_141pf.bin` (~1 KB)
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- Test result expectations documented in autosearch/.
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### Sources
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- CPUDIAG: widely mirrored on Altair-related sites; license is
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effectively public-domain (Microcosm Associates, 1980).
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- ZEXDOC/ZEXALL: Frank Cringle 1994; public domain.
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- Busicom firmware: Intel released to public domain in 2009.
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- 8088 V2 SingleStepTests: Daniel Balsom's MartyPC project,
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MIT-licensed.
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---
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## Phase G — Cycle accuracy (optional, deferred)
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### Goal
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Move from instruction-per-tick to cycle-accurate timing. Necessary
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for emulating cycle-counting retro games (Spectrum games, Lotus
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Esprit, etc.).
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### Sub-phases
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- **G.1** Per-opcode cycle counts for all 5 CPUs.
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- **G.2** 8086 prefetch queue (4 bytes). Affects self-modifying
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code observable behavior.
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- **G.3** Z80 contended memory model (Spectrum 16K..32K cycles).
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- **G.4** Wait-state insertion via WAIT̅ + READY pin sampling.
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This is HUGE work and only valuable for niche use-cases. Skipped
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until user asks for it.
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---
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## Documentation conventions for completed phases
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Each completed phase appends a section titled `## Phase X — completed
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(YYYY-MM-DD)` with:
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- **Delivered**: bullet list of what shipped
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- **Deferred**: bullet list of what was originally planned but moved
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out of scope
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- **Tests delta**: +N passing, +M todo, etc.
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- **Files touched**: key paths
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- **Lessons / surprises**: notable discoveries during implementation
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- **Sources cited**: PDFs / repos / docs actually consulted
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Commits made during the phase reference the phase letter in the
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subject line (e.g. "test_intel: phase A — 8080 INTA bus protocol").
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---
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## Phase A — completed (2026-04-30)
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### Delivered
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- `test_8080/8080.c`: replaced the synthesised-RST-7 stub with a real
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INTA bus cycle. When `int_pending && ime`, the chip clears IME +
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INTE pin, runs `bus_read(PC, ST_INTA)` to emit status byte 0x23
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(M1+INTA+WO̅) on the data bus during T1, then samples the opcode
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external hardware (e.g. an 8259 PIC) jams onto D0..D7 during DBIN.
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RST n opcodes (0xC7..0xFF, mask 0xC7==0xC7) are decoded and
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push+vector executed.
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- `test_8080/8080.test.js`: rewrote the INT test to install a
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test-fixture INTA driver that snoops SYNC + the status byte to
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detect INTA cycles, then drives RST 5 (0xEF) on the data bus during
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DBIN. Driver registered AFTER bootCpu's fake_rom so the late drive
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overrides the fake_rom's program-byte drive.
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### Deferred
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- Multi-byte opcodes during INTA (CALL nnn, JMP nnn) — would require
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the chip to issue further INTA cycles for operand bytes. Spec
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permits but rarely used in practice. The chip currently treats
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non-RST INTA opcodes as NOP.
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- EI delayed-effect: real 8080 enables INT acknowledge on the
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*instruction after* EI so `EI; RET` is atomic. Mine enables
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immediately. Minor fidelity gap, no current test exercises it.
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### Tests delta
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- `test_8080`: 17 passing → **18 passing** (+1, the INT test
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promoted from pending-broken to passing).
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- Total `test_intel`: 63 → **64 passing**, 16 todo.
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### Files touched
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- `test/test_intel/test_8080/8080.c`
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- `test/test_intel/test_8080/8080.test.js`
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### Lessons
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- Listener registration order matters when multiple listeners drive
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the same pin. fake_rom registers a DBIN listener; an INTA fixture
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must register its own DBIN listener LATER so the late drive
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overrides. Documented in test comments.
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- Two-stage SYNC→DBIN handoff (latch a flag at SYNC, act on DBIN)
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works cleanly; the alternative of doing everything in the SYNC
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callback fails because fake_rom's later DBIN drive wins.
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### Sources cited
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- `pdfs/mcs80_users.pdf` (Intel 1975) — INTA cycle status word + bus
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protocol
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- Cross-checked behavior against `superzazu/8080`'s `i8080.c` lines
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on its `interrupt()` function (no code copied).
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---
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## Phase B — Z80 ISA polish for ZEXDOC — STARTING
|
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(Updates appended as work proceeds.)
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@ -323,16 +323,32 @@ static bool cond_met(uint8_t cc) {
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/* ─── One-instruction step ──────────────────────────────────────────────── */
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static void step(void) {
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/* Service interrupt if pending and IME — simple model: synthesise an
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implicit RST 7 (vector 0x0038). Real 8080 reads the RST opcode from
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the data bus during INTA; we approximate. */
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/* Service interrupt if pending and IME. Real 8080 INT acknowledge:
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run an INTA bus cycle (status byte 0x23 = M1+INTA+WO̅), read the
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opcode that external hardware (8259 PIC or hard-wired logic)
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jams onto the data bus, and execute it. The opcode is typically
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a RST n (0xC7..0xFF); we support that fully. Other opcodes
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during INTA are documented to work too (e.g. CALL nnn) but
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require multi-byte fetches with INTA status — deferred. */
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if (G.int_pending && G.ime) {
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G.ime = false;
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G.int_pending = false;
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G.halted = false;
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vx_pin_write(G.inte, 0);
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push16(G.pc);
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G.pc = 0x0038;
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/* Address driven on A0..A15 during INTA is undefined per
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datasheet; we drive PC for clarity. */
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uint8_t opcode = bus_read(G.pc, ST_INTA);
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if ((opcode & 0xC7) == 0xC7) {
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/* RST n */
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push16(G.pc);
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G.pc = (uint16_t)((opcode >> 3) & 7) * 8;
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}
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/* If opcode is a non-RST (e.g. CALL nnn = 0xCD), full fidelity
|
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would require additional INTA bus cycles to fetch the
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operand bytes — not implemented yet. Treat as a NOP. */
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return;
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}
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|
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if (G.halted) {
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|
|
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|
|
@ -414,31 +414,50 @@ describe('Intel 8080 chip', () => {
|
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});
|
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|
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describe('interrupts', () => {
|
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it.skipIf(skip)('INT pin triggers RST-vector when EI was executed', async () => {
|
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it.skipIf(skip)('INT pin + INTA bus cycle vectors via RST opcode jammed on bus', async () => {
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// EI ; loop: NOP ; JMP loop
|
||||
// ISR at 0x0038 (RST 7): MVI A, 0x55 ; STA 0x8000 ; HLT
|
||||
// ISR at 0x0028 (RST 5): MVI A, 0x55 ; STA 0x8000 ; HLT
|
||||
const program = new Uint8Array(0x40);
|
||||
program.fill(I8080.NOP);
|
||||
program[0x00] = I8080.EI;
|
||||
program[0x01] = I8080.JMP; program[0x02] = 0x01; program[0x03] = 0x00;
|
||||
program[0x38] = I8080.MVI_A; program[0x39] = 0x55;
|
||||
program[0x3A] = I8080.STA; program[0x3B] = 0x00; program[0x3C] = 0x80;
|
||||
program[0x3D] = I8080.HLT;
|
||||
program[0x28] = I8080.MVI_A; program[0x29] = 0x55;
|
||||
program[0x2A] = I8080.STA; program[0x2B] = 0x00; program[0x2C] = 0x80;
|
||||
program[0x2D] = I8080.HLT;
|
||||
|
||||
const { board, ram } = await bootCpu(program);
|
||||
// Run a few cycles to let EI take effect.
|
||||
|
||||
// INTA bus driver. Two-stage:
|
||||
// 1. Watch SYNC. When high, sample the status byte. If INTA bit
|
||||
// is set (status 0x23 = M1 + INTA + WO̅), latch a flag.
|
||||
// 2. Watch DBIN AFTER bootCpu (so we register last and our drive
|
||||
// overrides the fake_rom's drive on the same DBIN edge).
|
||||
// When DBIN rises during a latched INTA cycle, drive the RST
|
||||
// opcode on D — the chip will read it.
|
||||
let intaPending = false;
|
||||
board.watchNet('SYNC', (high) => {
|
||||
if (!high) return;
|
||||
const status = board.readBus('D', 8);
|
||||
intaPending = (status & 0x01) !== 0;
|
||||
});
|
||||
board.watchNet('DBIN', (high) => {
|
||||
if (!high || !intaPending) return;
|
||||
intaPending = false;
|
||||
const RST5 = 0xEF;
|
||||
for (let i = 0; i < 8; i++) {
|
||||
board.setNet(`D${i}`, ((RST5 >> i) & 1) === 1);
|
||||
}
|
||||
});
|
||||
|
||||
// Let EI + a few NOPs run.
|
||||
board.advanceNanos(CLOCK_NS * 20);
|
||||
// Pulse INT high. The 8080 expects an RST opcode on the data bus
|
||||
// during interrupt acknowledge; our fake ROM doesn't model INTA.
|
||||
// For a first-cut test we mark this todo until we extend the fake
|
||||
// ROM with an INTA hook.
|
||||
// Pulse INT high.
|
||||
board.setNet('INT', true);
|
||||
board.advanceNanos(CLOCK_NS * 50);
|
||||
board.advanceNanos(CLOCK_NS * 5);
|
||||
board.setNet('INT', false);
|
||||
// Let the ISR run to HLT.
|
||||
board.advanceNanos(CLOCK_NS * 200);
|
||||
|
||||
// This assertion will only pass once the chip + harness understand
|
||||
// the INTA bus protocol. Until then it's expected to fail/skip.
|
||||
expect(ram.peek(0x8000)).toBe(0x55);
|
||||
board.dispose();
|
||||
});
|
||||
|
|
|
|||
Loading…
Reference in New Issue