test_intel: status doc — 93/105 passing across phases A/B/E + partial C

Final tally for this session's work:
- Started at 37 passing tests after the initial 5-CPU baseline.
- Phase A (8080 INTA bus protocol): +1 test.
- Phase B (Z80 CB/DAA/RLD/ADC HL/CPI + X/Y flags): +10 tests.
- Phase C partial (rom-1m, 8255 PPI, 8251 USART): +13 tests.
- Phase E (8086 string ops, MUL/DIV, BCD, port I/O, shifts, etc):
  +7 tests.
Total: 93 passing, 12 todo, 0 failed.

Plan tracked in autosearch/18_complete_emulation_plan.md. Phases D
(4004/4040 I/O completion using deferred 4001/4002 chips), F (real
software validation: CPUDIAG/ZEXDOC), and G (cycle accuracy) remain
as future iterations.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

test/test_intel/00_README.md

@@ -117,10 +117,13 @@ address and data pins, just like in a real PCB.
 | **test_8086/**| ✅ 13  | ✅    | **🎯 3 passing + 10 todo. ~750 LOC clean-room from Intel iAPX 86,88 User's Manual (Oct 1979).** Bus protocol + reset to 0xFFFF0 + ModR/M decode + ~50 opcodes (MOV/ALU/Jcc/CALL/RET/LOOP/etc.). Deferred: string ops, MUL/DIV, BCD, port I/O, interrupts. |
 | **test_z80/**| ✅ 13  | ✅    | **🎯 11 passing + 2 todo (IM 2 vectoring, ZEXDOC). ~600 LOC clean-room from Zilog UM008003 + Sean Young's "Undocumented Z80 Documented" v0.91.** Full bus + ISA + INT + NMI + LDIR + IX/IY + EXX + IM 0/1/2. Deferred: undocumented X/Y flags, MEMPTR, full DAA, CB-prefix bit ops. |
 
-Total: **80 tests authored, 63 passing** (8080: 18, Z80: 11,
-4004: 9, 4040: 5, 8086: 3, rom-32k: 6, ram-64k: 7, latch-8282: 4),
-0 skipping, 17 todo (deferred integration / extended-spec tests).
-Zero failures. **All 5 retro Intel/Zilog CPUs + all 3 bus device
-chips from the original plan are now implemented and validated.**
-No velxio core source has been modified. Run `npm test` from
-`test/test_intel/` to confirm.
+Total: **105 tests authored, 93 passing** (8080: 18, Z80: 21,
+4004: 9, 4040: 5, 8086: 10, rom-32k: 6, ram-64k: 7, latch-8282: 4,
+rom-1m: 4, 8255-ppi: 5, 8251-usart: 4), 0 skipping, 12 todo
+(deferred ZEXDOC/CPUDIAG integration + a few corner-case opcodes).
+Zero failures. **All 5 retro Intel/Zilog CPUs + 6 bus device chips
+implemented and validated.** Phase plan in
+`autosearch/18_complete_emulation_plan.md` tracks remaining work
+(4001/4002/8253/8259 chips for canvas demos; CPUDIAG/ZEXDOC software
+validation in Phase F). No velxio core source has been modified.
+Run `npm test` from `test/test_intel/` to confirm.