125 lines
7.1 KiB
TypeScript
125 lines
7.1 KiB
TypeScript
/**
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* Phase 3 — multi-chip RESET ordering race (project/multichip-bus/).
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*
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* The Galaksija example boots through a power-on-reset chip (reset-gen) wired to
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* the Z80's RESET line, NOT a manual RESET pulse like the other tests. reset-gen
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* holds RESET low, then a one-shot timer drives it high to release the CPU.
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*
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* The Z80 chip releases from reset on the RISING EDGE of RESET (vx_pin_watch).
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* In the browser the 7 chips instantiate ASYNCHRONOUSLY and the host feeds a
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* wall-clock now, so reset-gen (small, loads first) fires its release timer on
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* its first tick — potentially BEFORE the larger Z80 finishes registering its
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* RESET watch. If the Z80 misses that one rising edge it stays in reset forever
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* and the machine never boots (the live symptom: a frozen, garbled display).
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*
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* This reproduces both orderings:
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* - race: reset-gen releases RESET, THEN the Z80 is created -> must still boot
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* - safe: the Z80 is created first, THEN reset-gen releases -> boots
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* Both must boot once the Z80 samples the RESET level (not just the edge).
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*/
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import { describe, it, expect, beforeEach, afterEach } from 'vitest';
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import { readFileSync, existsSync } from 'node:fs';
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import { fileURLToPath } from 'node:url';
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import { PinManager } from '../simulation/PinManager';
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import { ChipInstance } from '../simulation/customChips/ChipRuntime';
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import {
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resolveChipNetKey, setChipBusEnabledForTest, resetChipNetIndexForTest, type ChipNetState,
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} from '../simulation/customChips/chipNets';
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import { syntheticChipPin } from '../simulation/customChips/syntheticPins';
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import { resetBusNets } from '../simulation/customChips/busNets';
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const f = (n: string) => fileURLToPath(new URL(`./fixtures/chipbus/${n}`, import.meta.url));
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const P = {
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z80: f('z80.wasm'), rom: f('galaksija-rom.wasm'), ram: f('galaksija-ram.wasm'),
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inv: f('inverter.wasm'), disp: f('galaksija-display.wasm'), rst: f('reset-gen.wasm'),
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};
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const have = Object.values(P).every(existsSync);
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const range = (n: number) => Array.from({ length: n }, (_, i) => i);
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const Z80 = [...range(16).map((i) => `A${i}`), ...range(8).map((i) => `D${i}`), 'M1', 'MREQ', 'IORQ', 'RD', 'WR', 'RFSH', 'HALT', 'WAIT', 'INT', 'NMI', 'RESET', 'BUSREQ', 'BUSACK', 'CLK', 'VCC', 'GND'];
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const ROM = [...range(13).map((i) => `A${i}`), ...range(8).map((i) => `D${i}`), 'CE', 'OE'];
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const RAM = [...range(16).map((i) => `A${i}`), ...range(8).map((i) => `D${i}`), 'CE', 'OE', 'WE', 'VCC', 'GND'];
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const INV = ['IN', 'OUT'];
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const DISP = [...range(14).map((i) => `A${i}`), ...range(8).map((i) => `D${i}`), 'WR'];
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const RST = ['RESET', 'WAIT', 'BUSREQ', 'INT', 'NMI'];
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const W: ChipNetState['wires'] = [];
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const wire = (a: string, ap: string, b: string, bp: string) => (W as { start: { componentId: string; pinName: string }; end: { componentId: string; pinName: string } }[]).push({ start: { componentId: a, pinName: ap }, end: { componentId: b, pinName: bp } });
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for (const i of range(13)) for (const c of ['rom', 'ram', 'disp']) wire('z80', `A${i}`, c, `A${i}`);
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wire('z80', 'A13', 'rom', 'CE'); wire('z80', 'A13', 'inv', 'IN'); wire('inv', 'OUT', 'ram', 'CE');
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wire('z80', 'A13', 'disp', 'A13');
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for (const i of range(8)) for (const c of ['rom', 'ram', 'disp']) wire('z80', `D${i}`, c, `D${i}`);
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wire('z80', 'RD', 'rom', 'OE'); wire('z80', 'RD', 'ram', 'OE');
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wire('z80', 'WR', 'ram', 'WE'); wire('z80', 'WR', 'disp', 'WR');
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// reset-gen drives the Z80 control lines (the example wiring).
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wire('rst', 'RESET', 'z80', 'RESET'); wire('rst', 'WAIT', 'z80', 'WAIT');
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wire('rst', 'BUSREQ', 'z80', 'BUSREQ'); wire('rst', 'INT', 'z80', 'INT'); wire('rst', 'NMI', 'z80', 'NMI');
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const STATE: ChipNetState = { wires: W, components: ['z80', 'rom', 'ram', 'inv', 'disp', 'rst'].map((id) => ({ id, metadataId: 'custom-chip' })), boards: [] };
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const pk = (c: string, p: string): number => resolveChipNetKey(STATE, c, p) ?? syntheticChipPin(c, p);
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const wf = (c: string, pins: string[]) => new Map(pins.map((p) => [p, pk(c, p)] as [string, number]));
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const cellLit = (fb: Uint8Array, col: number, row: number): number => {
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let n = 0;
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for (let y = 0; y < 8; y++) for (let x = 0; x < 8; x++) if (fb[((row * 8 + y) * 256 + (col * 8 + x)) * 4 + 1] > 0x80) n++;
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return n;
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};
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describe.skipIf(!have)('chipbus Phase 3 — RESET ordering race via reset-gen', () => {
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beforeEach(() => { setChipBusEnabledForTest(true); resetChipNetIndexForTest(); resetBusNets(); });
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afterEach(() => { setChipBusEnabledForTest(null); resetChipNetIndexForTest(); resetBusNets(); });
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const mk = async (pm: PinManager, k: keyof typeof P, id: string, pins: string[], display?: { width: number; height: number }) =>
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ChipInstance.create({ wasm: new Uint8Array(readFileSync(P[k])), componentId: id, pinManager: pm, wires: wf(id, pins), display });
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// Wall-clock-ish: a huge `now` so reset-gen's 2 ms one-shot is already due on
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// the first tick (exactly what the browser feeds via performance.now()*1e6).
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const NOW = BigInt(120_000 * 250);
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it('RACE: reset-gen releases RESET before the Z80 exists — must still boot', async () => {
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const pm = new PinManager();
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// reset-gen loads and ticks FIRST: it drives RESET low at setup then high on
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// this tick — the rising edge happens with no Z80 watching yet.
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const rst = await mk(pm, 'rst', 'rst', RST); rst.start();
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rst.tickTimers(NOW); // release RESET high (edge lost — nothing is listening)
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// Only now does the (larger) Z80 finish instantiating + register its watch.
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const z80 = await mk(pm, 'z80', 'z80', Z80); z80.start();
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(await mk(pm, 'rom', 'rom', ROM)).start();
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(await mk(pm, 'ram', 'ram', RAM)).start();
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(await mk(pm, 'inv', 'inv', INV)).start();
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const disp = await mk(pm, 'disp', 'disp', DISP, { width: 256, height: 128 });
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let fb: Uint8Array | null = null; disp.onFramebufferUpdate((r) => { fb = r as Uint8Array; }); disp.start();
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rst.tickTimers(NOW); // re-assert reset-gen outputs (WAIT/INT/NMI high)
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z80.tickTimers(NOW); // boot
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disp.tickTimers(50_000_000n);
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expect(fb).not.toBeNull();
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// The ">" prompt at col 0 of row 1 proves the CPU left reset and ran the ROM.
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expect(cellLit(fb!, 0, 1), 'the BASIC ">" prompt rendered — the Z80 left reset').toBeGreaterThan(4);
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z80.dispose(); rst.dispose(); disp.dispose();
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}, 60_000);
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it('SAFE: Z80 created first, then reset-gen releases RESET — boots', async () => {
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const pm = new PinManager();
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const z80 = await mk(pm, 'z80', 'z80', Z80); z80.start();
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(await mk(pm, 'rom', 'rom', ROM)).start();
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(await mk(pm, 'ram', 'ram', RAM)).start();
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(await mk(pm, 'inv', 'inv', INV)).start();
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const disp = await mk(pm, 'disp', 'disp', DISP, { width: 256, height: 128 });
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let fb: Uint8Array | null = null; disp.onFramebufferUpdate((r) => { fb = r as Uint8Array; }); disp.start();
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const rst = await mk(pm, 'rst', 'rst', RST); rst.start();
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rst.tickTimers(NOW); // NOW the rising edge is delivered to a live watch
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z80.tickTimers(NOW);
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disp.tickTimers(50_000_000n);
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expect(fb).not.toBeNull();
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expect(cellLit(fb!, 0, 1), 'the BASIC ">" prompt rendered').toBeGreaterThan(4);
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z80.dispose(); rst.dispose(); disp.dispose();
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}, 60_000);
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});
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