velxio/frontend/src
David Montero 8f148e836d fix(sim): a net is a set of pins, and a part's own line belongs to the part
Hardening pass on 57325aa, which fixed the reported HC-SR04 divider but did it
by returning the first answer any branch produced. Five topologies people
really draw break under that rule, and each one now has a test that fails on
57325aa and passes here:

  - a ground tie point almost always carries something else (a button's
    pull-down). Reaching a rail has to END the walk, or a grounded pin resolves
    to whatever GPIO that pull-down hangs off. Same through a breadboard rail;
  - two custom chips on one wire stopped sharing a chipbus net key, because a
    nested frame answered with its own neighbour's per-endpoint key before the
    root could mint the net-canonical one;
  - a chip one hop away ended the search before a real GPIO on the same node
    was ever looked at;
  - a node first reached deep, where the hop budget cut it short, was never
    re-walked when a shorter route arrived.

So the walk now models what a net IS. It collects the whole NODE (every pin
joined without crossing a component: the wires, and a breadboard strip's
holes), then judges the set: a driven pad wins outright; a supply pad means the
node IS the rail and the walk stops there; only then does it cross a passive to
the next node, where a rail is the weaker answer that lets a level-shifted
sensor resolve. Wires, components and breadboard groups are indexed per store
array, and a driven pad short-circuits collection — the common case is now
0.08 ms/pin on a 300-wire canvas, better than before this work started, with
the shared-rail worst case at ~2 ms.

Second half: a part that models its own line keeps it, on every board.
connectDigitalInputsToMcu thresholds the solved node into every input pin, and
its `sourcedNets` gate only ever protected part-driven lines by accident — it
holds while no component sits on the net, and stops the moment the user adds
the pull-up or the divider real hardware needs. Then the connector pins the
line an HC-SR04 or a DHT22 is answering on. simulation/partPinOwnership records
what each part drives (implicitly, through the simulator it is handed) and the
connector skips those pins; the ESP32 bridge answers the same question for
sensors the backend or an engine emulates, through a new optional `ownsPin`
seam. Parts SPICE can describe never claim anything, so a mis-wired button
still reads stuck — that property is why spiceDrivenInputs exists.

Also: setSensors merges per FIELD, so the coarser registration path can no
longer drop the finer one's echo_pin; the ESP32 bridge's guard is narrowed to
the single-wire sensor types, since an ePaper's DC pin or a keypad row must
stay drivable; and the Mega and Pico W pin maps get the supply-pad guard the
other boards have, where '5V' parsed as D5 and '3V3' as D3.

Verified in a browser against a local build of this tree, driving the real app:
HC-SR04 and DHT22, direct wiring and level-shifted, on Uno (avr8js), Pico
(rp2040js), ESP32 (esp32js and QEMU) and ESP32-S3 (esp32s3js) — see
scripts/sensor-wiring-matrix.mjs in velxio-prod.
2026-08-23 01:23:41 +02:00
..
__pro_stub__ prerender: initialise i18n for SSR; example pages mounted under their route 2026-08-18 18:35:01 +02:00
__tests__ fix(sim): a net is a set of pins, and a part's own line belongs to the part 2026-08-23 01:23:41 +02:00
assets
…
components fix(sim): a net is a set of pins, and a part's own line belongs to the part 2026-08-23 01:23:41 +02:00
data feat(micropython): install libraries from the micropython-lib index (#214) 2026-08-18 21:50:10 +02:00
desktop
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hooks feat(simulator): tilt and battery controls for boards that carry an IMU or a gauge 2026-08-09 23:48:56 +02:00
i18n flash: compile before flashing, stale-build warning, i18n dialog, entitlement seam (#207) 2026-08-18 20:21:57 +02:00
lib fix(spice): overlay boards were skipped before a single volt was injected 2026-08-22 05:13:41 +02:00
pages fix(editor): the workspace panel stacks its actions, and the toolbar stops growing a hole 2026-08-18 18:42:38 +02:00
services feat(boards): let a board declare the RAM and flash it is physically fitted with 2026-08-20 19:48:24 +02:00
simulation fix(sim): a net is a set of pins, and a part's own line belongs to the part 2026-08-23 01:23:41 +02:00
store fix(sim): a net is a set of pins, and a part's own line belongs to the part 2026-08-23 01:23:41 +02:00
tokens
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types feat(firmware): say why an uploaded binary cannot find any network (#270) 2026-08-22 07:18:01 +02:00
utils fix(sim): a net is a set of pins, and a part's own line belongs to the part 2026-08-23 01:23:41 +02:00
velxio-elements
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App.css flash: compile before flashing, stale-build warning, i18n dialog, entitlement seam (#207) 2026-08-18 20:21:57 +02:00
App.tsx
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elements-register.ts
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entry-server.tsx prerender: initialise i18n for SSR; example pages mounted under their route 2026-08-18 18:35:01 +02:00
index.css
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main.tsx chore(dev): expose core stores on window in dev builds for the QA harness 2026-08-15 08:29:39 +02:00
seoRoutes.ts seo: /v2 and /v2-5 canonical to the home and out of the sitemap 2026-08-18 17:29:54 +02:00
vite-env.d.ts
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