8a1d75a96c
Three new bus-device chips, all clean-room from public Intel datasheets: - rom-1m: 64 KB ROM mapped at 0xF0000..0xFFFFF for 8086 boot. 20-bit address bus watch with out-of-range tristate. 16-byte known signature pre-loaded at the reset vector 0xFFFF0. - 8255 PPI: Mode-0 (basic I/O) only; three 8-bit ports with split upper/lower port C. Control word parsing for direction setup. Bit set/reset and Modes 1/2 deferred. - 8251 USART: async-mode UART using vx_uart_attach for bit-timing; mode word + command word + status interface; TxRDY/RxRDY/TxEMPTY status pins; DTR/RTS pass-through. Internal-reset honoured. Deferred to a follow-up Phase C+: - 4001 ROM and 4002 RAM (multi-phase 4-bit bus timing requires either an external clock-gen chip or Bus4004-equivalent host coordination that's only available in the JS test harness today). - 8253 PIT (6 modes, countdown logic). - 8259 PIC (ICW init state machine + cascade + INTA cycle). These are flagged in autosearch/18_complete_emulation_plan.md as deferred — Phase D (4004/4040 I/O) and the 8259 work depend on them landing first. Tests: test_buses 17 → 30 passing (+13). Total test_intel 73 → 86 passing, 0 failed, 17 todo. Master plan doc updated. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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| .. | ||
| autosearch | ||
| scripts | ||
| src | ||
| test_4004 | ||
| test_4040 | ||
| test_8080 | ||
| test_8086 | ||
| test_buses | ||
| test_z80 | ||
| .gitignore | ||
| 00_README.md | ||
| package-lock.json | ||
| package.json | ||
| vitest.config.js | ||