93 lines
3.4 KiB
Markdown
93 lines
3.4 KiB
Markdown
# test_4040 — Intel 4040 as a velxio custom chip
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See [../autosearch/02_intel_chips_overview.md](../autosearch/02_intel_chips_overview.md#intel-4040-1974)
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for the spec.
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## Status
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✅ **Implemented (bus skeleton + STOP/STPA).** 2/5 active tests pass;
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3 are `it.todo` deferred. ~250 LOC clean-room in `4040.c` compiled to
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`fixtures/4040.wasm`.
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Validated against Intel MCS-40 User's Manual (Nov 1974) — PDF at
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`autosearch/pdfs/mcs40_users_manual.pdf`. Cross-checked control logic
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against `markablov/i40xx` (MIT) and `Kostu96/K4004` (MIT, ships
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Busicom 141-PF firmware).
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What works:
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- Full 24-pin DIP contract per [M40] pp. 1-5/1-6 — STP, STPA, INT,
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INTA, CY, dual CMROM (CMROM0/CMROM1), dual standby Vdd1/Vdd2.
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- 8-phase frame inherited from 4004 (binary-compatible, [M40] p. 1-22).
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- STP latched at M2 → STOP FF set at X3 → STPA asserts within ~2
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instruction cycles ([M40] p. 1-10). Clock and SYNC continue per
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manual ("CPU executes NOPs in a loop").
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- INT latched at M2 with EIN active → forced JMS to PC=0x003 at X3,
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INTA asserts ([M40] p. 1-12). Vector address is fixed; no vector
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table.
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- Index register file extended to 24 × 4 bits (3 banks × 8); SB0/SB1
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bank-select FF in place though not exercised by tests.
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- 7-deep PC stack ([M40] p. 1-12) — replaces 4004's 3-deep stack.
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Deferred:
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- 14 new instructions' semantics: HLT, BBS, LCR, OR4/OR5, AN6/AN7,
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DB0/DB1, SB0/SB1, EIN/DIN, RPM (currently all decoded as NOP).
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- BBS return-from-interrupt behaviour (pop stack, restore SRC, restore
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bank FF, clear INTA).
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- DB0/DB1 ROM-bank-select with 3-cycle takeover delay.
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- HALT FF semantics (HLT opcode).
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- Interrupt-during-2-byte-instruction edge cases ([M40] open question).
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## Pin contract (24-pin DIP, real silicon)
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The 4040 is a 4004 superset; it keeps every 4004 signal and adds:
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- `INT` (interrupt request, in)
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- `STOP` (single-step, in)
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- `STOP ACK` (out)
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- Additional bank-select / index-pointer lines
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**Action item:** pull the exact 4040 pinout from a datasheet and fill
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in this table before writing `.chip.json`. Pin order matters for the
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on-canvas drag-and-drop appearance.
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| Pin | Name | Dir | Notes |
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| --- | --------- | ----- | ----- |
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| | D0..D3 | I/O | Same multiplexed nibble bus as 4004 |
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| | CLK1, CLK2| in | |
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| | SYNC | out | |
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| | RESET | in | |
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| | TEST | in | |
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| | CM-ROM0..1| out | 4040 has *two* ROM strobes (4004 has one) |
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| | CM-RAM0..3| out | |
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| | INT | in | New on 4040 |
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| | STOP | in | New on 4040 |
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| | STOP ACK | out | New on 4040 |
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| | VDD, VSS | power | |
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## Implementation plan
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1. Land the 4004 first.
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2. Fork its `.c` source into `4040.c`.
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3. Extend the register file from 16 → 24 4-bit registers.
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4. Extend the PC stack from 3-deep → 7-deep.
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5. Add the new opcodes (interrupt enable/disable, return-from-interrupt,
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stop, the extra register-pair operations).
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6. Add `INT` pin watch. On rising edge, push PC and vector to fixed
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address `[verify from datasheet]`.
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7. Add `STOP` pin watch. On rising edge, freeze the cycle timer and
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assert `STOP ACK`.
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## Target demo sketch
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Same as 4004 (LED blink), then a second sketch that uses `INT` —
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an external "button" chip drives `INT`, the 4040's ISR toggles a
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different output. Demonstrates the only feature that matters versus
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the 4004.
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## Files to create later
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- `4040.chip.json`
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- `4040.c`
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- `sketch_blink.asm`
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- `sketch_irq.asm`
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