113 lines
4.5 KiB
Markdown
113 lines
4.5 KiB
Markdown
# test_4004 — Intel 4004 as a velxio custom chip
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See [../autosearch/02_intel_chips_overview.md](../autosearch/02_intel_chips_overview.md#intel-4004-1971)
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for the chip's specs and [../autosearch/03_emulation_strategy.md](../autosearch/03_emulation_strategy.md)
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for how the bus phases map onto velxio's reactive callbacks.
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## Status
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✅ **Implemented (bus skeleton).** 4/11 active tests pass; 7 are
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`it.todo` deferred to ISA-implementation phase. ~150 LOC clean-room
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in `4004.c` compiled to `fixtures/4004.wasm`.
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Validated against Intel MCS-4 User's Manual (Feb 1973) — PDF at
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`autosearch/pdfs/mcs4_users_manual.pdf`. Cross-checked the 8-phase
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frame timing and pin-out against `markablov/i40xx` (MIT, JS) and
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`Kostu96/K4004` (MIT, C++).
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What works:
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- Full 16-pin DIP contract (D0..D3, SYNC, RESET, TEST, CMROM,
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CMRAM0..3, CLK1, CLK2, VDD, VSS).
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- 8-phase instruction frame (A1, A2, A3, M1, M2, X1, X2, X3) at
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~740 kHz nominal clock (1351 ns per phase).
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- SYNC pulses high at A1, low at A2 onwards — once per 8-clock cycle.
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- Address bus walk: D0..D3 = PC[3:0] in A1, PC[7:4] in A2, PC[11:8]
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in A3 (low-nibble first per [M4] Fig. 2 p. 6).
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- CMROM strobed high during M1 (instruction fetch).
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- PC increments at end of every cycle (NOP-equivalent — every fetched
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opcode is treated as a NOP for now).
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- RESET behaviour: held high clears all state per [M4] §III.A.5 p. 9.
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Deferred until ISA implementation phase:
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- All 46 4004 instructions (currently only NOP behaviour). Tracked in
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`it.todo` for LDM, ADD, JCN, FIM, JMS, BBL.
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- SRC chip-select latching with CMRAMᵢ strobe at X2/X3.
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- I/O group (WRM, RDM, WRR, etc.) at 0xE0..0xEF.
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- Accumulator group (CLB, CLC, IAC, ..., DAA) at 0xF0..0xFD.
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- Busicom 141-PF integration test (the canonical 4004 demo).
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## Pin contract (16-pin DIP, real silicon)
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| Pin | Name | Dir | Notes |
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| --- | --------- | ----- | ----- |
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| 1 | D0 | I/O | Multiplexed nibble bus |
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| 2 | D1 | I/O | |
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| 3 | D2 | I/O | |
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| 4 | D3 | I/O | |
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| 5 | VSS | power | GND |
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| 6 | CLK1 | in | Phase 1 clock |
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| 7 | CLK2 | in | Phase 2 clock |
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| 8 | SYNC | out | Cycle marker |
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| 9 | RESET | in | |
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| 10 | TEST | in | Conditional-jump input |
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| 11 | CM-RAM3 | out | RAM bank select |
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| 12 | CM-RAM2 | out | |
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| 13 | CM-RAM1 | out | |
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| 14 | CM-RAM0 | out | |
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| 15 | CM-ROM | out | ROM strobe |
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| 16 | VDD | power | +5 V (real chip wanted +5/-10 V split — collapsed for digital sim) |
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**Pin-numbering note:** the table above orders pins logically, not in
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the physical 1–16 DIP layout. Cross-check against an Intel 4004
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datasheet before finalising the `.chip.json`. Logged in
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[../autosearch/05_open_questions.md](../autosearch/05_open_questions.md).
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## Bus model summary
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8-cycle instruction frame. Each CLK1+CLK2 pair = one cycle. Within an
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8-cycle frame the chip drives:
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| Cycle | What's on D0..D3 | Direction |
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| ----- | ---------------- | --------- |
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| A1 | addr nibble 0 | output |
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| A2 | addr nibble 1 | output |
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| A3 | addr nibble 2 | output |
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| M1 | opcode hi nibble | input (read from ROM) |
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| M2 | opcode lo nibble | input |
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| X1 | data / operand | varies |
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| X2 | data / operand | varies |
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| X3 | data / operand | varies |
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`SYNC` rises at the start of A1 to mark the cycle frame to external
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ROM/RAM chips.
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## Target demo sketch
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A 4004 running the classic `Busicom 141-PF` 4-instruction blink loop
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that decrements a register and writes its low bit to a CM-RAM line
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driving an LED. Smallest possible "I see CPU activity" demo.
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## Implementation outline
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1. `4004.chip.json` — declare 16 pins above, plus a `program_rom`
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property (hex string, max 4 KB).
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2. `4004.c`:
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- `chip_setup()`: register pins, allocate `cpu_state_t`, load ROM
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from property, start a repeating timer at the instruction-cycle
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period.
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- `on_cycle_tick()`: walk the 8-phase state machine, drive pins
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accordingly. For ROM reads this is internal (we hold the ROM in
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chip memory for the first cut); for RAM reads we'll route through
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external RAM chips on the canvas.
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3. Test with a hand-assembled ROM that lights an LED via CM-RAM0 →
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external 4002-equivalent RAM (or, simpler, drive an LED directly
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off CM-RAM0 since it's a real output pin).
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## Files to create later
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- `4004.chip.json`
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- `4004.c`
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- `sketch.asm` (hand-assembled demo) and `rom.hex` (assembled bytes)
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- `test_4004.test.ts` mirroring the style of
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`test/test_custom_chips/test/`
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