Replace the synthesised-RST-7 stub with a real INTA bus cycle. When
int_pending && IME, the chip emits status byte 0x23 on D during T1
(M1+INTA+WO̅) and samples the RST opcode external hardware drives on
the data bus during DBIN. Decodes RST n (0xC7..0xFF) and push+vectors.
Multi-byte INTA opcodes (CALL nnn) deferred.
Test rewrites the INT case to install a fixture INTA driver: snoop
SYNC + status byte, latch a pending flag, drive RST 5 (0xEF) on the
data bus during the next DBIN edge. Driver registers AFTER fake_rom
so its late drive overrides fake_rom's program-byte drive on the
same DBIN edge.
Tests: 8080 17→18 passing; test_intel 63→64 passing.
Adds master plan doc autosearch/18_complete_emulation_plan.md
covering phases A-G (this commit completes phase A).
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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