All 46 4004 instructions implemented per MCS-4 manual ([M4] Table V):
- ALU: NOP, INC Rn, ADD/SUB Rn, LD/XCH Rn, IAC/DAC, RAL/RAR, CMA, CMC,
STC, CLB, CLC, TCC, TCS, DAA, KBP
- Memory/IO: SRC Pn (no-op stub), I/O group (WRM/WMP/WRR/WPM/WR0..3,
RDM/RDR/ADM/RD0..3, SBM) all decoded; RAM-side effects stubbed
pending real 4001/4002 chips
- Control flow: JUN (12-bit jump), JMS (push+jump), BBL (pop+ACC),
JCN with full C1/C2/C3/C4 condition logic, ISZ in-page branch,
FIM (load reg pair), FIN/JIN (indirect via P0)
- DCL: load CMRAM bank select
Plus a Bus4004 helper class in 4004.test.js that mirrors a 4001 ROM
chip — pre-drives D0..D3 with the appropriate nibble during M1/M2,
tracks observed PC via the chip's A1/A2/A3 address-bus drives. This
mechanism lets the test feed arbitrary opcode streams without
needing a separate 4001 ROM chip on the canvas.
5 new ISA tests promoted from it.todo to passing:
- NOP advances PC by 1
- JUN jumps to 12-bit target
- JMS+BBL stack push/pop
- JCN with C4 jumps when TEST is logic-0
- JCN does not jump when condition false
3 it.todo remain: LDM, FIM, Busicom-style integration. These need
accumulator-state observability (a fake 4002 RAM via SRC+WRM) to
test, which is deferred.
Total test_intel: 52 passing (was 43), 0 failed, 25 todo.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
Companion chip for 8086 minimum-mode boards that demultiplexes
AD0..AD15 → A0..A15 under control of ALE. ~80 LOC clean-room from
the public Intel 8282/8283 datasheet.
Pin contract (20-pin DIP): DI0..7 in, DO0..7 out, STB strobe, OE̅
output enable, VCC, GND. Behaviour:
STB=1, OE̅=0 → DO follows DI (transparent)
STB falling → latch held while STB=0
OE̅=1 → DO pins released (modelled as VX_INPUT)
Tests: 4/4 passing (pin contract, transparent mode, latch hold,
output enable). Brings test_intel total to 47 passing.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
The two earliest commercial Intel CPUs as velxio custom chips:
- 4004.c (~150 LOC): 16-pin DIP, 8-phase frame (A1..X3), SYNC at A1
with PC nibble walk on D0..D3 (low-first per MCS-4 Fig. 2), CMROM
strobe during M1. ISA decoded as NOP for now — full 46-instruction
set deferred to ISA phase.
- 4040.c (~250 LOC): 24-pin DIP per MCS-40 pp. 1-5/1-6 (STP/STPA/INT/
INTA/CY/dual CMROM/dual standby Vdd). 4004-compatible bus + STP
latched at M2 → STPA asserts at X3 + INT forced JMS to PC=0x003.
14 new opcodes decoded as NOP for now.
Test refinements (analogous to bootCpu fix from 8080 work):
- bootChip no longer advances time post-RESET so first observed cycle
starts at A1 of cycle 0 with PC=0.
- SYNC sampler latches on first edge (was over-collecting on
subsequent SYNC pulses).
- 4040 test renamed STOP→STP, STOPACK→STPA per MCS-40 datasheet pin
names; added INTA, CY, VDD1, VDD2 pins; SYNC-stops assertion
removed (manual: STOP mode keeps clock and SYNC running).
Brings test_intel suite from 37 to 43 passing tests; 0 failures;
remaining 3 active are 8086 (deferred), 29 todo are intentional
deferred integration tests.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
Authoritative spec docs cite Intel MCS-4 (Feb 1973) and MCS-40 (Nov 1974)
manuals page-by-page. Reference-implementations doc surveys four
permissively-licensed open-source emulators (markablov/i40xx,
Kostu96/K4004, lpg2709/emulator-Intel-4004, alshapton/Pyntel4004) for
cross-validation, explicitly excluding GPL sources (MAME mcs40,
carlini/intel-4004-in-4004-bytes-of-c).
Critical findings:
- 4040 interrupt vector is fixed at PC=0x003 (no vector table).
- New 4040 instructions all live at OPR=0000, OPA=0x01..0x0E.
- 4004 DAA (opcode 0xFB) is single-nibble, very different from 8080.
- 4040 STP/STPA/INTA pin names per datasheet (not STOP/STOPACK).
- R16..R23 are not directly named — they're Bank-1 R0..R7 via SB0/SB1.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
- Added tcp_nat.py to handle TCP NAT, implementing the three-way handshake, data flow, and connection state management.
- Introduced udp_nat.py for UDP NAT, managing chip-initiated datagrams and maintaining flow state.
- Created integration tests in test_picow_net_bridge.py to validate the functionality of the TCP and UDP NAT implementations, including ARP, DHCP, ICMP, and DNS interactions.
- Introduced SVG layout dimensions for Phase 1 (B/W mono) and Phase 2 (colour) ePaper panels, detailing active areas, bezels, and pin layouts.
- Developed a phased emulation plan outlining the architecture and deliverables for different panel types, including SSD168x and UC81xx.
- Created a canonical "Hello, World!" sketch for the 1.54" ePaper panel, ensuring compatibility across ESP32, Raspberry Pi Pico, and Arduino Uno.
- Implemented a pure Python SSD168x decoder to validate SPI command sets and framebuffers against specifications.
- Added tests for compiling the hello-world sketch across supported boards and for the SSD168x protocol to ensure correct framebuffer behavior.
- Implemented handshake tests to validate initial bus state and register responses.
- Created end-to-end tests for Pico W LED blinking using MicroPython firmware.
- Added SDPCM framing tests to ensure proper encoding and decoding of control frames.
- Developed IOCTL tests to verify command responses and state changes in the emulator.
- Established a full lifecycle test for WiFi operations, including scanning, connecting, and packet handling.
- Introduced TypeScript configuration for test files to ensure compatibility and strict type checking.
- Implemented `esp32_spi_chip_demo.ino` to demonstrate SPI communication with a 74HC595 shift register.
- Created `esp32_uart_chip_demo.ino` for UART loopback testing with ROT13 transformation.
- Added Python tests for compiling chips and sketches, ensuring valid WASM output and successful compilation for various board families.
- Developed end-to-end tests for ESP32 with custom chips using I2C and SPI, validating synchronous communication through the backend.
- Introduced GPIO bridge tests to verify serial communication and GPIO state changes.
- Ensured all tests validate the expected behavior of the custom chips and their interaction with the ESP32 firmware.
https://github.com/kritishmohapatra/100_Days_100_IoT_Projects
- Introduced `_lib.py` containing shared validators for board support and static source analysis for MicroPython projects.
- Added `conftest.py` to configure pytest for the test suite, simplifying import paths.
- Created `NOT_SUPPORTED.md` files for two projects indicating they cannot be emulated in Velxio due to lack of source code.
- Implemented unit tests for the unsupported projects to verify the presence of the NOT_SUPPORTED marker and source preservation.
Fixes the user-reported bug where two RPi Pico W boards wired GP0↔GP1
running SerialPassthrough don't communicate. Replaces the broken
broadcast-style cross-board logic in addBoard (only routed AVR↔Pi3B,
ignored wires entirely, no RP2040↔anything path) with a wire-aware
Interconnect singleton.
Architecture: digital pin transitions are the lowest-common-denominator
abstraction. Each simulator's hardware peripherals (UART/I2C/SPI) and
bit-banging libraries (SoftwareSerial, software I2C) decode the
transitions naturally — propagate the pin and the protocols come for
free. For cross-process boards (ESP32 backend QEMU, Pi3B QEMU) a
byte-level shortcut is additionally enabled on hardware-UART pin
pairs to handle high-baud links over WebSocket latency.
Implementation:
- New simulation/Interconnect.ts singleton subscribes to wire/board
changes via the Zustand store. Handlers per tier: browser-sim →
pinManager.onPinChange, ESP32 → Esp32Bridge.sendPinEvent, Pi3B →
bridge.sendPinEvent. Re-entrancy guard via per-(board,pin) Set.
- New utils/boardProtocols.ts classifies pins (uart-tx, i2c-sda, etc.)
per board kind, used as optimization hint for the byte shortcut.
- types/wire.ts: added signalType field, exports WireSignalType /
WireColorMap (fixes a pre-existing TS import error in wireColors).
- Deleted the bridgeMap/simulatorMap broadcast forEach blocks in
addBoard. Initial board + future boards register with Interconnect
via setInterconnectRuntime + store subscription.
- PinManager.resetPinStates() helper for test isolation.
Tests (16 new files, 96 tests, all passing):
- Per-pair × per-protocol matrix: dual-arduino-digital,
dual-pico-digital, arduino-pico-digital, triple-pico-digital-chain,
dual-arduino-hw-uart, dual-arduino-software-serial,
arduino-pico-mixed-uart, arduino-esp32-uart, dual-esp32-uart,
pi3-pico-uart, arduino-pico-i2c, arduino-arduino-spi,
interconnect-routing, dual-arduino-multi-protocol (UART+I2C+SPI+
digital + concurrent), dual-pico-multi-protocol (UART0+UART1 alt+
I2C0+I2C1+SPI0+digital + 3-Pico star topology)
- Updated dual-pico-serial-passthrough to assert correct behaviour
- Backend test/multi_board_esp32/test_dual_esp32_serial.py for two
real QEMU instances (skip-graceful when lcgamboa lib absent)
Verified: 1107/1107 tests pass, zero regressions, vite build OK.
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
Track per-user, per-project, and per-board usage to inform pricing tier
decisions. Adds an admin dashboard with KPIs (DAU/WAU/MAU, totals,
success rate), time-series charts for compiles/runs, board family +
FQBN breakdowns, "board diversity" pie chart (key freemium signal),
top users/projects, and per-country breakdown via Cloudflare's
CF-IPCountry header. Admin can now also view private projects.
Backend:
- New UsageEvent table (append-only event log with user_id, project_id,
event_type, board_fqbn/family, country, error_kind, duration_ms)
- Aggregate counters on User (total_compiles/runs/errors, last_active,
signup_country, last_country) and Project (compile/run/update counts,
last_compiled/run timestamps) kept in sync by MetricsService for O(1)
dashboard reads
- 10 admin endpoints under /api/admin/metrics/{overview, timeseries,
boards, board-diversity, top-users, top-projects, countries,
users/{id}, projects/{id}}
- POST /api/metrics/run for client-side run telemetry
- Country detection via cf-ipcountry header (no DB / no API calls)
- Auto-migrations in lifespan for legacy DBs
Frontend:
- recharts-powered Dashboard tab with KPI cards and 4 charts
- New Boards tab with per-family + per-FQBN breakdown
- Country column with flag emoji on Users tab
- Top countries card on Dashboard
- compileCode now forwards project_id; Run button reports via WS
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
A user (st_stefanov on Discord) reported the manual setup steps clone
avr8js, wokwi-elements, and rp2040js but skip wokwi-boards. The frontend
imports board.svg assets from wokwi-libs/wokwi-boards/boards/* (ESP32
DevKit V1, ESP32-S3, ESP32-C3, Pi Pico W, etc.), so without that repo
the Vite build fails on missing imports.
Dockerfile.standalone:77 already clones it; the README's Option C
(manual setup) was the only path missing the line. wokwi-boards is
asset-only — no npm install or build step needed.
Registers test_esp32_spice_photodiode.mjs (added in the previous commit)
in the ESP32 + ngspice section of the backend e2e workflow, with a 150s
timeout to accommodate ESP32 firmware compile + QEMU boot.
Follows the same pattern as test_esp32_spice_analog.mjs and
test_esp32_spice_ntc_bridge.mjs: compile an ESP32 sketch on-the-fly via
/api/compile/, boot QEMU through the backend WebSocket, and sweep lux
levels while verifying analogRead() returns what ngspice solved.
The netlist uses the exact photodiode cards emitted by
frontend/.../componentToSpice.ts (D_<id> + I_<id>_ph + DPHOTO model), so
any drift in the frontend SPICE mapper surfaces here.
Validated against the live Docker container — lux=0/1000/2500 produce
raw=4095/2854/992, matching the expected 4095/2854/993 within ±1 LSB
and monotonically decreasing with brightness as expected.
The package-lock.json churn is a pre-existing drift: eecircuit-engine
was in package.json but missing from the lock — npm install re-added it.
Companion workflow change (registering the test in backend-e2e-tests.yml)
lives in a separate commit that requires a PAT with workflow scope to push.
Mirrors the /v2 page structure but targets the 2.5 launch: ngspice-WASM
analog simulation, hybrid digital + analog co-simulation with Arduino /
ESP32 / RP2040, expanded component catalog, live instruments, 40 new
analog/hybrid examples.
- Reuses Velxio2Page.css + SEOPage.css — no new stylesheet to maintain
- Adds SoftwareApplication, BreadcrumbList, and FAQPage JSON-LD for
rich-results eligibility
- Registers the route in App, entry-server (SSR prerender), and
seoRoutes (sitemap, priority 0.95 / changefreq weekly)
The SPICE emitter already reads properties.lux (default 500, 100 nA/lux)
but the UI had no way to set it — the static dialog rejected the "range"
control type and there was no entry in SENSOR_CONTROLS for the live panel.
- Add photodiode entry in SENSOR_CONTROLS (slider 0-1000 lux)
- Register a minimal PartSimulationRegistry handler that forwards slider
values via emitPropertyChange so the netlist memo invalidates
- Switch the photodiode lux control from "range" to "number" so the
static ComponentPropertyDialog renders an editable input
Loading an analog-only example removes every board. The single-board
branch of loadExample then called setBoardType, which only maps over
existing entries in boards[] and silently did nothing when the array
was empty — components rendered but no board. Fall back to addBoard +
setActiveBoardId when there are no boards.
- Modified the index file to reflect the new naming convention for Velxio components.
- Changed JSX declarations to use 'velxio-' prefix for various components.
- Updated component overrides to replace 'wokwi-' with 'velxio-' for logic gates and other components.
- Adjusted SVG generation script to use 'velxio-' prefix for BMP280 and Raspberry Pi components.
- Marked submodules as dirty in QEMU and RP2040 libraries.
- Added .prettierignore and .prettierrc.json for consistent code formatting.
- Introduced InstrumentComponent with support for Voltmeter and Ammeter, including pin information handling.
- Introduced RelayElements for SPDT relay representation.
- Added Resistor component for adjustable resistance in ohms.
- Created RiscVBoard component for visualizing a RISC-V chip.
- Implemented TransistorElements for BJT and MOSFET packages.
- Added Capacitor and CapacitorElectrolytic elements for capacitors.
- Introduced Inductor element for inductor representation.
- Updated index file to export new custom elements.
- Implemented a script to inject passive-component preset variants into `scripts/component-overrides.json`, including resistors, capacitors, and inductors with custom names and thumbnails.
- Added a new custom element `<wokwi-capacitor-electrolytic>` representing a polarized aluminum-can capacitor with appropriate SVG representation.
- Updated metadata generation to accommodate new component names and thumbnails for better user experience in the component picker.
- Marked submodules `qemu-lcgamboa` and `rp2040js` as dirty to reflect local changes.
- Replaced syncStoreProperty function with emitPropertyChange to decouple parts from Zustand store.
- Updated relay component mapping to ensure proper handling of coil and contact states.
- Added new test cases for half-wave rectifier and relay-controlled LED to ensure correct functionality.
- Introduced InlineComponentSVGs for schematic-style icons of various components.
- Updated submodule references for qemu-lcgamboa, rp2040js, and wokwi-elements to indicate dirty state.
- Implement `ammeter-waveform.test.ts` to validate AC readings from a sine wave source.
- Create `capacitor-charge-transient.test.ts` to test the charging response of an RC circuit driven by a microcontroller pin.
- Introduce `esp32-rectifier-integration.test.ts` for testing rectifier behavior using QEMU and ESP32.
- Add helper functions in `esp32RectifierE2E.ts` for the rectifier test harness.
- Develop `voltmeter-waveform.test.ts` to ensure correct AC and DC readings from a sine wave source.
- Implement unit tests for waveform statistics in `waveform-stats.test.ts` to validate RMS, mean, peak, and interpolation functions.
- Create `waveformStats.ts` to provide statistical functions for time-domain waveform analysis.
- Implement `serial-batching.test.ts` to verify the behavior of `createSerialBatcher`, ensuring it coalesces multiple appends into a single flush, preserves byte order, and groups by board.
- Create `spice-rectifier-integration.test.ts` to test the end-to-end functionality of the Half-Wave Rectifier example, covering the entire simulation pipeline from input building to circuit solving.
- Add `spice-rectifier-live-repro.test.ts` to reproduce a live-app failure scenario, tracing through each layer of the simulation to identify potential failure points.
- Introduce `spice-signal-generator-tran.test.ts` to validate the behavior of the signal generator and ensure correct analysis type switching based on circuit components.
- Establish `serialBatcher.ts` to implement a batching mechanism for USART output, reducing the frequency of store updates and preventing React's maximum update depth error.
- Decoupled electrical simulation from the simulator store, ensuring SPICE is always active for accurate circuit analysis.
- Removed feature flag for electrical simulation, simplifying the state management.
- Preloaded SPICE engine at app start to eliminate latency during the first solve.
- Added comprehensive tests for MOSFET PWM LED behavior and NPN transistor switch functionality, ensuring correct current flow and response to pin states.
- Implemented diagnostics for floating input nodes in RC low-pass filter circuits, addressing singular matrix issues in SPICE simulations.
- Introduced active semiconductor metadata registry for better component management and simulation fidelity.
- Updated Vite configuration to force re-bundling of local wokwi-elements after component additions.
Documents 5 issues found in production logs: RPi3 missing QEMU boot
files (51 hits), ESP32-S3 unsupported machine type, WebSocket race
condition, Google OAuth unhandled 400, and the uvicorn keepalive crash
that was mitigated in 8e3c00e.
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
fix: increase timeout for compilation requests to 180 seconds
refactor: call recalculateAllWirePositions after loading examples
chore: update subproject commit for rp2040js to dirty state
chore: update subproject commit for wokwi-elements to dirty state
generate-sitemap.mjs was only scanning examples.ts for example IDs using a
textual regex. With the 40 new circuit examples living in a separate file
(examples-circuits.ts), they were missing from the generated sitemap.xml
and therefore invisible to search engines / SSR prerender URL list.
Now the generator reads both source files and merges their example IDs.
Also includes auto-applied formatting changes to generate-component-metadata.ts.
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
Previously examples.ts pushed to exampleProjects[] after declaration, which
some bundlers can treat as dead code under aggressive tree-shaking. This
also made HMR unreliable when examples-circuits.ts changed.
Now:
const legacyExamples = [...]
export const exampleProjects = [...legacyExamples, ...circuitExamples]
Single immutable export. Guaranteed to include all 150 examples at import
time. The gallery (ExamplesGallery.tsx) and SSR prerender (entry-server.tsx)
both pick up the new circuit examples automatically.
Also adds frontend/src/__tests__/examples-circuits.test.ts with 5 assertions
to catch future regressions (all circuit ids present, no duplicates, valid
required fields, expected categories covered).
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
David Montero