velxio/test/test_intel
David Montero f429e113ab test_intel: phase D-4 — Busicom-style increment-and-blink demo
Convert the last outstanding it.todo (4004 Busicom-style program)
into a passing integration test. The Busicom 141-PF firmware itself
isn't available in-environment, so this is an original demo that
exercises the same bus paths the firmware used:

  CLB ; loop: SRC P0 ; WMP ; IAC ; JUN loop

Wires real 4004 + real 4002 chips on a shared D bus and uses the
JS-side nibble-bus driver to feed the 6-byte program. The 4002's
O0..O3 output port blinks through 0, 1, 2, 3, …, F, 0, … each
iteration. Test asserts the first 6 distinct outputs are 0..5 —
proving the loop iterates and the output port reflects each WMP-
driven ACC update faithfully.

Final state: 126 tests, 126 passing, 0 todo, 0 failed.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-05-01 03:43:24 +02:00
..
autosearch test_intel: phase D-4 — Busicom-style increment-and-blink demo 2026-05-01 03:43:24 +02:00
roms test_intel: phase F — software validation (CPUDIAG + ZEXDOC pass) 2026-04-30 20:44:17 +02:00
scripts
src test_intel: phase E — 8086 ISA expansion 2026-04-30 20:44:17 +02:00
test_4004 test_intel: phase D-4 — Busicom-style increment-and-blink demo 2026-05-01 03:43:24 +02:00
test_4040 test_intel: phase D-3 — 4040 SRC + I/O bus wiring (4004 parity) 2026-05-01 03:07:11 +02:00
test_8080 test_intel: phase D-3 + todo cleanup — 125/126 passing 2026-05-01 03:20:50 +02:00
test_8086 test_intel: phase D-3 + todo cleanup — 125/126 passing 2026-05-01 03:20:50 +02:00
test_buses test_intel: phase D-2 — 4004 SRC + I/O bus wiring end-to-end 2026-05-01 01:44:45 +02:00
test_z80 test_intel: phase D-3 + todo cleanup — 125/126 passing 2026-05-01 03:20:50 +02:00
.gitignore
00_README.md test_intel: phase D-4 — Busicom-style increment-and-blink demo 2026-05-01 03:43:24 +02:00
package-lock.json
package.json
vitest.config.js