adc99a8035
Apply the same xact_t pattern from the 4004 (phase D-2) to the 4040, so SRC and the I/O group (WRM/WMP/WRR/WPM/WR0..3/SBM/RDM/RDR/ADM/ RD0..3) drive or sample the multiplexed nibble bus during X2/X3 with CM-RAM (or CM-ROM for ROM-port ops) strobed. The 4040's two CM-ROM lines (selected by rom_bank) and its STP/INT control flow are unchanged — the bus action is staged at M2 and acted on at X2/X3, fitting cleanly inside the existing PHASE_X3 control-flow block. Two new integration tests under "4040 + 4002 RAM integration" mirror the 4004's: SRC + WMP drives the output port, and SRC + WRM/RDM round-trips a nibble through 4002 storage. Total test_intel: 117 passing, 11 todo, 0 failed (was 115). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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| .. | ||
| autosearch | ||
| roms | ||
| scripts | ||
| src | ||
| test_4004 | ||
| test_4040 | ||
| test_8080 | ||
| test_8086 | ||
| test_buses | ||
| test_z80 | ||
| .gitignore | ||
| 00_README.md | ||
| package-lock.json | ||
| package.json | ||
| vitest.config.js | ||