215 lines
7.5 KiB
JavaScript
215 lines
7.5 KiB
JavaScript
/**
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* Zilog Z80 emulator chip — TDD spec.
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*
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* The Z80 is binary-compatible with the 8080 plus extensions, so the
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* 8080 tests' structure carries over. This file focuses on:
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* 1. The Z80-specific bus protocol (M1̅ / MREQ̅ / IORQ̅ / RFSH̅)
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* 2. Z80-only instructions (EX, EXX, DJNZ, IX/IY, block ops, IM 0-2)
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* 3. NMI behaviour (pushes PC, vectors to 0x0066)
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*
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* The 8080-subset instructions are NOT re-tested here — once both chips
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* are implemented, a shared "8080-subset suite" should run against both.
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*/
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import { describe, it, expect, beforeEach, afterEach } from 'vitest';
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import { BoardHarness } from '../src/BoardHarness.js';
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import { chipWasmExists, hex8, hex16 } from '../src/helpers.js';
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const CHIP = 'z80';
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const skip = !chipWasmExists(CHIP);
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const CLOCK_HZ = 4_000_000;
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const CLOCK_NS = Math.round(1e9 / CLOCK_HZ);
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function fullPinMap() {
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const m = {
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M1: 'M1', MREQ: 'MREQ', IORQ: 'IORQ', RD: 'RD', WR: 'WR', RFSH: 'RFSH',
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HALT: 'HALT', WAIT: 'WAIT', INT: 'INT', NMI: 'NMI', RESET: 'RESET',
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BUSREQ: 'BUSREQ', BUSACK: 'BUSACK', CLK: 'CLK',
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VCC: 'VCC', GND: 'GND',
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};
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for (let i = 0; i < 16; i++) m[`A${i}`] = `A${i}`;
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for (let i = 0; i < 8; i++) m[`D${i}`] = `D${i}`;
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return m;
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}
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async function bootZ80(program) {
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const board = new BoardHarness();
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await board.addChip(CHIP, fullPinMap());
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board.installFakeRom(program, {
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addrPrefix: 'A', addrWidth: 16,
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dataPrefix: 'D', dataWidth: 8,
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rd: 'RD', rdActiveLow: true,
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cs: 'MREQ', // only respond when MREQ̅ is asserted
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csActiveLow: true,
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baseAddr: 0,
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});
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const ram = board.installFakeRam(0x8000, {
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addrPrefix: 'A', addrWidth: 16,
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dataPrefix: 'D', dataWidth: 8,
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rd: 'RD', wr: 'WR',
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cs: 'MREQ',
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baseAddr: 0x8000,
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});
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board.setNet('WAIT', true); // not waiting
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board.setNet('INT', true); // INT̅ deasserted (active-low on Z80)
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board.setNet('NMI', true); // NMI̅ deasserted
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board.setNet('BUSREQ', true);
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board.setNet('RESET', false);
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board.advanceNanos(CLOCK_NS * 4);
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board.setNet('RESET', true);
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board.advanceNanos(CLOCK_NS * 2);
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return { board, ram };
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}
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describe('Zilog Z80 chip', () => {
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describe('pin contract', () => {
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it.skipIf(skip)('registers all 40 named pins', async () => {
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const board = new BoardHarness();
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await expect(board.addChip(CHIP, fullPinMap())).resolves.toBeDefined();
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board.dispose();
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});
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});
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describe('reset', () => {
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it.skipIf(skip)('first M1 fetch is from 0x0000', async () => {
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const board = new BoardHarness();
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await board.addChip(CHIP, fullPinMap());
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const m1Fetches = [];
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board.watchNet('M1', (low) => {
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if (low === false) m1Fetches.push(board.readBus('A', 16));
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});
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board.installFakeRom([0x00, 0x00, 0x76], { // NOP NOP HALT
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rd: 'RD', cs: 'MREQ', csActiveLow: true,
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});
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board.setNet('WAIT', true);
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board.setNet('INT', true);
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board.setNet('NMI', true);
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board.setNet('BUSREQ', true);
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board.setNet('RESET', false);
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board.advanceNanos(CLOCK_NS * 4);
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board.setNet('RESET', true);
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board.advanceNanos(CLOCK_NS * 30);
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expect(m1Fetches[0], 'first M1 fetch').toBe(0x0000);
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board.dispose();
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});
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});
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describe('M1 cycle', () => {
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it.skipIf(skip)('asserts M1̅ + MREQ̅ + RD̅ during opcode fetch', async () => {
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const board = new BoardHarness();
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await board.addChip(CHIP, fullPinMap());
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let sawAllAsserted = false;
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board.watchNet('M1', (state) => {
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if (state === false) {
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// Snap the other signals at the same instant
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if (board.getNet('MREQ') === false && board.getNet('RD') === false) {
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sawAllAsserted = true;
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}
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}
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});
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board.installFakeRom([0x00, 0x76], { rd: 'RD', cs: 'MREQ', csActiveLow: true });
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board.setNet('WAIT', true);
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board.setNet('INT', true); board.setNet('NMI', true); board.setNet('BUSREQ', true);
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board.setNet('RESET', false);
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board.advanceNanos(CLOCK_NS * 4);
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board.setNet('RESET', true);
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board.advanceNanos(CLOCK_NS * 30);
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expect(sawAllAsserted, 'M1̅, MREQ̅, RD̅ asserted simultaneously during fetch').toBe(true);
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board.dispose();
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});
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it.skipIf(skip)('asserts RFSH̅ during the refresh phase of M1', async () => {
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const board = new BoardHarness();
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await board.addChip(CHIP, fullPinMap());
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let rfshSeen = false;
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board.watchNet('RFSH', (state) => { if (state === false) rfshSeen = true; });
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board.installFakeRom([0x00, 0x00, 0x76], { rd: 'RD', cs: 'MREQ', csActiveLow: true });
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board.setNet('WAIT', true); board.setNet('INT', true);
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board.setNet('NMI', true); board.setNet('BUSREQ', true);
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board.setNet('RESET', false);
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board.advanceNanos(CLOCK_NS * 4);
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board.setNet('RESET', true);
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board.advanceNanos(CLOCK_NS * 30);
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expect(rfshSeen, 'RFSH̅ must pulse low after M1 fetch').toBe(true);
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board.dispose();
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});
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});
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describe('Z80-only instructions', () => {
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// Z80 mnemonic constants — only those used in tests below.
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const LD_A_n = 0x3E;
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const LD_BC_nn = 0x01;
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const LD_DE_nn = 0x11;
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const LD_HL_nn = 0x21;
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const LD_IX_nn = 0xDD; const _IX_LD_nn = 0x21; // DD 21 nn nn
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const EX_DE_HL = 0xEB;
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const EXX = 0xD9;
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const DJNZ = 0x10;
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const LDIR = 0xED; const _LDIR = 0xB0; // ED B0
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const LD_aHL_n = 0x36;
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const LD_addr_A = 0x32;
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const HALT = 0x76;
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it.skipIf(skip)('EX DE, HL swaps register pairs', async () => {
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// LD HL, 0x1234 ; LD DE, 0x5678 ; EX DE, HL ; LD (0x8000), A is awkward
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// because we can't read HL/DE directly. Use this instead:
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// LD HL, 0xAA00 ; LD DE, 0xBB00 ; EX DE, HL ; LD (HL), 0x77 ; HALT
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// After EX, HL = 0xBB00 (in our RAM range) so we write to 0xBB00.
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// Wait, 0xBB00 is in our RAM (0x8000+) — yes.
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const program = new Uint8Array([
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LD_HL_nn, 0x00, 0xAA,
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LD_DE_nn, 0x00, 0xBB,
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EX_DE_HL,
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LD_aHL_n, 0x77,
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HALT,
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]);
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const { board, ram } = await bootZ80(program);
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for (let i = 0; i < 200; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0xBB00)).toBe(0x77);
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board.dispose();
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});
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it.skipIf(skip)('DJNZ decrements B and jumps while non-zero', async () => {
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// LD A, 0 ; LD B, 5 ; LOOP: INC A ; DJNZ LOOP ; LD (0x8000), A ; HALT
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// Expected: A = 5 stored at 0x8000.
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const INC_A = 0x3C;
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const program = new Uint8Array([
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LD_A_n, 0x00,
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0x06, 0x05, // LD B, 5
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INC_A, // LOOP:
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DJNZ, 0xFD, // jump back -3 to LOOP
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LD_addr_A, 0x00, 0x80, // LD (0x8000), A
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HALT,
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]);
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const { board, ram } = await bootZ80(program);
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for (let i = 0; i < 500; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x8000)).toBe(5);
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board.dispose();
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});
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it.todo('LDIR copies a memory block from HL to DE');
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it.todo('LD A, (IX+d) reads via IX with signed displacement');
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it.todo('EXX swaps the main register set with the shadow set');
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});
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describe('interrupts', () => {
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it.todo('NMI̅ falling edge pushes PC and vectors to 0x0066');
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it.todo('IM 1 + INT̅ vectors to 0x0038');
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it.todo('IM 2 + INT̅ uses I:byte to vector through a table');
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});
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describe('integration', () => {
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it.todo('runs the public-domain ZEXDOC test ROM (documented flags)');
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});
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});
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