velxio/scripts
David Montero Crespo ca427db8ac fix(ci): the metadata gate failed over a missing newline, on every commit
`Fail if components-metadata.json is out of date` has been red on every push
for days. The diff it printed was one line — the last one:

    -}
    +}
    \ No newline at end of file

The committed JSON ends with a newline; the generator wrote
JSON.stringify(...) with none, so `git diff` was never empty and no content
change could ever clear it. The generator now writes the trailing newline,
which makes a fresh run byte-identical to what is committed.

Verified by running the real generator (needs the wokwi-elements clone, and
NODE_PATH pointing at frontend/node_modules): 156 components, `git diff`
empty.
2026-08-25 02:36:06 +02:00
..
asm8080.py feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
component-overrides.json fix(ssd1306): picker thumbnail matches the redrawn part 2026-08-20 16:04:54 +02:00
counter-rom.s feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
counter-rom.txt feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
generate-component-metadata.ts fix(ci): the metadata gate failed over a missing newline, on every commit 2026-08-25 02:36:06 +02:00
generate-component-svgs.cjs fix(scripts): generate-component-svgs no longer skips bmp280 / fails on ssd1306 2026-05-09 00:05:28 -03:00
generate-example-screenshots.md
…
generate-favicons.mjs
…
generate-og-image.mjs
…
generate-sitemap.ts
…
killbits-rom.s feat(chips): programmable retro CPU chips with external ROM 2026-05-18 23:38:18 -03:00
larson-z80.s feat(chips): programmable Z80 chip + Larson scanner example 2026-05-19 00:21:08 -03:00
make-z80-cpu.py fix(z80-cpu): map RAM over the whole 0x8000-0xFFFF so vanilla SDCC C runs 2026-06-03 13:31:26 +02:00
repl-rom.s feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
repl-rom.txt feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
test-z80.s feat(chips): programmable Z80 chip + Larson scanner example 2026-05-19 00:21:08 -03:00
visual-led-test.mjs test(visual-led): add RGB + 7-segment leafCheck assertions 2026-05-18 22:39:01 -03:00