velxio/frontend/src/simulation
David Montero Crespo 9ba8687743 fix(epaper): correct orientation across all boards + Pico VCC wire
ePaper panels rendered rotated/misaligned on AVR and RP2040 (e.g. the 2.13"
Pico clock came out sideways and clipped). The ESP32 worker decoder was just
taught to compose in the controller's native RAM geometry and rotate to the
display orientation, but the browser-side SSD168xDecoder (used by AVR/RP2040)
still composed at display dims with no rotation, so the two diverged.

- SSD168xDecoder.ts: port the worker's native-window compose + rotation.
  * Size RAM to the longer side both ways so a rotated native layout
    (128x296 behind a 296x128 panel) isn't truncated.
  * Compose in the active RAM window, then rotate via the inverse of
    Adafruit_GFX setRotation(1). Detect orientation by BYTE width so a
    non-multiple-of-8 native width (the 2.13" panel is 122 px) is handled.
  * Track the UNION of windows per frame: paged drivers (GxEPD2 page height
    < panel) set one partial window per page, so compose must use the full
    native area, not just the last page's strip. Fixes the all-white render
    on paged panels (1.54" Uno, 4.2" Pico, 7.5" ESP32).
  * Add an isBwr option: B/W panels treat 0x26 as a 2nd mono plane (white
    only if both planes white), tri-colour panels keep red-wins.
  * Default the active window to display geometry; the firmware overrides it.
- EPaperPart.ts: pass isBwr = cfg.palette === 'bwr' to the decoder.
- esp32_spi_slaves.py / esp32_worker.py: mirror the byte-aware rotation +
  window-union in the worker, and derive is_bwr from panel_kind on the
  runtime sensor_attach path too (fixes the tri-colour ESP32 alert badge).
- test_epaper/ssd168x_decoder.py: re-port the golden reference to match
  (keeps the 3-way TS/Python/worker identity invariant). Tests updated to
  construct tri-colour cases with is_bwr/palette='bwr'.
- examples-displays-epaper.ts: the Pico VCC wire referenced '3V3(OUT)',
  which the velxio-pi-pico-w element doesn't expose (it has '3V3'), so the
  wire snapped to the board corner. Use '3V3'.
2026-06-04 23:15:37 -03:00
..
customChips fix(z80-cpu): map RAM over the whole 0x8000-0xFFFF so vanilla SDCC C runs 2026-06-03 13:31:26 +02:00
cyw43 fix(sim): desktop QEMU sims use injected sidecar URL; fix nano-button-led wiring 2026-06-02 03:24:19 +02:00
displays fix(epaper): correct orientation across all boards + Pico VCC wire 2026-06-04 23:15:37 -03:00
parts fix(epaper): correct orientation across all boards + Pico VCC wire 2026-06-04 23:15:37 -03:00
spice feat(sim): custom chips read inputs (buttons/switches/sensors) with no board 2026-06-04 05:09:51 +02:00
verify
AVRSimulator.ts fix(multi-board): initSimulator wiped Interconnect's UART wrapper 2026-05-26 17:08:04 +02:00
Esp32Bridge.ts perf(esp32): drop per-edge gpio_change console.log that throttled the sim 2026-06-02 05:10:24 +02:00
Esp32C3Simulator.ts fix(spice+pipeline): LED visualization, INPUT_PULLUP, ESP32-C3, PWM fade, examples 2026-05-18 21:52:07 -03:00
Esp32MicroPythonLoader.ts
HD44780Decoder.ts
I2CBusManager.ts
Interconnect.ts feat: STM32 (Blue Pill / Black Pill) QEMU emulation + Pro board gating 2026-05-30 19:06:14 -03:00
LogicFamilies.ts
MicroPythonLoader.ts
PinManager.ts fix(stop): reset CPU to PC=0 on Stop (real-life power-cycle semantics) 2026-05-26 21:28:41 +02:00
PinResolver.ts
RP2040Simulator.ts feat(rp2040/uart): synthesize bit-level TX waveform on GP0 / GP4 2026-05-22 19:54:55 +02:00
RaspberryPi3Bridge.ts fix(sim): desktop QEMU sims use injected sidecar URL; fix nano-button-led wiring 2026-06-02 03:24:19 +02:00
RiscVCore.ts
RiscVSimulator.ts fix(spice+pipeline): LED visualization, INPUT_PULLUP, ESP32-C3, PWM fade, examples 2026-05-18 21:52:07 -03:00
SensorUpdateRegistry.ts
SignalRouter.ts
SpiBus.ts
Stm32Bridge.ts fix(sim): desktop QEMU sims use injected sidecar URL; fix nano-button-led wiring 2026-06-02 03:24:19 +02:00
esp32-signals.ts
piSlaveScanner.ts
rp2040-bootrom.ts
sensorControlConfig.ts