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velxio/backend/app
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David Montero 2fa5d801ec feat(esp32s3): use a 49-pin GPIO pinmap for the ESP32-S3 worker 
The S3 has GPIO0..48; the identity pinmap length drives how many pins
picsimlab_wire_gpio connects to the host. Default 40 left GPIO40..48 unwired,
so digitalWrite/Read on those pins never reached the frontend. Build a 49-entry
pinmap when the machine is esp32s3 (mirrors the c3->22 special case). Requires
the GPIO-model widening in libqemu (esp32_gpio bank-1 8->17).
 		2026-07-11 05:11:10 +02:00
..
api feat(opencore): extract Pico W WiFi to a pluggable PIO peripheral seam 2026-06-15 08:33:28 +02:00
core feat(opencore): extract Pico W WiFi to a pluggable PIO peripheral seam 2026-06-15 08:33:28 +02:00
database refactor(oss-split): remove auth/DB/admin stack from OSS 2026-05-14 13:36:31 -03:00
mcp
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models refactor(oss-split): remove auth/DB/admin stack from OSS 2026-05-14 13:36:31 -03:00
schemas refactor(oss-split): remove auth/DB/admin stack from OSS 2026-05-14 13:36:31 -03:00
services feat(esp32s3): use a 49-pin GPIO pinmap for the ESP32-S3 worker 2026-07-11 05:11:10 +02:00
utils refactor(oss-split): remove auth/DB/admin stack from OSS 2026-05-14 13:36:31 -03:00
__init__.py
…
main.py feat(flash): write compiled sketches to real USB boards (phases D1+D3) 2026-05-27 00:20:20 -03:00