555a4315be
First test wiring the 8086 CPU to a real 8259 PIC chip on the same board and proving hardware-interrupt routing works end-to-end: IRQ0 input → PIC asserts INT → CPU's INTR pin → CPU runs INTA cycle → PIC drives vector 0x40 on AD bus → CPU does do_int(0x40) → fetches CS:IP from IVT entry at 0x100 → ISR runs → IRET → main resumes from HLT. Two related chip fixes required to make this work: 1. 8086 INTA cycle no longer drives AD itself. Real 8086 INTA bus cycle has the PIC drive the data lines, not the CPU. My earlier code did `bus_read_byte(0, false)` which first drove AD with addr=0, overwriting whatever the PIC had driven. Fix: release_ad → INTA̅ low → sample AD (PIC's INTA watcher fires synchronously and drives) → INTA̅ high. 2. 8086 HLT now interruptible. on_clock previously early-returned on G.halted, so step() never ran and the INTR check never executed. Real 8086 HLT wakes on INTR/NMI. Fix: remove the early return; step()'s own halted check (later in the function) only no-ops if no pending interrupt. Tests: total test_intel 110 → 111 passing (+1, the integration test). 0 failed. 11 todo. test_8086 now 11→12 passing. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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| .. | ||
| autosearch | ||
| roms | ||
| scripts | ||
| src | ||
| test_4004 | ||
| test_4040 | ||
| test_8080 | ||
| test_8086 | ||
| test_buses | ||
| test_z80 | ||
| .gitignore | ||
| 00_README.md | ||
| package-lock.json | ||
| package.json | ||
| vitest.config.js | ||