Z80 chip enhancements:
- Add maskable INT̅ handling. Pin is level-triggered, active-low. The
on_int watcher tracks line state; step() services at instruction
boundaries when IFF1=1.
- IM 0/1 vector to 0x0038; IM 2 vectors via I:00 indirection (no
interrupt-controller hardware on the bus, so we approximate the
data byte as 0x00 — user code must pre-load the vector table).
- INTA cycle clears IFF1 and IFF2 per Zilog UM008003 p. 24.
- Power-on reset state: chip starts with reset_active=true so the
RESET̅ rising edge releases the chip (the watcher only fires on
edges; without an initial-true assumption, setting RESET=false
was a no-op and the chip executed instructions during the
test's pre-reset cycles).
Test infrastructure:
- bootZ80 no longer advances time after RESET deassert. Same lesson
as bootCpu in the 8080 tests — caller may need to poke RAM
contents BEFORE the chip executes.
5 it.todo tests promoted to passing:
- LDIR copies a memory block from HL to DE
- LD A, (IX+d) reads via IX with signed displacement
- EXX swaps the main register set with the shadow set
- NMI̅ falling edge pushes PC and vectors to 0x0066
- IM 1 + INT̅ vectors to 0x0038
Total test_intel: 60 passing (was 55), 0 failed, 17 todo.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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