479b52634e
Two long-deferred Phase C chips, both clean-room from public Intel datasheets. These complete the support-chip ecosystem needed for real interrupt-driven 8080/Z80/8086 software on the canvas. 8259 PIC (~280 LOC, single-master subset): - Full ICW1..ICW4 init sequence with branching on single/cascade and ICW4-needed flags. - IRR/ISR/IMR registers; OCW3 read-back; OCW1 mask write. - Priority-based INT (lower IRQ# = higher priority, fully-nested); pre-emption when a higher-priority IRQ arrives during a lower- priority ISR. - INTA falling-edge → drives vector_base + IRQ# on D bus. - Non-specific (0x20) and specific (0x60..67) EOI. - Cascade-master/slave routing NOT implemented (single master is sufficient for 95% of demos). - 7/7 tests passing. 8253 PIT (~210 LOC, Modes 0/2/3 subset): - Three independent 16-bit counters with own CLK/GATE/OUT pins. - Mode 0 (interrupt on terminal count) for one-shot timers. - Mode 2 (rate generator) for system tick. - Mode 3 (square wave, decrements by 2) for PC-speaker tone. - Modes 1/4/5 coerced to Mode 0 (rare in practice). - Full RW mode set: LSB-only / MSB-only / LSB-then-MSB / latch. - GATE-low pauses the countdown. - 4/4 tests passing. Tests: total test_intel 99→110 passing (+11). 0 failed. 11 todo. Master plan doc updated: Phase C extension done; Phase G still deferred. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> |
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| .. | ||
| autosearch | ||
| roms | ||
| scripts | ||
| src | ||
| test_4004 | ||
| test_4040 | ||
| test_8080 | ||
| test_8086 | ||
| test_buses | ||
| test_z80 | ||
| .gitignore | ||
| 00_README.md | ||
| package-lock.json | ||
| package.json | ||
| vitest.config.js | ||