velxio/frontend/src/simulation
davidmonterocrespo24 8bde313a91 test(sim): Phase 1d-tests J + C — vitest.config.ts + components-metadata integrity
J: vitest.config.ts split out from inline `test:` block in
vite.config.ts.  CI workflows can now reference vitest.config.ts
directly; test settings no longer pulled into vite build deps.
Settings: testTimeout 30s, hookTimeout 30s, forks pool with
singleFork:false (per-file worker isolation for the
NgSpiceNodeAdapter singleton), coverage excludes
`src/simulation/spice/wasm/**` (irrelevant lcov bytes).

C: components-metadata-integrity.test.ts — 11 sub-tests, all live
checks against the real `public/components-metadata.json` + every
examples-*.ts source-of-truth + the live PartSimulationRegistry:
  • Shape per entry: id / tagName / name / category / pinCount
  • IDs unique
  • tagName matches wokwi/velxio prefix
  • Thumbnail is an SVG
  • properties[] + defaultValues{} shape
  • Every metadataId referenced from gallery exists in metadata
    (instr-* filtered — instruments aren't canvas-rendered)
  • PartSimulationRegistry registrations cross-checked vs metadata
    (informational — some runtime-only parts have no metadata entry
    by design: custom-chip, raspberry-pi-3, 74hc595 internals)
  • Orphan-entries report: surfaces metadata entries no example or
    part-sim uses (informational, doesn't fail)

The orphan report flags 58 dead-ish metadata entries (preset
variants like resistor-220, individual epaper sizes, etc.) for
later cleanup conversation.  Not an error.

`PartSimulationRegistry.listRegisteredParts()` exposed for the test
to enumerate without duplicating the list.

1472 tests pass (was 1461 — +11 new metadata sub-tests).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-05-15 22:58:12 +02:00
..
customChips Add ESP32 chip demos and comprehensive tests for I2C, SPI, and UART interactions 2026-04-28 19:24:39 -03:00
cyw43 refactor: rename wokwi-libs/ → third-party/ 2026-05-03 00:58:57 -03:00
displays feat: add support for UC8159c (ACeP 7-colour) display 2026-04-30 00:27:40 -03:00
parts test(sim): Phase 1d-tests J + C — vitest.config.ts + components-metadata integrity 2026-05-15 22:58:12 +02:00
spice feat(sim): Phase 1d #10 + #11 + #16 — observable + perf + UX touch-ups 2026-05-15 22:34:29 +02:00
verify feat(sim): Phase 1c F2 — migrate 22 SPICE test files to NgSpiceNodeAdapter 2026-05-15 21:23:53 +02:00
AVRSimulator.ts feat(sim): Phase 1c G+F3 — retire legacy CircuitScheduler / eecircuit-engine 2026-05-15 21:46:34 +02:00
Esp32Bridge.ts feat(i2c): cross-board bridging across all velxio boards (AVR/RP2040/ESP32 xtensa+riscv) 2026-05-12 17:51:39 -03:00
Esp32C3Simulator.ts refactor: rename components and update prefixes to 'velxio-' for consistency 2026-04-21 16:45:45 -03:00
Esp32MicroPythonLoader.ts Add comprehensive tests for Cyw43Emulator functionality and lifecycle 2026-04-29 00:21:26 -03:00
HD44780Decoder.ts Add HD44780Decoder and various I2C sketches 2026-05-12 14:26:33 -03:00
I2CBusManager.ts feat(i2c): cross-board bridging across all velxio boards (AVR/RP2040/ESP32 xtensa+riscv) 2026-05-12 17:51:39 -03:00
Interconnect.ts feat(i2c): cross-board bridging across all velxio boards (AVR/RP2040/ESP32 xtensa+riscv) 2026-05-12 17:51:39 -03:00
LogicFamilies.ts feat(sim): Phase 3 — logic families (TTL/CMOS-5V/LVCMOS33/AVR_HC/Schmitt) 2026-05-15 16:42:11 +02:00
MicroPythonLoader.ts refactor: rename components and update prefixes to 'velxio-' for consistency 2026-04-21 16:45:45 -03:00
PinManager.ts feat(multi-board): add wire-aware cross-board interconnect router 2026-04-25 19:47:40 -03:00
PinResolver.ts feat(sim): Phase 3 — logic families (TTL/CMOS-5V/LVCMOS33/AVR_HC/Schmitt) 2026-05-15 16:42:11 +02:00
RP2040Simulator.ts fix(rp2040): route SPI0 through the adapter in initMCU too 2026-05-15 00:23:36 -03:00
RaspberryPi3Bridge.ts refactor: rename components and update prefixes to 'velxio-' for consistency 2026-04-21 16:45:45 -03:00
RiscVCore.ts refactor: rename components and update prefixes to 'velxio-' for consistency 2026-04-21 16:45:45 -03:00
RiscVSimulator.ts refactor: rename components and update prefixes to 'velxio-' for consistency 2026-04-21 16:45:45 -03:00
SensorUpdateRegistry.ts feat: add SensorControlPanel for interactive sensor controls 2026-03-19 01:52:46 -03:00
SpiBus.ts refactor(spi): unify SPI bus interface across all simulators 2026-05-02 22:36:29 -03:00
rp2040-bootrom.ts Refactor simulator store to unify serial data handling and add board pin mapping utility 2026-03-05 21:07:03 -03:00
sensorControlConfig.ts feat(photodiode): add lux control in sensor panel and property dialog 2026-04-24 16:42:36 +02:00