15541 lines
448 KiB
Plaintext
15541 lines
448 KiB
Plaintext
|
||
===PAGE 1===
|
||
|
||
|
||
===PAGE 2===
|
||
InDecember 1973Intelshippedthefirst8-bit,N-channel microprocessor,
|
||
the8080.Sincethenithasbecomethemostwidelyusedmicroprocessor in
|
||
theindustry. Applications ofthe8080spanfromlarge,intelligent systems
|
||
terminals todecompression computers fordeepseadivers.
|
||
This8080Microcomputer SystemsUser'sManualpresentsallofthe
|
||
8080systemcomponents. Overtwenty-five devicesaredescribed indetail.
|
||
Thesenewdevicesfurtherenhancethe8080system:
|
||
8080A-8-BitCentralProcessor Unit
|
||
Functionally andElectrically Compatible withthe8080.
|
||
TTLDriveCapability.
|
||
Enhanced Timing.
|
||
8224-ClockGenerator for8080A.
|
||
Single16Pin(DIP)Package.
|
||
Auxiliary TimingFunctions.
|
||
Power-On Reset.
|
||
8228-SystemController for8080A.
|
||
Single28Pin(DIP)Package.
|
||
SingleInterrupt Vector(RST7).
|
||
.Multi-Byte Interrupt Instruction Capability (e.g.CALL).
|
||
DirectDataandControlBusConnect toall8080System.I/O
|
||
andMemory Components.
|
||
8251-Programmable Communication Interface.
|
||
ASYNCorSYNC(including IBMbi·SYNC).
|
||
Single28PinPackage.
|
||
Single+5VoltPowerSupply.
|
||
8255-Programmable Peripheral Interface.
|
||
Three8-BitPorts.
|
||
BitSet/Reset Capability.
|
||
Interrupt Generation.
|
||
Single40PinPackage.
|
||
Single+5VoltPowerSupply.
|
||
Inaddition, newmemorycomponents include:8708,8KErasablePROM;
|
||
8316A,HighDensityMaskROM;and5101,LowPowerCMOSRAM.
|
||
intel® Microcomputers. Firstfromthebeginning.
|
||
|
||
===PAGE 3===
|
||
CONTENTS
|
||
INTRODUCTION
|
||
General .
|
||
Advantages ofDesigning withMicrocomputers . . ii
|
||
Microcomputer DesignAids iii
|
||
Application Example . . . . . . . . . . . . . . . . . . . iii
|
||
Application Table... . . . . . . . . . . . . . . . . . . iv
|
||
CHAPTER1-
|
||
THEFUNCTIONS OFACOMPUTER
|
||
ATypicalComputer System 1-1
|
||
TheArchitecture ofaCPU 1-1
|
||
Computer Operations. . . . . . . . . . . . . . . . . . . 1-3
|
||
CHAPTER2-
|
||
THE8080CENTRAL PROCESSING UNIT
|
||
General . . . . . . . . . . . . . . . . . . . . . . . . . . ..2-1
|
||
Architectu.re ofthe8080CPU. . . . . . . . . . . ..2-2
|
||
TheProcessor Cycle. . . . . . . . . . . . . . . . . . ..2-3
|
||
Interrupt Sequences. . . . . . . . . . . . . . . . . . ..2-11
|
||
HoldSequences. . . . . . . . . . . . . . . . . . . . . ..2-12
|
||
HaltSequences . . . . . . . . . . . . . . . . . . . . . ..2-13
|
||
Start-upofthe8080CPU. . . . . . . . . . . . . . ..2-13
|
||
CHAPTER3
|
||
INTERFACING THE8080
|
||
General . . . . . . . . . . . . . . . . . . . . . . . . . . ..3-1
|
||
BasicSystemOperation 3-1
|
||
CPUModuleDesign. . . . . . . . . . . . . . . . . . ..3-2
|
||
Interfacing the8080toMemory and
|
||
I/ODevices 3-6CHAPTER4
|
||
INSTRUCTION SET
|
||
General . . . . . . . . . . . . . . . . . . . . . . . . . . ..4-1
|
||
DataTransfer Group 4-4
|
||
Arithmetic Group. . . . . . . . . . . . . . . . . . . ..4-6
|
||
BranchGroup. . . . . . . . . . . . . . . . . . . . . . ..4-11
|
||
Stack,I/OandMachine ControlGroup... . ...4-13
|
||
Summary Table.. . . . . . . . . . . . . . . . . . . . ..4-15
|
||
CHAPTER5-
|
||
8080MICROCOMPUTER SYSTEM COMPONENTS
|
||
CPUGroup
|
||
8224ClockGenerator
|
||
Functional Description and
|
||
SystemApplications 5-1
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . ..5-4
|
||
8228SystemController
|
||
Functional Description and
|
||
SystemApplications. . . . . . . . . . . . . . . . ..5-7
|
||
DataSheet.. . . . . . . . . . . . . . . . . . . . . ..5-11
|
||
S080ACentralProcessor
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . ..5-13
|
||
8080A-1 CentralProcessor (1.3,us)
|
||
DataSheet.. . . . . . . . . . . . . . . . . . . . . ..5-20
|
||
8080A-2 CentralProcessor (1.5,us)
|
||
DataSheet.. . . . . . . . . . . . . . . . . . . . . ..5-24
|
||
M80SOA CentralProcessor (-55°to+125°C)
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . ..5-29
|
||
IntelCorporation assumesnoresponsibility fortheuseofanycircuitry otherthancircuitry embodied inanIntelproduct. Noothercircuitpatentlicensesareimplied.
|
||
|
||
===PAGE 4===
|
||
ROMs
|
||
8702AErasablePROM(256x8)
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . ..5-37
|
||
8708/8704 ErasablePROM(1Kx8)
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . ..5-45
|
||
8302MaskROM(256x8)
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . ..5-51
|
||
8308MaskROM(1Kx8)
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . ..5-59
|
||
8316AMaskROM(2Kx8)
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . ..5-61
|
||
RAMs
|
||
8101-2StaticRAM(256x4)
|
||
DataSheet.. . . . . . . . . . . . . . . . . . . . . ..5-67
|
||
8111-2StaticRAM(256x4)
|
||
DataSheet. . . . . . . . . . . . . . . ... . . . ...5-71
|
||
8102-2StaticRAM(1Kx1)
|
||
DataSheet 05-75
|
||
8102A-4 StaticRAM(1Kx1)
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . ..5-79
|
||
81078-4Dynamic RAM(4Kx1)
|
||
DataSheet.. . . . . . . . . . . . . . . . . . . . . ..5-83
|
||
5101StaticCMOSRAM(256x4)
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . ..5-91
|
||
8210Dynamic RAMDriver
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . ..5-95
|
||
8222Dynamic RAMRefreshController
|
||
NewProductAnnouncement . . . . . . . . . . ..5-99
|
||
I/O
|
||
82128-BitI/OPort
|
||
Functional Description 5-101
|
||
SystemApplications ofthe8212 5-103
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . . . 5-1098255Programmable Peripheral Interface
|
||
BasicFunctional Description . . . . . . . . . . . . 5-113
|
||
DetailedOperationa-I Description ~. . .5-116
|
||
SystemApplicationsofthe8255 . . . .5-127
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . . . 5-130
|
||
8251Programmable Communication Interface
|
||
BasicFunctional Description . . . . . . . . . . . . 5-135
|
||
DetailedOperational Description 5-139
|
||
SystemApplications ofthe8251 5-143
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . . . 5-144
|
||
Peripherals
|
||
8205Oneof8Decoder
|
||
Functional Description 5-147
|
||
SystemApplications ofthe8205 5-149
|
||
DataSheet 5-151
|
||
8214PriorityInterrupt ControlUnit
|
||
Interrupts jnMicrocomputer Systems 5-153
|
||
Functional Description . . . . . . . . . . . . . . . . 5-155
|
||
SystemApplicationsofthe8214... . . . . . . 5-157
|
||
DataSheet 5-160
|
||
8216/8226 4-BitBi-Directional BusDriver
|
||
Functional Description 5-163
|
||
SystemApplications ofthe8216/8226 5-165
|
||
DataSheet. . . . . . . . . . . . . . . . . . . . . . . . 5-166
|
||
ComingSoon
|
||
8253Programmable IntervalTimer. . . . . . . . . . 5-169
|
||
8257Programmable DMAController 5-171
|
||
8259Programmable Interrupt Controller 5-173
|
||
CHAPTER6-
|
||
PACKAGING INFORMATION ....•.......... 6-1
|
||
|
||
===PAGE 5===
|
||
Sincetheirinception, digitalcomputers havecontin
|
||
uouslybecome moreefficient, expanding intonewappli
|
||
cationswitheachmajortechnological improvement. The
|
||
adventofminicomputers enabled theinclusion ofdigital
|
||
computers asapermanent partofvariousprocesscontrol
|
||
systems. Unfortunately, thesizeandcostofminicomputers
|
||
in"dedicated" applications haslimitedtheiruse.Another
|
||
approach hasbeentheuseofcustombuiltsystems madeup
|
||
of"random logic"(i.e.,logicgates,flip-flops, counters, etc.).
|
||
However, thehugeexpense anddevelopment timeinvolved
|
||
inthedesignanddebugging ofthesesystems hasrestricted
|
||
theirusetolargevolumeapplications wherethedevelop
|
||
mentcostscouldbespreadoveralargenumberofmachines.
|
||
Today,Inteloffersthesystems designer anewalter
|
||
native...themicrocomputer. Utilizing thetechnologies and
|
||
experience gainedinbecoming theworld'slargestsupplier
|
||
ofLSImemory components, Intelhasmadethepowerof
|
||
thedigitalcomputer available attheintegrated circuitlevel.
|
||
Usingthen-channel silicongateMOSprocess, Intelengi
|
||
neershaveimplemented thefast(2/ls.cycle)andpowerful
|
||
(72basicinstructions) 8080microprocessor onasingleLSI
|
||
chip.Whenthisprocessor iscombined withmemory and
|
||
I/Ocircuits,thecomputer iscomplete. Inteloffersavariety
|
||
ofrandom-access memory (RAM),read-only memory (ROM)
|
||
andshiftregister circu~ts, thatcombine withthe8080pro
|
||
cessortoformtheMCS-80 microcomputer system,asystem
|
||
thatcandirectly addressandretrieve asmanyas65,536
|
||
bytesstoredinthememory devices.
|
||
The8080processor ispackaged ina40-pindualin-line
|
||
package (DIP)thatallowsforremarkably easyinterfacing.
|
||
The8080hasa16-bitaddressbus,a8-bitbidirectional data
|
||
busandfullydecoded, TTL-compatible controloutputs. In
|
||
addition tosupporting upto64KbytesofmixedRAMand
|
||
ROMmemory, the8080canaddressupto256inputports
|
||
and256outputports;thusallowing forvirtually unlimited
|
||
systemexpansion. The8080instruction setincludes con
|
||
ditional branching, decimal aswellasbinaryarithmetic,logical,register-to-register, stackcontrolandmemory refer
|
||
enceinstructions. Infact,the8080instruction setispower
|
||
fulenoughtorivaltheperformance ofmanyofthemuch
|
||
higherpricedminicomputers, yetthe8080isupwardsoft
|
||
warecompatible withIntel'searlier8008microprocessor
|
||
(Le.,programs writtenforthe8008canbeassembled and
|
||
executed onthe8080).
|
||
Inaddition toanextensive instruction setoriented to
|
||
problem solving,the8080hasanother significant feature
|
||
SPEED. Incontrast torandom logicdesignswhichtendto
|
||
workinparallel, themicrocomputer worksbysequentially
|
||
executing itsprogram. Asaresultofthissequential execu
|
||
tion,thenumber oftasksamicrocomputer canundertake
|
||
inagivenperiodoftimeisdirectly proportional tothe
|
||
execution speedofthemicrocomputer. Thespeedofexe
|
||
cutionisthelimitingfactoroftherealmofapplications of
|
||
themicrocomputer. The8080,withinstruction timesas
|
||
shortas2/lsec.,isanorderofmagnitude fasterthanearlier
|
||
generations ofmicrocomputers, andtherefore hasanex
|
||
pandedfieldofpotential applications.
|
||
Thearchitecture ofthe8080alsoshowsasignificant
|
||
improvement overearliermicrocomputer designs.The8080
|
||
contains a16-bitstackpointerthatcontrols theaddressing
|
||
ofanexternal stacklocatedinmemory. Thepointercanbe
|
||
initialized viatheproperinstructions suchthatanyportion
|
||
ofexternal memory canbeusedasalastin/firstoutstack;
|
||
thusenabling almostunlimited subroutine nesting.Thestack
|
||
pointerallowsthecontents oftheprogram counter, theac
|
||
cumulator, thecondition flagsoranyofthedataregisters to
|
||
bestoredinorretrieved fromtheexternal stack.Inaddi
|
||
tion,multi-level interrupt processing ispossible usingthe
|
||
8080'sstackcontrol instructions. Thestatusofthepro
|
||
cessorcanbe"pushed" ontothestackwhenaninterrupt is
|
||
accepted, then"popped" offthestackaftertheinterrupt has
|
||
beenserviced. Thisabilitytosavethecontents ofthepro
|
||
cessor's registers ispossible evenifaninterrupt service
|
||
routine, itself,isinterrupted.
|
||
|
||
===PAGE 6===
|
||
Product definition
|
||
Systemandlogicdesign
|
||
Debug
|
||
PCcardlayout
|
||
Documentation
|
||
Coolingandpackaging
|
||
Powerdistribution
|
||
Engineering changesCONVENTIONAL SYSTEM
|
||
Donewithlogicdiagrams
|
||
Donewithconventional
|
||
LabInstrumentation
|
||
DonewithyellowwirePROGRAMMED LOGIC
|
||
Simplifiedbecauseofeaseofincorporating features
|
||
Canbeprogrammed withdesignaids
|
||
(compilers, assemblers, editors)
|
||
Software andhardware aidsreducetime
|
||
Fewercardstolayout
|
||
Lesshardware todocument
|
||
Reduced systemsizeandpowerconsumption
|
||
easesjob
|
||
Lesspowertodistribute
|
||
Changeprogram
|
||
Table0-1.TheAdvantages ofUsingMicroprocessors
|
||
ADVANTAGES OFDESIGNING
|
||
WITHMICROCOMPUTERS
|
||
Microcomputers simplify almosteveryphaseofpro
|
||
ductdevelopment. Thefirststep,asinanyproduct devel
|
||
opment program, istoidentify thevariousfunctions that
|
||
theendsystemisexpected toperform. Insteadofrealizing
|
||
thesefunctions withnetworks ofgatesandflip-flops, the
|
||
functions areimplemented byencoding suitable sequences
|
||
ofinstructions (programs) inthememory elements. Data
|
||
andcertaintypesofprograms arestoredinRAM,whilethe
|
||
basicprogram canbestoredinROM.Themicroprocessor
|
||
performs allofthesystem's functions byfetching thein
|
||
structions inmemory, executing themandcommunicating
|
||
theresultsviathemicrocomputer's I/Oports.An8080
|
||
microprocessor, executing theprogrammed logicstoredina
|
||
single2048-byte ROMelement, canperform thesamelogical
|
||
functions thatmighthavepreviously required upto1000
|
||
logicgates.
|
||
Thebenefits ofdesigning amicrocomputer intoyour
|
||
systemgofarbeyondtheadvantages ofmerelysimplifying
|
||
product development. Youwillalsoappreciate theprofit
|
||
making advantages ofusingamicrocomputer inplaceof
|
||
custom-designed random logic.Themostapparent advantage
|
||
isthesignificant savingsinhardware costs.Amicrocomputer
|
||
chipsetreplaces dozensofrandom logicelements, thusre
|
||
ducingthecostaswellasthesizeofyoursystem. Inaddi
|
||
tion,production costsdropasthenumber ofindividual
|
||
components tobehandled decreases, andthenumber of
|
||
complex printedcircuitboards(whicharedifficult tolay
|
||
out,testandcorrect) isgreatlyreduced. Probably themost
|
||
profitable advantage ofamicrocomputer isitsflexibility
|
||
forchange.Tomodifyyoursystem,youmerelyre-program
|
||
thememory elements; youdon'thavetoredesign theentire
|
||
system. Youcanimagine thesavingsintimeandmoney
|
||
whenyouwanttoupgrade yourproduct. Reliability is
|
||
another reasontochoosethemicrocomputer overrandom
|
||
logic.Asthenumber ofcomponents decreases, theprob
|
||
abilityofamalfunctioning element likewise decreases. All
|
||
iiofthelogicalcontrol functions formerly performed by
|
||
numerous hardware components cannowbeimplemented
|
||
inafewROMcircuits whicharenon-volatile; thatis,the
|
||
contents ofROMwillneverbelost,evenintheeventofa
|
||
powerfailure. Table0-1summarizes manyoftheadvan
|
||
tagesofusingmicrocomputers.
|
||
MICROCOMPUTER DESIGN AIDS
|
||
Ifyou'reusedtologicdesignandtheideaofdesigning
|
||
withprogrammed logicseemsliketooradicalachange, re
|
||
gardless ofadvantages, there'snoneedtoworrybecause
|
||
Intelhasalreadydonemostofthegroundwork foryou.The
|
||
INTELLEC® 8Development Systems provideflexible, in
|
||
expensive andsimplified methods forOEMproduct develop
|
||
ment.TheINT~LLEC@ 8provides RAMprogram storage
|
||
making program loadingandmodification easier,adisplay
|
||
andcontrolconsole forsystemmonitoring anddebugging,
|
||
astandard TTYinterface, aPROMprogramming capability
|
||
andastandard software package (System Monitor, Assem
|
||
blerandTestEditor). Inaddition tothestandard software
|
||
package available withtheINTELLEC® 8,Inteloffersa
|
||
PL/MTcompiler, across-assembler andasimulator writtenin
|
||
FORTRAN IVanddesigned torunonanylargescalecom
|
||
puter.Theseprograms maybeprocured directly fromIntel
|
||
orfromanumber ofnationwide computer time-sharing
|
||
services. Intel'sMicrocomputer Systems Groupisalways
|
||
available toprovideassistance ineveryphaseofyourproduct
|
||
development.
|
||
Intelalsoprovides complete documentation onall
|
||
theirhardware andsoftware products. Inaddition tothis
|
||
User'sManual, therearethe:
|
||
•PL/M'~Language Reference Manual
|
||
•8080Assembly Language Programming Manual
|
||
•INTELLEC®8/MOD 80Operator's Manual
|
||
•INTELLEC®8/MOD 80Hardware Reference
|
||
Manual
|
||
•8080User'sProgram Library
|
||
|
||
===PAGE 7===
|
||
APPLICATIONS EXAMPLE
|
||
The8080canbeusedasthebasisforawidevariety
|
||
ofcalculation andcontrol systems. Thesystemconfigura
|
||
tionsforparticular applications willdifferinthenatureof
|
||
theperipheral devicesusedandintheamount andthetype
|
||
ofmemory required. Theapplications andsolutions de
|
||
scribedinthissectionarepresented primarily toshowhow
|
||
microcomputers canbeusedtosolvedesignproblems. The
|
||
8080shouldnotbeconsidered limitedeitherinscopeor
|
||
performance tothoseapplications listedhere.
|
||
Consider an8080microcomputer usedwithinanauto
|
||
maticcomputing scaleforasupermarket. Thebasicmachine
|
||
hastwoinputdevices: theweighing unitandakeyboard,
|
||
usedforfunction selection andtoenterthepriceperunit
|
||
ofweight.Theonlyoutputdeviceisadisplayshowing the
|
||
totalprice,although aticketprintermightbeaddedasan
|
||
optional outputdevice.
|
||
Thecontrolunitmustacceptweightinformation from
|
||
theweighing unit,function anddatainputsfromthekey
|
||
board,andgenerate thedisplay. Theonlyarithmetic func
|
||
tiontobeperformed isasimplemultiplication ofweight
|
||
timesrate.
|
||
Thecontrol unitcouldprobably berealized with
|
||
standard TTLlogic.Statediagrams forthevariousportions
|
||
couldbedrawnandamultiplier unitdesigned. Thewhole
|
||
designcouldthenbetiedtogether, andeventually reduced
|
||
toaselection ofpackages andaprintedcircuitboardlayout.
|
||
Ineffect,whendesigning withalogicfamilysuchasTTL,
|
||
thedesignsare"customized" bythechoiceofpackages and
|
||
thewiringofthelogic.
|
||
If,however, an8080microcomputer isusedtorealizethecontrolunit(asshowninFigure0-1),theonly"custom"
|
||
logicwillbethatoftheinterface circuits. Thesecircuitsare
|
||
usuallyquitesimple,providing electrical buffering forthe
|
||
inputandoutputsignals.
|
||
Insteadofdrawing statediagrams leadingtologic,the
|
||
systemdesigner nowprepares aflowchart,indicating which
|
||
inputsignalsmustberead,whatprocessing andcomputa
|
||
tionsareneeded,andwhatoutputsignaIsmustbeproduced.
|
||
Aprogram iswrittenfromtheflowchart.Theprogram is
|
||
thenassembled intobitpatterns whichareloadedintothe
|
||
program memory. Thus,thissystemiscustomized primarily
|
||
bythecontents ofprogram memory.
|
||
Forthisautomatic scale,theprogram wouldprobably
|
||
resideinread-only memory (ROM), sincethemicrocom
|
||
puterwouldalwaysexecute thesameprogram, theone
|
||
whichimplements thescalefunctions. Theprocessor would
|
||
constantly monitorthekeyboard andweighing unit,andup
|
||
datethedisplaywhenever necessary. Theunitwouldrequire
|
||
verylittledatamemory; itwouldonlybeneededforrate
|
||
storage, intermediate results,andforstoringacopyofthe
|
||
display.
|
||
Whenthecontrolportionofaproduct isimplemented
|
||
withamicrocomputer chipset,functions canbechanged
|
||
andfeatures addedmerelybyalteringtheprogram inmem
|
||
ory.WithaTTLbasedsystem,however, alterations mayre
|
||
quireextensive rewiring, alteration ofPCboards,etc.
|
||
Thenumber ofapplications formicrocomputers is
|
||
limitedonlybythedepthofthedesigner's imagination. We
|
||
havelistedafewpotential applications inTable0-2,along
|
||
withthetypesofperipheral devicesusuallyassociated with
|
||
eachproduct.
|
||
,
|
||
I
|
||
I
|
||
I
|
||
-J/ /KEYBOARDPRINTER-00000
|
||
00 DISPLAY000CIJ00 ---..WEIGHING 000
|
||
1':II':II':~I':ff':'1UNIT 0000000IIIIIIIIII
|
||
11 T+
|
||
I
|
||
Ir------
|
||
INPUT INPUT OUTPUTIOPTIONAL
|
||
IOUTPUTINTERFACE #1 INTERFACE #2 INTERFACE #1INTERFACE #2I'---TT--
|
||
I+I 1+ ItIItI 8080I ICPU IL..--
|
||
BUS
|
||
CONTROLIt[ ItIUNIT
|
||
PROGRAM DATA
|
||
MEMORY MEMORY
|
||
(PROM) (RAM)
|
||
Figure0-1.Microcomputer Application -Automatic Scale
|
||
iii
|
||
|
||
===PAGE 8===
|
||
APPLICATION PERIPHERAL DEVICES ENCOUNTERED
|
||
Intelligent Terminals Cathode RayTubeDisplay
|
||
PrintingUnits
|
||
Synchronous andAsynchronous datalines
|
||
CassetteTapeUnit
|
||
Keyboards
|
||
GamingMachines Keyboards, pushbuttonsandswitches
|
||
Variousdisplaydevices
|
||
Coinacceptors
|
||
Coindispensers
|
||
CashRegisters Keyboard orInputSwitchArray
|
||
ChangeDispenser
|
||
DigitalDisplay
|
||
TicketPrinter
|
||
Magnetic Cardreader
|
||
Communication interface
|
||
Accounting andBillingMachines Keyboard
|
||
PrinterUnit
|
||
Cassetteorothermagnetic tapeunit
|
||
"Floppy" disks
|
||
Telephone Switching Control Telephone LineScanner
|
||
AnalogSwitching Network
|
||
DialRegisters
|
||
ClassofServiceParcel
|
||
Numerically Controlled Machines Magnetic orPaperTapeReader
|
||
StepperMotors
|
||
OpticalShaftEncoders
|
||
ProcessControl Analog-to-DigitaIConverters
|
||
Digital-to-Analog Converters
|
||
Control Switches
|
||
Displays
|
||
Table0-2.Microprocessor Applications
|
||
iv
|
||
|
||
===PAGE 9===
|
||
\Thischapterintroduces certainbasiccomputer con
|
||
cepts.Itprovides background information anddefinitions
|
||
whichwillbeusefulinlaterchapters ofthismanual.Those
|
||
alreadyfamiliar withcomputers mayskipthismaterial, at
|
||
theiroption.
|
||
ATYPICAL COMPUTER SYSTEM
|
||
Atypicaldigitalcomputer consistsof:
|
||
a)Acentralprocessor unit(CPU)
|
||
b)Amemory
|
||
c)Input/output (I/O)ports
|
||
Thememory servesasaplacetostoreInstructions,
|
||
thecodedpiecesofinformation thatdirecttheactivities of
|
||
theCPU,andData,thecodedpiecesofinformation thatare
|
||
processed bytheCPU.Agroupoflogically relatedinstruc
|
||
tionsstoredinmemory isreferredtoasaProgram. TheCPU
|
||
"reads"eachinstruction frommemory inalogically deter
|
||
minedsequence, andusesittoinitiateprocessing actions.
|
||
Iftheprogram sequence iscoherent andlogical,processing
|
||
theprogram willproduce intelligible andusefulresults.
|
||
Thememory isalsousedtostorethedatatobemanip
|
||
ulated,aswellastheinstructions thatdirectthatmanipu
|
||
lation.Theprogram mustbeorganized suchthattheCPU
|
||
doesnotreadanon-instruction wordwhenitexpectsto
|
||
seeaninstruction. TheCPUcanrapidlyaccessanydata
|
||
storedinmemory; butoftenthememory isnotlargeenough
|
||
tostoretheentiredatabankrequired foraparticular appli
|
||
cation.Theproblem canberesolved byproviding thecom
|
||
puterwithoneormoreInputPorts.TheCPUcanaddress
|
||
theseportsandinputthedatacontained there.Theaddition
|
||
ofinputportsenablesthecomputer toreceiveinformation
|
||
fromexternal equipment (suchasapapertapereaderor
|
||
floppydisk)athighratesofspeedandinlargevolumes.
|
||
Acomputer alsorequires oneormoreOutputPorts
|
||
thatpermittheCPUtocommunicate theresultofitspro
|
||
cessingtotheoutsideworld.Theoutputmaygotoadis
|
||
play,forusebyahumanoperator, toaperipheral device
|
||
thatproduces "hard-copy," suchasaline-printer,toa
|
||
1-1peripheral storagedevice,suchasafloppydiskunit,orthe
|
||
outputmayconstitute processcontrolsignalsthatdirectthe
|
||
operations ofanothersystem,suchasanautomated assembly
|
||
line.Likeinputports,outputportsareaddressable. The
|
||
inputandoutputportstogether permittheprocessor to
|
||
communicate withtheoutsideworld.
|
||
TheCPUunifiesthesystem.Itcontrols thefunctions
|
||
performed bytheothercomponents. TheCPUmustbeable
|
||
tofetchinstructions frommemory, decodetheirbinary
|
||
contents andexecutethem.Itmustalsobeabletoreference
|
||
memory andI/Oportsasnecessary intheexecution ofin
|
||
structions. Inaddition, theCPUshouldbeabletorecognize
|
||
andrespond tocertainexternal control signals,suchas
|
||
INTERRUPT andWAITrequests. Thefunctional units
|
||
withinaCPUthatenableittoperform thesefunctions are
|
||
described below.
|
||
THEARCHITECTURE OFACPU
|
||
Atypicalcentralprocessor unit(CPU)consistsofthe
|
||
following interconnected functional units:
|
||
•Registers
|
||
•Arithmetic/Logic Unit(ALU)
|
||
•ControlCircuitry
|
||
Registers aretemporary storageunitswithintheCPU.
|
||
Someregisters, suchastheprogram counterandinstruction
|
||
register, havededicated uses.Otherregisters, suchastheac
|
||
cumulator, areformoregeneralpurpose use.
|
||
Accumulator:
|
||
Theaccumulator usuallystoresoneoftheoperands
|
||
tobemanipulated bytheALU.Atypicalinstruction might
|
||
directtheALUtoaddthecontents ofsomeotherregisterto
|
||
thecontents oftheaccumulator andstoretheresultinthe
|
||
accumulator itself.Ingeneral, theaccumulator isbotha
|
||
source(operand) andadestination (result)register.
|
||
OftenaCPUwillincludeanumber ofadditional
|
||
generalpurpose registers thatcanbeusedtostoreoperands
|
||
orintermediate data.Theavailability ofgeneralpurpose
|
||
|
||
===PAGE 10===
|
||
registers eliminates theneedto"shuffle" intermediate re
|
||
sultsbackandforthbetween memory andtheaccumulator,
|
||
thusimproving processing speedandefficiency.
|
||
ProgramCounter(Jumps,Subroutines
|
||
andtheStack):
|
||
Theinstructions thatmakeupaprogram arestored
|
||
inthesystem's memory. Thecentralprocessor references
|
||
thecontents ofmemory, inordertodetermine whataction
|
||
isappropriate. Thismeansthattheprocessor mustknow
|
||
whichlocation contains thenextinstruction.
|
||
Eachofthelocations inmemory isnumbered, todis
|
||
tinguish itfromallotherlocations inmemory. Thenumber
|
||
whichidentifies amemory location iscalleditsAddress.
|
||
Theprocessor maintains acounterwhichcontains the
|
||
addressofthenextprogram instruction. Thisregister is
|
||
calledtheProgram Counter. Theprocessor updatesthepro
|
||
gramcounter byadding"1"tothecounter eachtimeit
|
||
fetchesaninstruction, sothattheprogram counter isalways
|
||
current(pointing tothenextinstruction).
|
||
Theprogrammer therefore storeshisinstructions in
|
||
numerically adjacent addresses, sothattheloweraddresses
|
||
containthefirstinstructions tobeexecuted andthehigher
|
||
addresses contain laterinstructions. Theonlytimethepro
|
||
grammer mayviolatethissequential ruleiswhenaninstruc
|
||
tioninonesectionofmemory isaJumpinstruction to
|
||
anothersectionofmemory.
|
||
Ajumpinstruction contains theaddressoftheinstruc
|
||
tionwhichistofollowit.Thenextinstruction maybe
|
||
storedinanymemory location, aslongastheprogrammed
|
||
jumpspecifies thecorrectaddress. Duringtheexecution of
|
||
ajumpinstruction, theprocessor replacesthecontents ofits
|
||
program counter withtheaddressembodied intheJump.
|
||
Thus,thelogicalcontinuity oftheprogram isma.intained.
|
||
Aspecialkindofprogram jumpoccurswhenthestored
|
||
program "Calls"asubroutine. Inthiskindofjump,thepro
|
||
cessorisrequired to"remember" thecontents ofthepro
|
||
gramcounteratthetimethatthejumpoccurs.Thisenables
|
||
theprocessor toresumeexecution ofthemainprogram
|
||
whenitisfinished withthelastinstruction ofthesubroutine.
|
||
ASubroutine isaprogram withinaprogram. Usually
|
||
itisageneral-purpose setofinstructions thatmustbeexe
|
||
cutedrepeatedly inthecourseofamainprogram. Routines
|
||
whichcalculate thesquare,thesine,orthelogarithm ofa
|
||
program variable aregoodexamples offunctions often
|
||
writtenassubroutines. Otherexamples mightbeprograms
|
||
designed forinputting oroutputting datatoaparticular
|
||
peripheral device.
|
||
Theprocessor hasaspecialwayofhandling sub
|
||
routines, inordertoinsureanorderlyreturntothemain
|
||
program. Whentheprocessor receives aCallinstruction, it
|
||
increments theProgram Counter andstoresthecounter's
|
||
contents inareserved memory areaknownastheStack.
|
||
TheStackthussavestheaddressoftheinstruction tobe
|
||
executed afterthesubroutine iscompleted. Thenthepro-
|
||
1-2cessorloadstheaddress specified intheCallintoitsPro
|
||
gramCounter. Thenextinstruction fetchedwilltherefore
|
||
bethefirststepofthesubroutine.
|
||
Thelastinstruction inanysubroutine isaReturn.Such
|
||
aninstruction needspecifynoaddress. Whentheprocessor
|
||
fetchesaReturninstruction, itsimplyreplaces thecurrent
|
||
contents oftheProgram Counter withtheaddressonthe
|
||
topofthestack.Thiscausestheprocessor toresumeexecu
|
||
tionofthecallingprogram atthepointimmediately foUow
|
||
ingtheoriginal CallInstruction.
|
||
Subroutines areoftenNested;thatis,onesubroutine
|
||
willsometimes callasecondsubroutine. Thesecondmay
|
||
callathird,andsoon.Thisisperfectly acceptable, aslong
|
||
astheprocessor hasenoughcapacity tostorethenecessary
|
||
returnaddresses, andthelogicalprovision fordoingso.In
|
||
otherwords,themaximum depthofnestingisdetermined
|
||
bythedepthofthestackitself.Ifthestackhasspacefor
|
||
storingthreereturnaddresses, thenthreelevelsofsubrou
|
||
tinesmaybeaccommodated.
|
||
Processors havedifferent waysofmaintaining stacks.
|
||
Somehavefacilities forthestorageofreturnaddresses built
|
||
intotheprocessor itself.Otherprocessors useareserved
|
||
areaofexternal memory asthestackandsimplymaintain a
|
||
Pointer register whichcontains theaddressofthemost
|
||
recentstackentry.Theexternal stackallowsvirtually un
|
||
limitedsubroutine nesting. Inaddition, iftheprocessor pro
|
||
videsinstructions thatcausethecontents oftheaccumulator
|
||
andothergeneralpurpose registerstobe"pushed" ontothe
|
||
stackor"popped" offthestackviatheaddressstoredinthe
|
||
stackpointer, multi-level interrupt processing (described
|
||
laterinthischapter) ispossible. Thestatusoftheprocessor
|
||
(i.e.,thecontents ofalltheregisters) canbesavedinthe
|
||
stackwhenaninterrupt isaccepted andthenrestored after
|
||
theinterrupt hasbeenserviced. Thisabilitytosavethepro
|
||
cessor'sstatusatanygiventimeispossible evenifaninter
|
||
ruptserviceroutine, itself,isinterrupted.
|
||
Instruction RegisterandDecoder:
|
||
Everycomputer hasaWordLengththatischaracteris
|
||
ticofthatmachine. Acomputer's wordlengthisusually
|
||
determined bythesizeofitsinternal storageelements and
|
||
interconnecting paths(referred toasBusses); forexample,
|
||
acomputer whoseregisters andbussescanstoreandtrans
|
||
ferabitsofinformation hasacharacteristic wordlengthof
|
||
8-bitsandisreferred toasana-bitparallelprocessor. An
|
||
eight-bit parallelprocessor generally findsitmostefficient
|
||
todealwitheight-bit binaryfields,andthememory asso
|
||
ciatedwithsuchaprocessor istherefore organized tostore
|
||
eightbitsineachaddressable memory location. Dataand
|
||
instructions arestoredinmemory aseight-bit binarynum
|
||
bers,orasnumbers thatareintegralmultiples ofeightbits:
|
||
16bits,24bits,andsoon.Thischaracteristic eight-bit field
|
||
isoftenreferredtoasaByte.
|
||
Eachoperation thattheprocessor canperform is
|
||
identified byauniquebyteofdataknownasanInstruction
|
||
|
||
===PAGE 11===
|
||
CodeorOperation Code.Aneight-bit wordusedasanin
|
||
struction codecandistinguish between 256alternative
|
||
actions, morethanadequate formostprocessors.
|
||
Theprocessor fetchesaninstruction intwodistinct
|
||
operations. First,theprocessor transmits theaddressinits
|
||
Program Counter tothememory. Thenthememory returns
|
||
theaddressed bytetotheprocessor. TheCPUstoresthis
|
||
instruction byteinaregister knownastheInstruction
|
||
Register, andusesittodirectactivities duringtheremainder
|
||
oftheinstruction execution.
|
||
Themechanism bywhichtheprocessor translates an
|
||
instruction codeintospecific processing actionsrequires
|
||
moreelaboration tha~wecanhereafford.Theconcept,
|
||
however, shouldbeintuitively cleartoanylogicdesigner.
|
||
Theeightbitsstoredintheinstruction registercanbede
|
||
codedandusedtoselectively activate oneofanumberof
|
||
outputlines,inthiscaseupto256lines.Eachlinerepre
|
||
sentsasetofactivities associated withexecution ofapar
|
||
ticularinstruction code.Theenabled linecanbecombined
|
||
w\thselected timingpulses,todevelop electrical signalsthat
|
||
canthenbeusedtoinitiatespecific actions. Thistransla
|
||
tionofcodeintoactionisperformed bytheInstruction
|
||
Decoder andbytheassociated controlcircuitry.
|
||
Aneight-bit instruction codeisoftensufficient to
|
||
specifyaparticular processing action.Therearetimes,how
|
||
ever,whenexecution oftheinstruction requires moreinfor
|
||
mationthaneightbitscanconvey.
|
||
Oneexample ofthisiswhentheinstruction refer
|
||
encesamemory location. Thebasicinstruction codeiden
|
||
tifiestheoperation tobeperformed, butcannotspecify
|
||
theobjectaddressaswell.Inacaselikethis,atwo-orthree
|
||
byteinstruction mustbeused.Successive instruction bytes
|
||
arestoredinsequentially adjacent memory locations, and
|
||
theprocessor performs twoorthreefetchesinsuccession to
|
||
obtainthefullinstruction. Thefirstbyteretrieved from
|
||
memory isplacedintheprocessor's instruction register, and
|
||
subsequent bytesareplacedintemporary storage; thepro
|
||
cessorthenproceeds withtheexecution phase.Suchan
|
||
instruction isreferredtoasVariable Length.
|
||
AddressRegister(s):
|
||
ACPUmayusearegisterorregister-pair toholdthe
|
||
addressofamemory location thatistobeaccessed for
|
||
data.Iftheaddressregister isProgrammable, (Le.,ifthere
|
||
areinstructions thatallowtheprogrammer toalterthe
|
||
contents oftheregister) theprogram can"build" anad-
|
||
dressintheaddress register priortoexecuting aMemory
|
||
Reference instruction (Le.,aninstruction thatreadsdata
|
||
frommemory, writesdatatomemory oroperates ondata
|
||
storedinmemory).
|
||
Arithmetic/Logic Unit(ALU):
|
||
Allprocessors containanarithmetic/logic unit,which
|
||
isoftenreferred tosimplyastheALU.TheALU,asits
|
||
nameimplies, isthatportion oftheCPUhardware which
|
||
1-3performs thearithmetic andlogicaloperations onthebinary
|
||
data.
|
||
TheALUmustcontainanAdderwhichiscapableof
|
||
combining thecontents oftworegisters inaccordance with
|
||
thelogicofbinaryarithmetic. Thisprovision permitsthe
|
||
processor toperform arithmetic manipulations onthedata
|
||
itobtainsfrommemory andfromitsotherinputs.
|
||
Usingonlythebasicadderacapableprogrammer can
|
||
writeroutines whichwillsubtract, multiply anddivide,giv
|
||
ingthemachine complete arithmetic capabilities. Inpractice,
|
||
however, mostALUsprovideotherbuilt-infunctions, in
|
||
cludinghardware subtraction, boolean logicoperations, and
|
||
shiftcapabiIities.
|
||
TheALUcontains FlagBitswhichspecifycertain
|
||
conditions thatariseinthecourseofarithmetic andlogical
|
||
manipulations. 'Flagstypically includeCarry,Zero,Sign,and
|
||
Parity.Itispossible toprogram jumpswhicharecondi
|
||
tionallydependent onthestatusofoneormoreflags.Thus,
|
||
forexample, theprogram maybedesigned tojumptoa
|
||
specialroutine ifthecarrybitissetfollowing anaddition
|
||
instruction.
|
||
ControlCircuitry:
|
||
Thecontrol circuitry istheprimary functional unit
|
||
withinaCPU.Usingclockinputs,thecontrol circuitry
|
||
maintains thepropersequence ofeventsrequired forany
|
||
processing task.Afteraninstruction isfetchedanddecoded,
|
||
thecontrolcircuitry issuestheappropriate signals(tounits
|
||
bothinternal andexternal totheCPU)forinitiating the
|
||
properprocessing action.Oftenthecontrolcircuitry willbe
|
||
capableofresponding toexternal signals,suchasaninter
|
||
ruptorwaitrequest. AnInterrupt requestwillcausethe
|
||
control circuitry totemporarily interrupt mainprogram
|
||
execution, jumptoaspecialroutinetoservicetheinterrupt
|
||
ingdevice,thenautomatically returntothemainprogram.
|
||
AWaitrequest isoftenissuedbyamemory orI/Oelement
|
||
thatoperates slowerthantheCPU.Thecontrol circuitry
|
||
willidletheCPUuntilthememory orI/Oportisreadywith
|
||
thedata.
|
||
COMPUTER OPERATIONS
|
||
Therearecertainoperations thatarebasictoalmost
|
||
anycomputer. Asoundunderstanding ofthesebasicopera
|
||
tionsisanecessary prerequisite toexamining thespecific
|
||
operations ofaparticular computer.
|
||
Timing:
|
||
Theactivities ofthecentralprocessor arecyclical. The
|
||
processor fetches aninstruction, performs theoperations
|
||
required, fetches thenextinstruction, andsoon.This
|
||
orderlysequence ofeventsrequires precisetiming,andthe
|
||
CPUtherefore requires afreerunning oscillator clockwhich
|
||
furnishes thereference forallprocessor actions. Thecom
|
||
binedfetchandexecution ofasingleinstruction isreferred
|
||
toasanInstruction Cycle.Theportionofacycleidentified
|
||
|
||
===PAGE 12===
|
||
withaclearlydefinedactivityiscalledaState.Andtheinter
|
||
valbetween pulsesofthetimingoscillator isreferredtoasa
|
||
ClockPeriod.Asageneralrule,oneormoreclockperiods
|
||
are necessary forthecompletion ofastate,andthereare
|
||
severalstatesinacycle.
|
||
Instruction Fetch:
|
||
Thefirststate(s) ofanyinstruction cyclewillbe
|
||
dedicated tofetching thenextinstruction. TheCPUissuesa
|
||
readsignalandthecontents oftheprogram counteraresent
|
||
tomemory, whichresponds byreturning thenextinstruc
|
||
tionword.Thefirstbyteoftheinstruction isplacedinthe
|
||
instruction register. Iftheinstruction consistsofmorethan
|
||
onebyte,additional statesarerequired tofetcheachbyte
|
||
oftheinstruction. Whentheentireinstruction ispresentin
|
||
theCPU,theprogram counter isincremented (inprepara
|
||
tionforthenextinstruction fetch)andtheinstruction is
|
||
decoded. Theoperation specified intheinstruction willbe
|
||
executed intheremaining statesoftheinstruction cycle.
|
||
Theinstruction maycallforamemory readorwrite,an
|
||
inputoroutputand/oraninternalCPUoperation, suchas
|
||
aregister-to-register transferoranadd-registers operation.
|
||
MemoryRead:
|
||
Aninstruction fetchismerelyaspecialmemory read
|
||
operation thatbringstheinstruction totheCPU'sinstruc
|
||
tionregister.Theinstruction fetchedmaythencallfordata
|
||
tobereadfrommemory intotheCPU.TheCPUagainissues
|
||
areadsignalandsendsthepropermemory address; memory
|
||
responds byreturning therequested word.Thedatare
|
||
ceivedisplacedintheaccumulator oroneoftheothergen
|
||
eralpurposeregisters (nottheinstruction register).
|
||
MemoryWrite:
|
||
Amemory writeoperation issimilartoareadexcept
|
||
-forthedirection ofdataflow.TheCPUissuesawrite
|
||
signal,sendsthepropermemory address,thensendsthedata
|
||
wordtobewrittenintotheaddressed memory location.
|
||
Wait(memory synchronization):
|
||
Aspreviously stated,theactivities oftheprocessor
|
||
aretimedbyamasterclockoscillator. Theclockperiod
|
||
determines thetimingofallprocessing activity.
|
||
Thespeedoftheprocessing cycle,however, islimited
|
||
bythememory's AccessTime.Oncetheprocessor hassenta
|
||
readaddresstomemory, itcannotproceeduntilthememory
|
||
hashadtimetorespond. Mostmemories arecapableof
|
||
responding muchfasterthantheprocessing cyclerequires.
|
||
Afew,however, cannotsupplytheaddressed bytewithin
|
||
theminimum timeestablished bytheprocessor's clock.
|
||
Therefore aprocessor shouldcontainasynchroniza
|
||
tionprovision, whichpermitsthememory torequestaWait
|
||
state.Whenthememory rec.eivesareadorwriteenablesig
|
||
nal,itplacesarequestsignalontheprocessor's READY line,
|
||
causingtheCPUtoidletemporarily. Afterthememory has
|
||
1-4hadtimetorespond, itfreestheprocessor's READY line,
|
||
andtheinstruction cycleproceeds.
|
||
Input/Output:
|
||
InputandOutputoperations aresimilartomemory
|
||
readandwriteoperations withtheexception thataperi
|
||
pherall/O deviceisaddressed insteadofamemory location.
|
||
TheCPUissuestheappropriate inputoroutputcontrol
|
||
signal,sendstheproperdeviceaddressandeitherreceives
|
||
thedatabeinginputorsendsthedatatobeoutput.
|
||
Datacanbeinput/output ineitherparallelorserial
|
||
form.Alldatawithinadigitalcomputer isrepresented in
|
||
binarycodedform.Abinarydatawordconsistsofagroup
|
||
ofbits;eachbitiseitheraoneorazero.ParallelI/Ocon
|
||
sistsoftransferring allbitsinthewordatthesametime,
|
||
onebitperline.SerialI/Oconsistsoftransferring onebit
|
||
atatimeona single line.Naturally serialI/Oismuch
|
||
s.lower,butitrequires considerably lesshardware thandoes
|
||
parallelI/O.
|
||
Interrupts:
|
||
Interrupt. provIsions areincluded onmanycentral
|
||
processors, asameansofimproving theprocessor's effi
|
||
ciency.Consider thecaseofacomputer thatisprocessing a
|
||
largevolumeofdata,portions ofwhicharetobeoutput
|
||
toaprinter.TheCPUcanoutputabyteofdatawithina
|
||
singlemachine cyclebutitmaytaketheprintertheequiva
|
||
lentofmanymachine cyclestoactually printthecharacter
|
||
specified bythedatabyte.TheCPUcouldthenremainidle
|
||
waitinguntiltheprintercanacceptthenextdatabyte.If
|
||
aninterrupt capability isimplemented onthecomputer, the
|
||
CPUcanoutputadatabytethenreturntodataprocessing.
|
||
Whentheprinter isreadytoacceptthenextdatabyte,it
|
||
canrequestaninterrupt. WhentheCPUacknowledges the
|
||
interrupt, itsuspends mainprogram execution andauto
|
||
matically branches toaroutinethatwilloutputthenext
|
||
databyte.Afterthebyteisoutput, theCPUcontinues
|
||
withmainprogram execution. Notethatthisis,inprinciple,
|
||
quitesimilartoasubroutine call,exceptthatthejumpis
|
||
initiated externally ratherthanbytheprogram.
|
||
Morecomplex interrupt structures arepossible, in
|
||
whichseveralinterrupting devicessharethesameprocessor
|
||
buthavedifferent priority levels.Interruptive processing is
|
||
animportant featurethatenablesmaximum untilization of
|
||
aprocessor's capacity forhighsystemthroughput.
|
||
Hold:
|
||
Another important featurethatimproves thethrough
|
||
putofaprocessor istheHold.Theholdprovision enables
|
||
DirectMemory Access(DMA)operations.
|
||
Inordinary inputandoutputoperations, theprocessor
|
||
itselfsupervises theentiredatatransfer. Information tobe
|
||
placedinmemory istransferred fromtheinputdevicetothe
|
||
processor, andthenfromtheprocessor tothedesignated
|
||
memory location. Insimilarfashion, information thatgoes
|
||
_...
|
||
|
||
===PAGE 13===
|
||
frommemory tooutputdevices goesbywayofthe
|
||
processor.
|
||
Someperipheral devices, however, arecapable of
|
||
transferring information toandfrommemory muchfaster
|
||
thantheprocessor itselfcanaccomplish thetransfer. Ifany
|
||
appreciable quantity ofdatamustbetransferred toorfrom
|
||
suchadevice,thensystemthroughput willbeincreased by
|
||
1-5havingthedeviceaccomplish thetransfer directly. Thepro
|
||
cessormusttemporarily suspend itsoperation duringsucha
|
||
transfer, toprevent conflicts thatwouldariseifprocessor
|
||
andperipheral deviceattempted toaccessmemory simul
|
||
taneously. Itisforthisreasonthataholdprovision isin
|
||
cludedonsomeprocessors.
|
||
|
||
===PAGE 14===
|
||
|
||
|
||
===PAGE 15===
|
||
The8080isacomplete 8-bitparallel,centralprocessor
|
||
unit(CPU)foruseingeneralpurposedigitalcomputer sys
|
||
tems.Itisfabricated onasingleLSIchip(seeFigure2-1).
|
||
usingIntel'sn-channel silicongateMaSprocess.The8080
|
||
transfers dataandinternalstateinformation viaan8-bit,
|
||
bidirectional 3-stateDataBus(00-07). Memory andperi
|
||
pheraldeviceaddresses aretransmitted overaseparate 16-bit3-stateAddressBus(AO-A15).Sixtimingandcontrol
|
||
outputs(SYNC,DBIN,WAIT,WR, HLDAandINTE)eman
|
||
atefromthe8080,whilefourcontrolinputs(READY,
|
||
HOLD,INTandRESET), fourpowerinputs(+12v,+!5v,
|
||
-5v,andGND)andtwoclockinputs (<1>1and<1>2)areac
|
||
ceptedbythe8080.
|
||
Figure2-1.8080 Photomicrograph WithPinDesignations
|
||
2-1A,O 1
|
||
GNO 2
|
||
043
|
||
Os 4
|
||
060.-.5
|
||
07 6
|
||
037
|
||
O28
|
||
0,0 9
|
||
DO0 10
|
||
-5V 11
|
||
RESET 12
|
||
HOLD 13
|
||
INT 14
|
||
¢2 15
|
||
INTE0 16
|
||
DBIN0 17
|
||
WR 18
|
||
SYNC 19
|
||
+5V 2040
|
||
39
|
||
38
|
||
37
|
||
36
|
||
35
|
||
34
|
||
INTE~ 33
|
||
328080 31
|
||
30
|
||
29
|
||
28
|
||
27
|
||
26
|
||
25
|
||
24
|
||
23
|
||
22
|
||
21A"
|
||
A14
|
||
A'3
|
||
A'2
|
||
oA,s
|
||
oAg
|
||
As
|
||
oA7
|
||
A6
|
||
As
|
||
oA4
|
||
A3
|
||
+12V
|
||
A2
|
||
A,
|
||
Ao
|
||
WAIT
|
||
READY
|
||
tp,
|
||
HLOA
|
||
|
||
===PAGE 16===
|
||
ARCHITECTURE OFTHE8080CPU
|
||
The8080CPUconsists ofthefollowing functional
|
||
units:
|
||
•Register arrayandaddresslogic
|
||
•Arithmetic andlogicunit(ALU)
|
||
• Instruction registerandcontrolsection
|
||
•Bi-directional, 3-statedatabusbuffer
|
||
Figure2-2illustrates thefunctional blockswithin
|
||
the8080CPU.
|
||
Registers:
|
||
Theregister sectionconsists ofastaticRAMarray
|
||
organized intosix16-bitregisters:
|
||
•Program counter (PC)
|
||
•Stackpointer(SP)
|
||
•Six8-bitgeneralpurpose registers arranged inpairs,
|
||
referredtoasS,C;D,E;andH,L
|
||
• Atemporary registerpaircalledW,Z
|
||
Theprogram counter maintains thememory address
|
||
ofthecurrentprogram instruction andisincremented auto-matically duringeveryinstruction fetch.Thestackpointer
|
||
maintains theaddressofthenextavailable stacklocation in
|
||
memory. Thestackpointer canbeinitialized touseany
|
||
portionofread-write memory asastack.Thestackpointer
|
||
isdecremented whendatais"pushed" ontothestackand
|
||
incremented whendatais"popped" offthestack(Le.,the
|
||
stackgrows"downward").
|
||
Thesixgeneralpurpose registers canbeusedeitheras
|
||
singleregisters (8-bit)orasregister pairs(16-bit). The
|
||
temporary register pair,W,Z,isnotprogram addressable
|
||
andisonlyusedfortheinternalexecution ofinstructions.
|
||
Eight-bit databytescanbetransferred between the
|
||
internal busandtheregister arrayviatheregister-select
|
||
multiplexer. Sixteen-bit transfers canproceed between the
|
||
register arrayandtheaddress latchortheincrementer /
|
||
decrementer circuit.Theaddress latchreceives datafrom
|
||
anyofthethreeregister pairsanddrivesthe16address
|
||
output buffers (AO-A15),aswellastheincrementer /
|
||
decrementer circuit.Theincrementer/decrementer circuit
|
||
receives datafromtheaddress latchandsendsitto
|
||
theregister array.The16-bitdatacanbeincremented or
|
||
decremented orsimplytransferred between registers.
|
||
81-01RECTIONAL
|
||
DATABUS
|
||
A15-Ao
|
||
ADDRESS BUSRESETW(8) Z(8)
|
||
TEMPREG. TEMPREG.
|
||
B(8) C(8) ...0REG. REG. w
|
||
INSTRUCTION..J0(8) E(8) wDECODER enREG. REG.AND a:
|
||
MACHINEwH (8) L(8) REGISTER ...
|
||
CYCLEen REG. REG. ARRAY
|
||
ENCODINGa(16) wa: STACKPOINTER
|
||
(16)
|
||
PROGRAM COUNTER
|
||
DATABUSINTERRUPT HOLD WAIT
|
||
WRITECONTROL CONTROL CONTROL CONTROL SYNCCLOCKS
|
||
ACKPOWER1-" +12VSUPPLIES---.+5V
|
||
---.-5V
|
||
..---.GND
|
||
Figure2-2.8080CPUFunctional BlockDiagram
|
||
2-2
|
||
|
||
===PAGE 17===
|
||
Arithmetic andLogicUnit(ALU):
|
||
TheALUcontains thefollowing registers:
|
||
•An8-bitaccumulator
|
||
•An8-bittemporary accumulator (ACT)
|
||
• A5-bitflagregister: zero,carry,sign,parityand
|
||
auxiliary carry
|
||
•An8-bittemporary register(TMP)
|
||
Arithmetic, logicalandrotateoperations areper
|
||
formed intheALU.TheALUisfedbythetemporary
|
||
register(TMP)andthetemporary accumulator (ACT)and
|
||
carryflip-flop. Theresultoftheoperation canbetrans
|
||
ferredtotheinternal busortotheaccumulator; theALU
|
||
alsofeedstheflagregister.
|
||
Thetemporary register (TMP)receives information
|
||
fromtheinternal busandcansendallorportions ofitto
|
||
theALU,theflagregisterandtheinternal bus.
|
||
Theaccumulator (ACC)canbeloadedfromtheALU
|
||
andtheinternal busandcantransferdata ~othetemporary
|
||
accumulator (ACT)andtheinternal bus.Thecontents of
|
||
theaccumulator (ACC)andtheauxiliary carryflip-flop can
|
||
betestedfordecimal correction duringtheexecution ofthe
|
||
DAAinstruction (seeChapter 4).
|
||
Instruction RegisterandControl:
|
||
Duringaninstruction fetch,thefirstbyteofanin
|
||
struction (containing theOPcode)istransferred fromthe
|
||
internalbustothe8-bitinstruction register.
|
||
Thecontents oftheinstruction registerare,inturn,
|
||
available totheinstruction decoder. Theoutputofthe
|
||
decoder, combined withvarioustimingsignals, provides
|
||
thecontrol signalsfortheregister array,ALUanddata
|
||
bufferblocks.Inaddition, theoutputsfromtheinstruction
|
||
decoder andexternal control signalsfeedthetimingand
|
||
statecontrol sectionwhichgenerates thestateandcycle
|
||
timingsignals.
|
||
DataBusBuffer:
|
||
This8-bitbidirectional 3-state bufferisusedto
|
||
isolatetheCPU'sinternal busfromtheexternal databus.
|
||
(DOthrough 07).Intheoutputmode,theinternal bus
|
||
content isloadedintoan8-bitlatchthat,inturn,drivesthe
|
||
databusoutputbuffers. Theoutputbuffersareswitched
|
||
offduringinputornon-transfer operations.
|
||
Dur\ngtheinputmode,datafromtheexternal databus
|
||
istransferred totheinternal bus.Theinternal busispre
|
||
charged atthebeginning ofeachinternal state,exceptfor
|
||
thetransfer state(T3-described laterinthischapter).
|
||
2-3THEPROCESSOR CYCLE
|
||
Aninstruction cycleisdefined asthetimerequired
|
||
tofetchandexecute aninstruction. Duringthefetch,a
|
||
selected instruction (one,twoorthreebytes)isextracted
|
||
frommemory anddeposited intheCPU'sinstruction regis
|
||
ter.Duringtheexecution phase,theinstruction isdecoded
|
||
andtranslated intospecificprocessing activities.
|
||
Everyinstruction cycle consists ofone,two,three,
|
||
fourorfivemachine cycles.Amachine cycleisrequired
|
||
eachtimetheCPUaccesses memory oranI/Oport.The
|
||
fetchportionofaninstruction cyclerequires onemachine
|
||
cycleforeachbytetobefetched. Theduration oftheexecu
|
||
tionportionoftheinstruction cycledepends onthekind
|
||
ofinstruction thathasbeenfetched. Someinstructions do
|
||
notrequireanymachine cyclesotherthanthosenecessary
|
||
tofetchtheinstruction; otherinstructions, however, re
|
||
quireadditional machine cyclestowriteorreaddatato/
|
||
frommemory orI/Odevices. TheDADinstruction isan
|
||
exception inthatitrequires twoadditional machine cycles
|
||
tocomplete aninternal register-pair add(seeChapter 4).
|
||
Eachmachine cycleconsists ofthree,fourorfive
|
||
states.Astateisthesmallest unitofprocessing activityand
|
||
isdefined astheinterval between twosuccessive positive~
|
||
goingtransitions ofthe¢1drivenclockpulse.The8080
|
||
isdrivenbyatwo-phase clockoscillator. Allprocessing activ
|
||
itiesarereferredtotheperiodofthisclock.Thetwonon
|
||
overlapping clockpulses,labeled¢1andcP2,arefurnished
|
||
byexternal circuitry. ItisthecPlclockpulsewhichdivides
|
||
eachmachine cycleintostates.Timing logicwithinthe
|
||
8080usestheclockinputstoproduce aSYNCpulse,
|
||
whichidentifies thebeginning ofeverymachine cycle.The
|
||
SYNCpulseistriggered bythelow-to-high transition ofcP2,
|
||
asshowninFigure2-3.
|
||
FIRSTSTATEOF
|
||
*EVERY MACHINE
|
||
CYCLE
|
||
4>1
|
||
SYNC
|
||
*SYNCDOESNOTOCCURINTHESECOND ANDTHIRDMACHINE
|
||
CYCLES OFADADINSTRUCTION SINCETHESEMACHINE CYCLES
|
||
AREUSEDFORANINTERNAL REGISTER-PAIR ADD.
|
||
Figure2-3.1>1,</J2 AndSYNCTiming
|
||
Therearethreeexceptions tothedefinedduration of
|
||
astate.TheyaretheWAITstate,thehold(HLOA)state
|
||
andthehalt(HLTA)state,described laterinthischapter.
|
||
BecausetheWAIT,theHLOA,andtheHLTAstatesdepend
|
||
uponexternal events,theyarebytheirnatureofindeter
|
||
minatelength.Eventheseexceptional states,however, must
|
||
|
||
===PAGE 18===
|
||
besynchronized withthepulsesofthedrivingclock.Thus,
|
||
theduration ofallstatesareintegralmultiples oftheclock
|
||
period.
|
||
Tosummarize then,eachclockperiodmarksastate;
|
||
threetofivestatesconstitute amachine cycle;andoneto
|
||
fivemachine cyclescomprise aninstruction cycle.Afull
|
||
instruction cyclerequires anywhere fromfourtoeight
|
||
teenstatesforitscompletion, depending onthekindofin
|
||
struction involved.
|
||
Machine CycleIdentification:
|
||
Withtheexception oftheDADinstruction, thereis
|
||
justoneconsideration thatdetermines howmanymachine
|
||
cyclesarerequired inanygiveninstruction cycle:thenum
|
||
beroftimesthattheprocessor mustreference amemory
|
||
address oranaddressable peripheral device,inorderto
|
||
fetchandexecute theinstruction. Likemanyprocessors,
|
||
the8080issoconstructed thatitcantransmit onlyone
|
||
addresspermachine cycle.Thus,ifthefetchandexecution
|
||
ofaninstruction requires twomemory references, thenthe
|
||
instruction cycleassociated withthatinstruction consistsof
|
||
twomachine cycles.Iffivesuchreferences arecalledfor,
|
||
thentheinstruction cyclecontains fivemachine cycles.
|
||
Everyinstruction cyclehasatleastonereference to
|
||
memory, duringwhichtheinstruction isfetched. Anin
|
||
struction cyclemustalwayshaveafetch,eveniftheexecu
|
||
tionoftheinstruction requires nofurtherreferences to
|
||
memory. Thefirstmachine cycleineveryinstruction cycle
|
||
istherefore aFETCH. Beyondthat,therearenofastrules.
|
||
Itdepends onthekindofinstruction thatisfetched.
|
||
Consider someexamples. Theadd-register (ADDr)
|
||
instruction isaninstruction thatrequires onIyasingle
|
||
machine cycle(FETCH) foritscompletion. Inthisone-byte
|
||
instruction, thecontents ofoneoftheCPU'ssixgeneral
|
||
purpose registers isaddedtotheexisting contents ofthe
|
||
accumulator. Sincealltheinformation necessary toexecute
|
||
thecommand iscontained intheeightbitsoftheinstruction
|
||
code,onlyonememory reference isnecessary. Threestates
|
||
areusedtoextracttheinstruction frommemory, andone
|
||
additional stateisusedtoaccomplish thedesiredaddition.
|
||
Theentireinstruction cyclethusrequiresonlyonemachine
|
||
cyclethatconsistsoffourstates,orfourperiodsoftheex
|
||
ternalclock.
|
||
Suppose now,however, thatwewishtoaddthecon
|
||
tentsofaspecificmemory locationtotheexistingcontents
|
||
oftheaccumulator (ADDM).Although thisisquitesimilar
|
||
inprinciple totheexample justcited,severaladditional
|
||
stepswillbeused.Anextramachine cyclewillbeused,in
|
||
ordertoaddressthedesiredmemory location.
|
||
Theactualsequence isasfollows. Firsttheprocessor
|
||
extracts frommemory theone-byte instruction wordad
|
||
dressed byitsprogram counter. Thistakesthreestates.
|
||
Theeight-bit instruction wordobtained duringtheFETCH
|
||
machine cycleisdeposited intheCPU'sinstruction register
|
||
andusedtodirectactivities duringtheremainder ofthe
|
||
instruction cycle.Next,theprocessor sendsout,asanaddress,
|
||
2-4thecontents ofitsHandLregisters. Theeight-bit data
|
||
wordreturned duringthisMEMORY READmachine cycle
|
||
isplacedinatemporary registerinsidethe8080CPU.By
|
||
nowthreemoreclockperiods(states)haveelapsed. Inthe
|
||
seventhandfinalstate,thecontents ofthetemporary regis
|
||
terareaddedtothoseoftheaccumulator. Twomachine
|
||
cycles,consisting ofsevenstatesinall,complete the
|
||
"ADDMilinstruction cycle.
|
||
Attheopposite extreme isthesaveHandLregisters
|
||
(SHLD) instruction, whichrequires fivemachine cycles.
|
||
Duringan"SHLD"instruction cycle,thecontents ofthe
|
||
processor's HandLregisters aredeposited intwosequen
|
||
tiallyadjacent memory locations; thedestination isindi
|
||
catedbytwoaddressbyteswhicharestoredinthetwo
|
||
memory locations immediately following theoperation code
|
||
byte.Thefollowing sequence ofeventsoccurs:
|
||
(1)AFETCH machine cycle,consisting offour
|
||
states.Duringthefirstthreestatesofthis
|
||
machine cycle,theprocessor fetchestheinstruc
|
||
tionindicated byitsprogram counter. Thepro
|
||
gramcounter isthenincremented. Thefourth
|
||
stateisusedforinternal instruction decoding.
|
||
(2)AMEMORY READmachine cycle,consisting
|
||
ofthreestates.Duringthismachine cycle,the
|
||
byteindicated bytheprogram counter isread
|
||
frommemory andplacedintheprocessor's
|
||
Zregister. Theprogram counter isincremented
|
||
again.
|
||
(3)Another MEMORY READmachine cycle,con
|
||
sistingofthreestates,inwhichthebyteindica-
|
||
tedbytheprocessor's program counter isread
|
||
frommemory andplacedintheWregister.The
|
||
program counter isincremented, inanticipation
|
||
ofthenextinstruction fetch.
|
||
(4)AMEMORY WRITE machine cycle,ofthree
|
||
states,inwhichthecontents oftheLregister
|
||
aretransferred tothememory location pointed
|
||
tobythepresentcontents oftheWandZregis
|
||
ters.Thestatefollowing thetransfer isusedto
|
||
increment theW,Zregisterpairsothatitindi
|
||
catesthenextmemory locationtoreceivedata.
|
||
(5)AMEMORY WRITE machine cycle,ofthree
|
||
states,inwhichthecontents oftheHregister
|
||
aretransferred tothenewmemory location
|
||
pointedtobytheW,Zregisterpair.
|
||
Insummary, the"SHLD" instruction cyclecontains
|
||
fivemachine cyclesandtakes16statestoexecute.
|
||
Mostinstructions fallsomewhere between theex
|
||
tremestypified bythe"ADDr"andthe"SHLD" \ostruc
|
||
tions.Theinput(INP)andtheoutput(OUT)instructions,
|
||
forexample, requirethreemachine cycles:aFETCH, to
|
||
obtaintheinstruction; aMEMORY READ,toobtainthe
|
||
addressoftheobjectperipheral; andanINPUToranOUT
|
||
PUTmachine cycle,tocomplete thetransfer.
|
||
|
||
===PAGE 19===
|
||
Whilenooneinstruction cyclewillconsistofmore
|
||
thenfivemachine cycles,thefollowing tendifferent types
|
||
ofmachine cyclesmayoccurwithinaninstruction cycle:
|
||
(1)FETCH (M1)
|
||
(2)MEMORY READ
|
||
(3)MEMORYWRITE
|
||
(4)STACK REAO
|
||
(5)STACK WRITE
|
||
(6)INPUT
|
||
(7)OUTPUT
|
||
(8)INTERRUPT
|
||
(9)HALT
|
||
(10)HALT. INTERRUPT
|
||
Themachine cyclesthatactually dooccurinapar
|
||
ticularinstruction cycledepend uponthekindofinstruc
|
||
tion,withtheoverriding stipulation thatthefirstmachine
|
||
cycleinanyinstruction cycleisalwaysaFETCH.
|
||
Theprocessor identifies themachine cycleinprog
|
||
ressbytransmitting aneight-bit statuswordduringthefirst
|
||
stateofeverymachine cycle.Updated statusinformation is
|
||
presented onthe8080'sdatalines(00-07), duringthe
|
||
SYNCinterval. Thisdatashouldbesavedinlatches, and
|
||
usedtodevelop controlsignalsforexternal circuitry. Table
|
||
2-1showshowthepositive-true statusinformation isdis
|
||
tributed ontheprocessor's databus.
|
||
Statussignalsareprovided principally forthecontrol
|
||
ofexternal circuitry. Simplicity ofinterface, ratherthan
|
||
machine cycleidentification, dictates thelogicaldefinition
|
||
ofindividual statusbits.Youwilltherefore observethat
|
||
certainprocessor machine cyclesareuniquely identified by
|
||
asinglestatusbit,butthatothersarenot.TheM1status
|
||
bit(06),forexample, unambiguously identifies aFETCH
|
||
machine cycle.ASTACK REAO,ontheotherhand,is
|
||
indicated bythecoincidence ofSTACK andMEMR sig
|
||
nals.Machine cycleidentification dataisalsovaluable in
|
||
thetestandde-bugging phasesofsystemdevelopment.
|
||
Table2-1liststhestatusbitoutputs foreachtypeof
|
||
machine cycle.
|
||
StateTransition Sequence:
|
||
Everymachine cyclewithinaninstruction cyclecon
|
||
sistsofthreetofiveactivestates(referred toasT1,T2,T3,
|
||
T4,T5orTW).Theactualnumber ofstatesdepends upon
|
||
theinstruction beingexecuted, andontheparticular ma
|
||
chinecyclewithinthegreaterinstruction cycle.Thestate
|
||
transition diagram inFigure2-4showshowthe8080pro
|
||
ceedsfromstatetostateinthecourseofamachine cycle.
|
||
Thediagram alsoshowshowtheREADY, HOLD, and
|
||
INTERRUPT linesaresampled duringthemachine cycle,
|
||
andhowtheconditions ontheselinesmaymodifythe
|
||
2-5basictransition sequence. Inthepresentdiscussion, weare
|
||
concerned onlywiththebasicsequence andwiththe
|
||
READY function. TheHOLDandINTERRUPT functions
|
||
willbediscussed later.
|
||
The8080CPUdoesnotdirectly indicate itsinternal
|
||
statebytransmitting a"state contro'" output during
|
||
eachstate;instead,the8080supplies directcontroloutput
|
||
(INTE,HLOA, OBIN,WRandWAIT)forusebyexternal
|
||
circuitry.
|
||
Recallthatthe8080passesthrough atleastthree
|
||
statesineverymachine cycle,witheachstatedefined by
|
||
successive low-to-high transitions ofthe¢1clock.Figure
|
||
2-5showsthetimingrelationships inatypical FETCH
|
||
machine cycle.Eventsthatoccurineachstatearereferenced
|
||
totransitions ofthe¢1and¢2clockpulses.
|
||
TheSYNCsignalidentifies thefirststate(T1)in
|
||
everymachine cycle.AsshowninFigure2-5,theSYNC
|
||
signalisrelatedtotheleadingedgeofthe¢2clock.Thereis
|
||
adelay(tOC)between thelow-to-high transition of¢2and
|
||
thepositive-going edgeoftheSYNCpulse.Therealsoisa
|
||
corresponding delay(alsotOC)between thenext¢2pulse
|
||
andthefallingedgeoftheSYNCsignal.Statusinformation
|
||
isdisplayed on00-D7duringthesamecP2tocP2interval.
|
||
Switching ofthestatussignalsislikewise controlled by<1>2.
|
||
Therisingedgeof¢2duringT1alsoloadsthepro
|
||
cessor's address lines(AO-A15).Theselinesbecome stable
|
||
withinabriefdelay(tDA)ofthecP2clocking pulse,and
|
||
theyremainstableuntilthefirst¢2pulseafterstateT3.
|
||
Thisgivestheprocessor ampletimetoreadthedatare
|
||
turnedfrommemory.
|
||
Oncetheprocessor hassentanaddresstomemory,
|
||
thereisanopportunity forthememory torequestaWAIT.
|
||
Thisitdoesbypullingtheprocessor's READY linelow,
|
||
priortothe"Ready set-up" interval (tRS)whichoccurs
|
||
duringthe(/)2pulsewithinstateT2orTW.Aslongasthe
|
||
REAOY lineremains low,theprocessor willidle,givingthe
|
||
memory timetorespond totheaddressed datarequest.
|
||
RefertoFigure2-5.
|
||
Theprocessor responds toawaitrequestbyentering
|
||
analternative state(TW)attheendofT2,ratherthanpro
|
||
ceedingdirectly totheT3state.EntryintotheTWstateis
|
||
indicated byaWAITsignalfromtheprocessor, acknowledg
|
||
ingthememory's request. Alow-to-high transition onthe
|
||
WAITlineistriggered bytherisingedgeofthe(/)1clockand
|
||
occurswithinabriefdelay(tOC)oftheactualentryinto
|
||
theTWstate.
|
||
Awaitperiodmaybeofindefinite duration. Thepro
|
||
cessorremains inthewaitingcondition untilitsREADY line
|
||
againgoeshigh.AREADY indication mustprecedethefail
|
||
ingedgeofthe(/)2clockbyaspecified interval (tRS),in
|
||
ordertoguarantee anexitfromtheTWstate.Thecycle
|
||
maythenproceed, beginning withtherisingedgeofthe
|
||
next(/)1clock.AWAITintervalwilltherefore consistofan
|
||
integralnumberofTWstatesandwillalwaysbeamultiple
|
||
oftheclockperiod.
|
||
|
||
===PAGE 20===
|
||
Symbols
|
||
INTA*
|
||
STACK°2
|
||
HLTA°3OUT°4
|
||
M,°5
|
||
INP*°6
|
||
MEMR* 07Instructions forthe8080requirefromonetofivemachine
|
||
cyclesforcomplete execution. The8080sendsout8bitof
|
||
statusinformatton onthedatabusatthebeginning ofeach
|
||
machine cycle(duringSYNCtime).Thefollowing tabledefines
|
||
thestatusinformation.
|
||
STATUS INFORMATION DEFINITION
|
||
DataBus
|
||
Bit Definition
|
||
00Acknowledge signalforINTERRUPT re
|
||
quest.Signalshouldbeusedtogateare
|
||
startinstruction ontothedatabuswhen
|
||
OBINisactive.
|
||
0,Indicates thattheoperation inthecurrent
|
||
machine cyclewillbeaWRITEmemory
|
||
orOUTPUT function (WO=O).Otherwise,
|
||
aREAOmemory orINPUToperation will
|
||
beexecuted.
|
||
Indicates thattheaddress busholdsthe
|
||
pushdown stackaddressfromtheStack
|
||
Pointer.
|
||
Acknowledge signalforHALTinstruction.
|
||
Indicatesthattheaddressbuscontains the
|
||
addressofanoutputdeviceandthedata
|
||
buswillcontain theoutputdatawhen
|
||
WRisactive.
|
||
Provides asignaltoindicatethattheCPU
|
||
isinthefetchcycleforthefirstbyteof
|
||
aninstruction.
|
||
Indicates thattheaddressbuscontains the
|
||
addressofaninputdeviceandtheinput
|
||
datashouIdbeplacedonthedatabus
|
||
whenOBINisactive.
|
||
Designates thatthedatabuswillbeused
|
||
formemory readdata.
|
||
*Thesethreestatusbitscanbeusedtocontrol
|
||
theflowofdataontothe8080databus.
|
||
STATUS WORDCHART
|
||
DOINTA
|
||
02STACK
|
||
03HLTA
|
||
04OUT
|
||
06 INP
|
||
07MEMR
|
||
Table2-1.8080StatusBitDefinitions
|
||
2-68080STATUS LATCH
|
||
o10o90,o8
|
||
2 7
|
||
033
|
||
8080044
|
||
055
|
||
~66
|
||
7
|
||
SYNC19-
|
||
OBIN~
|
||
01 02STATUS
|
||
22 15LATCH
|
||
--2.01 DO~
|
||
5~~~9 ~16 .lL.
|
||
18 8212 17
|
||
20 JL -- 22~ CLOCKGEN.(olTTl)
|
||
&DRIVER
|
||
~r;;CLR
|
||
OS2MOOS,
|
||
13 12Y1
|
||
I I~
|
||
T2
|
||
01
|
||
SYNC
|
||
OATA1------ ''---t--t--
|
||
STATUS......-.----+001'----1
|
||
TYPEOFMACHINE CYCLE
|
||
IINTA
|
||
W6
|
||
STACK
|
||
HlTA
|
||
OUT
|
||
M1
|
||
INP
|
||
MEMR
|
||
DBIN
|
||
|
||
===PAGE 21===
|
||
G)_RESETTill
|
||
READY+HLTA
|
||
HOLD(3)SETINTERNAL
|
||
HOLDF/F
|
||
RESETINTERNAL
|
||
HOLDF/FINT.INTEYES
|
||
I
|
||
I
|
||
I
|
||
I(31
|
||
IHOLD
|
||
IMODE
|
||
I
|
||
I
|
||
I
|
||
I__.JSETINTERNAL
|
||
HOLDF/FYES(2)
|
||
READY. HLTA
|
||
NO
|
||
READY ~~
|
||
I...-------------~ READY
|
||
7
|
||
?~~----
|
||
YES
|
||
NO
|
||
RESETHLTA
|
||
NO
|
||
NORESETINTERNAL
|
||
HOLDF/FHOLD
|
||
SETINTERNAL
|
||
INTF/F
|
||
(1),NTEF/FISRESETIFINTERNAL INTF/FISSET.
|
||
(2),NTERNAL INTF/FISRESETIFINTEF/FISRESET.
|
||
(3)SEEPAGE2-13.
|
||
Figure2-4.CPUStateTransition Diagram
|
||
2-7
|
||
|
||
===PAGE 22===
|
||
TheeventsthattakeplaceduringtheT3stateare
|
||
determined bythekindofmachine cycleinprogress. Ina
|
||
FETCH machine cycle,theprocessor interprets thedataon
|
||
itsdatabusasaninstruction. DuringaMEMORY READor
|
||
aSTACK READ,dataonthisbusisinterpreted asadata
|
||
word.Theprocessor outputs dataonthisbusduringa
|
||
MEMORY WRITE machine cycle.DuringI/Ooperations,
|
||
theprocessor mayeithertransmit orreceivedata,de
|
||
pending onwhether anOUTPUT oranINPUToperation
|
||
isinvolved.
|
||
Figure2-6illustrates thetimingthatischaracteristic
|
||
ofadatainputoperation. Asshown,thelow-to-high transi
|
||
tionof<P2duringT2clearsstatusinformation fromthepro
|
||
cessor'sdatalines,preparing theselinesforthereceiptof
|
||
incoming data.Thedatapresented totheprocessor must
|
||
havestabilized priortoboththe"¢1-data set-up"interval
|
||
(tDS1),thatprecedes thefallingedgeofthe¢1pulsedefin
|
||
ingstateT3,andthe"¢2-dataset-up" interval (tDS2),
|
||
thatprecedes therisingedgeof<P2instateT3.Thissamedatamustremainstableduringthe"datahold"interval
|
||
(tDH)thatoccursfollowing therisingedgeofthe<P2pulse.
|
||
DataplacedontheseIinesbymemory orbyotherexternal
|
||
deviceswillbesampled duringT3.
|
||
Duringtheinputofdatatotheprocessor, the8080
|
||
generates aDBINsignalwhichshouldbeusedexternally to
|
||
enablethetransfer. Machine cyclesinwhichDBINisavail
|
||
ableinclude: FETCH, MEMORY READ,STACK READ,
|
||
andINTERRUPT. DBINisinitiated bytherisingedgeof¢2
|
||
duringstateT2andterminated bythecorresponding edgeof
|
||
<P2duringT3.AnyTWphasesintervening between T2and
|
||
T3willtherefore extend DBINbyoneormoreclock
|
||
periods.
|
||
Figure2-7showsthetimingofamachine cyclein
|
||
whichtheprocessor outputs data.Outputdatamaybedes
|
||
tinedeitherformemory orforperipherals. Therisingedge
|
||
of<P2withinstateT2clearsstatusinformation fromthe
|
||
CPU'sdatalines,andloadsinthedatawhichistobeoutput
|
||
toexternal devices. Thissubstitution takesplacewithinthe
|
||
4>1
|
||
A,S-O
|
||
SYNC
|
||
READY
|
||
WAIT
|
||
DBINT1 T2 Tw T3 T4 T6
|
||
n rr\nnrln
|
||
L.-J,f,f\IL
|
||
~UNKNOWN
|
||
---------_-..-®XL.....WRITEMODE FLOATING
|
||
-----~-----JFLOATING
|
||
I
|
||
DATA ~READMODE
|
||
STABLE
|
||
I
|
||
\
|
||
\
|
||
DATA
|
||
V
|
||
STATUS
|
||
INFORMATION
|
||
DATA
|
||
A,S·0 SAMPLE READY OPTIONAL FETCHDATA OPTIONAL
|
||
MEMORY ADDRESS HOLDANDHALT OR
|
||
OR HALTINSTRUCTIONINSTRUCTION
|
||
1/0DEVICE NUMBEROROREXECUTION
|
||
0-,,0 MEMORYWRITEDATAIFREQUIRED
|
||
STATUS INFORMATION ACCESSTIME
|
||
INTA OUT ADJUST
|
||
HLTA WO
|
||
MEMR M,
|
||
INP STACK
|
||
NOTE;®RefertoStatusWordChartonPage2-6.
|
||
Figure2-5.Basic8080Instruction Cycle
|
||
2-8
|
||
|
||
===PAGE 23===
|
||
~.....--..,.....--...,~-FLOATING
|
||
\._JBYTE
|
||
ONE411_n~---frr\~----Ifn~~n~~n,-- .........n-.--.......n,--~n~---.n~ .........n~----4
|
||
~_.J\._J\.J\.J\.L.IlLi\.~~l.-.l:1cd:J.
|
||
-~-- I\UNKNOWN BYTE X INPUTDATATO
|
||
TWO ACCUMULATOR---..-.-+--- ............--....---- - ,., ,.'~_~J ~__JA15·0....._.......
|
||
SYNC-WI I
|
||
DBIN \ L
|
||
READY"1"
|
||
WAIT"0"
|
||
WR"1"
|
||
STATUS
|
||
INFORMATION
|
||
NOTE:®RefertoStatusWordChartonPage2-6.
|
||
Figure2-6.InputInstruction Cycle
|
||
0]·0
|
||
SYNC
|
||
DBIN
|
||
READY
|
||
WAIT
|
||
STATUS
|
||
INFORMATIONM1 M2 ~ Ml
|
||
T1 T2 T3 T4 Tl T2 T3 Tl T2 T3 Tl
|
||
_rL-n_rL-rL-rL-rL-rL-rL-rL-rL-rL
|
||
_J\.JlJlJlJ\.LJl~JlJlJ\. .---J
|
||
I"\.
|
||
I ---IX'I/ODEVICE UNKNOWNBYTE BYTENUMBER
|
||
ONE TWO,,----- ~- , 1r~--X \..I--_JFLOATINGU__J ACCUMULATOR
|
||
-L-J
|
||
I I\
|
||
"1"
|
||
"0"
|
||
,---\
|
||
~0 ~0 1~0
|
||
NOTE:®RefertoStatusWordChartonPage2-6.
|
||
Figure2-7.OutputInstruction Cycle
|
||
2-9
|
||
|
||
===PAGE 24===
|
||
"dataoutputdelay"interval(tOO)following the</>2clock's
|
||
leadingedge.Dataonthebusremainsstablethroughout
|
||
theremainder ofthemachine cycle,untilreplaced byup
|
||
datedstatusinformation inthesubsequent T1state.Observe
|
||
thataREADY signalisnecessary forcompletion ofan
|
||
OUTPUT machine cycle.Unlesssuchanindication ispres
|
||
ent,theprocessor enterstheTWstate,following theT2
|
||
state.Dataontheoutputlinesremains stableinthe
|
||
interim,andtheprocessing cyclewillnotproceed until
|
||
theREADYlineagaingoeshigh.
|
||
The8080CPUgenerates aWRoutputforthesyn
|
||
chronization ofexternal transfers, duringthosemachine
|
||
cyclesinwhichtheprocessor outputsdata.Theseinclude
|
||
MEMORY WRITE, STACKWRITE, andOUTPUT. The
|
||
negative-going leadingedgeofWRisreferenced totherising
|
||
edgeofthefirst</>1clockpulsefollowing T2,andoccurs
|
||
withinabriefdelay(tDC)ofthatevent.WRremainslow
|
||
untilre-triggered bytheleadingedgeof</>1duringthe
|
||
statefollowing T3.NotethatanyTWstatesintervening
|
||
between T2andT3oftheoutputmachinecyclewillneces-sarilyextendWR,inmuchthesamewaythatDBrNisaf
|
||
fectedduringdatainputoperations.
|
||
Allprocessor machinecyclesconsistofatleastthree
|
||
states:T1,T2,andT3asjustdescribed. Iftheprocessor has
|
||
towaitforaresponse fromtheperipheral ormemorywith
|
||
whichitiscommunicating, thenthemachine cyclemay
|
||
alsocontainoneormoreTWstates.Duringthethreebasic
|
||
states,dataistransferred toorfromtheprocessor.
|
||
AftertheT3state,however, itbecomes difficultto
|
||
generalize. T4andTSstatesareavailable, iftheexecution
|
||
ofaparticular instruction requiresthem.Butnot·allmachine
|
||
cyclesmakeuseofthesestates.Itdepends uponthekindof
|
||
instruction beingexecuted, andontheparticular machine
|
||
cyclewithintheinstruction cycle.Theprocessor willtermi
|
||
nateanymachinecycleassoonasitsprocessing activities
|
||
arecompleted, ratherthanproceeding throughtheT4and
|
||
TSstateseverytime.Thusthe8080mayexitamachine
|
||
cyclefollowing theT3,theT41ortheTSstateandpro
|
||
ceeddirectlytotheT1stateofthenextmachinecycle.
|
||
STATE
|
||
TW
|
||
(optional)
|
||
T3
|
||
T4
|
||
TS
|
||
(optional)ASSOCIATED ACTIVITIES
|
||
Amemory addressorI/Odevicenumber is
|
||
placedontheAddress Bus(A15-0);status
|
||
information isplacedonDataBus(D7-0).
|
||
TheCPUsamplestheREADYandHOLDin
|
||
putsandchecksforhaltinstruction.
|
||
Processor enterswaitstateifREADY islow
|
||
orifHALTinstruction hasbeenexecuted.
|
||
Aninstruction byte(FETCH machine cycle),
|
||
databyte(MEMORY READ,STACKREAD)
|
||
orinterrupt instruction (INTERRUPT machine
|
||
cycle)isinputtotheCPUfromtheDataBus;
|
||
oradatabyte(MEMORY WRITE,STACK
|
||
WRITEorOUTPUT machinecycle)isoutput
|
||
ontothedatabus.
|
||
StatesT4andTSareavailable iftheexecu
|
||
tionofaparticular instruction requiresthem;
|
||
ifnot,theCPUmayskiponeorbothof
|
||
them.T4andTSareonlyusedforinternal
|
||
processor operations.
|
||
Table 2~2.StateDefinitions
|
||
2-10
|
||
|
||
===PAGE 25===
|
||
INTERRUPT SEQUENCES
|
||
The8080hasthebuilt-incapacity tohandleexternal
|
||
interrupt requests. Aperipheral devicecaninitiateaninter
|
||
ruptsimplybydrivingtheprocessor's interrupt (INT)line
|
||
high.
|
||
Theinterrupt (INT)inputisasynchronous, anda
|
||
request maytherefore originate atanytimeduringany
|
||
instruction cycle.Internal logicre-clocks theexternal re
|
||
quest,sothatapropercorrespondence withthedriving
|
||
clockisestablished. AsFigure2-8shows,aninterrupt
|
||
request (INT)arriving duringthetimethattheinterrupt
|
||
enableline(INTE)ishigh,actsincoincidence withthe~2
|
||
clocktosettheinternal interrupt latch.Thiseventtakes
|
||
placeduringthelaststateoftheinstruction cycleinwhich
|
||
therequest occurs,thusensuring thatanyinstruction in
|
||
progress iscompleted beforetheinterrupt canbeprocessed.
|
||
TheINTERRUPT machine cyclewhichfollowsthe
|
||
arrivalofanenabled interrupt requestresembles anordinary
|
||
FETCH machine cycleinmostrespects. TheM1statusbit
|
||
istransmitted asusualduringtheSYNCinterval. Itis
|
||
accompanied, however, byanINTAstatusbit(DO)which
|
||
acknowledges theexternal request. Thecontents ofthe
|
||
program counter arelatchedontotheCPU'saddress lines
|
||
duringT1,butthecounter itselfisnotincremented during
|
||
theINTERRUPT machine cycle,asitotherwise wouldbe.Inthisway,thepre-interrupt statusoftheprogram counter
|
||
ispreserved, sothatdatainthecounter mayberestored by
|
||
theinterrupted program aftertheinterrupt requesthasbeen
|
||
processed.
|
||
Theinterrupt cycleisotherwise indistinguishable from
|
||
anordinary FETCH machine cycle.Theprocessor itself
|
||
takesnofurtherspecialaction.Itistheresponsibility ofthe
|
||
peripheral logictoseethataneight-bit interrupt instruction
|
||
is"jammed" ontotheprocessor's databusduringstateT3.
|
||
Inatypicalsystem, thismeansthatthedata-inbusfrom
|
||
memory mustbetemporarily disconnected fromthepro
|
||
cessor's maindatabus,sothattheinterrupting devicecan
|
||
command themainbuswithout interference.
|
||
The8080'sinstruction setprovides aspecialone-byte
|
||
callwhichfacilitates theprocessing ofinterrupts (theordi
|
||
naryprogram Calltakesthreebytes).ThisistheRESTART
|
||
instruction (RST).Avariable three-bit fieldembedded in
|
||
theeight-bit fieldof.theRSTenablestheinterrupting device
|
||
todirectaCalltooneofeightfixedmemory locations. The
|
||
decimal addresses ofthesededicated locations are:0,8,16,
|
||
24,32,40,48,and56.Anyoftheseaddresses maybeused
|
||
tostorethefirstinstruction (s)ofaroutine designed to
|
||
servicetherequirements ofaninterrupting device.Since
|
||
the(RST)isacall,completion oftheinstruction also
|
||
storestheoldprogram counter contents ontheSTACK.
|
||
A1S-0
|
||
SYNC
|
||
DBIN
|
||
RETURN M1
|
||
(INTERNAL)
|
||
INTE
|
||
INT
|
||
INTF/F
|
||
(INTERNAL)
|
||
INHIBITSTOREOF
|
||
PC+1(INTERNAL)
|
||
STATUS
|
||
INFORMATIONM1 M2 M3
|
||
T3 T1 T2 T3 T4 Ts T1 T2 T3 T1 T2 T3
|
||
_nn r~rLrL-rL"-rLrL-rL-rLrL
|
||
_---r~U~ ~Ur--LLJl.LIl.J\.J\U\Wl.Lr\.Jl..Jl.--- ~-pc·, Ipc \ IsP·' XSP·2
|
||
----- ~-- 1--
|
||
Do\RST XPCHXXPCl
|
||
(INTA)
|
||
I \ I rM
|
||
\
|
||
'---' L-
|
||
-~\ ,-
|
||
I
|
||
~
|
||
I \
|
||
I \
|
||
0--- X\@ A\@
|
||
NOTE:®RefertoStatusWordChartonPage2-6.
|
||
Figure2-8.Interrupt Timing
|
||
2-11
|
||
|
||
===PAGE 26===
|
||
Mn Mn+1
|
||
l--OR~ I I
|
||
¢l_n ~n~n n~n
|
||
¢2-+--sLJJlL-..rrL~LJLLJTLJJ\.lJL
|
||
! i : II I
|
||
II!
|
||
A'5·0:I ! I-:-- - - - - - - - -:-- - - - - - - -
|
||
11 I FLOATING I
|
||
OJ·O ~ \ .1-I----------I---------- ......--~ 'i\. - --..III :
|
||
HOLDU ~ I 1REQUEST - (1)
|
||
i
|
||
HOLD.....1 '
|
||
READY
|
||
HOLDF/F
|
||
INTERNAL -+- --+- +--_J1
|
||
I
|
||
i
|
||
i
|
||
HLDAI
|
||
(1)SEEATTACHED ELECTRICAL CHARACTERISTICS.*T4ANDT5OPERATION CANBE
|
||
DONEINTERNALLY.
|
||
I I
|
||
Figure2-9.HOLDOperation (ReadMode)
|
||
A'5·0
|
||
HOLD
|
||
REQUEST
|
||
HOLD
|
||
READY
|
||
HOLDF/F
|
||
INTERNAL
|
||
HLDAMn Mn+1 Mn+2
|
||
T3 T4 T, T2 T3 T,
|
||
_V\nnnnnnn
|
||
-L.-ILL.-IL--F\...--F\...L.....JLL.-ILL.-ILL.-IL
|
||
I--------jXI
|
||
IFLOATING
|
||
I,-~--------XI--------y-
|
||
-~--~
|
||
I
|
||
-U\
|
||
II \
|
||
!
|
||
I
|
||
WRITEDATA
|
||
Figure2-10.HOLDOperation (WriteMode)
|
||
2-12
|
||
|
||
===PAGE 27===
|
||
HOLDSEQUENCES
|
||
TheSOSOACPUcontains provisions forDirectMem
|
||
oryAccess(DMA)operations. Byapplying aHOLDtothe
|
||
appropriate controlpinontheprocessor, anexternal device
|
||
cancausetheCPUtosuspend itsnormaloperations andre
|
||
linquish controloftheaddressanddatabusses.Theproces
|
||
sorresponds toarequestofthiskindbyfloating itsaddress
|
||
tootherdevicessharingthebusses.Atthesametime,the
|
||
processor acknowledges theHOLDbyplacingahighonits
|
||
HLDAoutpinpin.Duringanacknowledged HOLD,the
|
||
addressanddatabussesareundercontroloftheperipheral
|
||
whichoriginated therequest, enabling ittoconduct mem
|
||
orytransfers without processor intervention.
|
||
Liketheinterrupt, theHOLDinputissynchronized
|
||
internally. AHOLDsignalmustbestablepriortothe"Hold
|
||
set-up" interval (tHS),thatprecedes therisingedgeof<P2.
|
||
Figures2-9and2-10illustrate thetiminginvolved in
|
||
HOLDoperations. Notethedelaybetween theasynchronous
|
||
HOLDREQUEST andthere-clocked HOLD.Asshownin
|
||
thediagram, acoincidence oftheREADY, theHOLD,and
|
||
the¢2clockssetstheinternal holdlatch.Settingthelatch
|
||
enablesthesubsequent risingedgeofthe¢1clockpulseto
|
||
triggertheHLOAoutput.
|
||
Acknowledgement oftheHOLDREQUEST precedes
|
||
slightlytheactualfloating oftheprocessor's address and
|
||
datalines.Theprocessor acknowledges aHOLDatthebegin
|
||
ningofT3,ifareadoraninputmachine cycleisinprogress
|
||
(seeFigure2-9).Otherwise, acknowledgement isdeferred
|
||
untilthebeginning ofthestatefollowing T3(seeFigure
|
||
2-10).Inbothcases,however, theHLDAgoeshighwithin
|
||
aspecified delay(tDC)oftherisingedgeoftheselected ¢1
|
||
clockpulse.Address anddatalinesarefloatedwithina
|
||
briefdelayaftertherisingedgeofthenext¢2clockpulse.
|
||
Thisrelationship isalsoshowninthediagrams.
|
||
Toalloutward appearances, theprocessor hassuspend
|
||
editsoperations oncetheaddressanddatabussesarefloated.
|
||
Internally, however, certainfunctions maycontinue. Ifa
|
||
HOLDREQUEST isacknowledged atT3,andifthepro
|
||
cessorisinthemiddleofamachine cyclewhichrequires
|
||
fourormorestatestocomplete, theCPUproceeds through
|
||
T4andT5beforecomingtoarest.Notuntiltheendofthe
|
||
machine cycleisreached willprocessing activities cease.
|
||
Internal processing isthuspermitted tooverlaptheexternal
|
||
DMAtransfer, improving boththeefficiency andthespeed
|
||
oftheentiresystem.
|
||
Theprocessor exitstheholding statethrough a
|
||
sequence similartothatbywhichitentered. AHOLD
|
||
REQUEST isterminated asynchronously whentheexternal
|
||
devicehascompleted itsdatatransfer. TheHLOAoutputreturnstoalowlevelfollowing theleadingedgeofthenext
|
||
¢1clockpulse.Normal processing resumes withthema
|
||
chinecyclefollowing thelastcyclethatwasexecuted.
|
||
HALTSEQUENCES
|
||
Whenahaltinstruction (HLT)isexecuted, theCPU
|
||
entersthehaItstate(TWH)afterstateT2ofthenextma
|
||
chinecycle,asshowninFigure2-11.Thereareonlythree
|
||
waysinwhichthe8080canexitthehaltstate:
|
||
• AhighontheRESET linewillalwaysresetthe
|
||
8080tostateT1;RESETalsoclearstheprogram
|
||
counter.
|
||
• AHOLDinputwillcausethe8080toenterthe
|
||
holdstate,aspreviously described. Whenthe
|
||
HOLDlinegoeslow,the8080re-enters thehalt
|
||
stateontherisingedgeofthenext¢1clock
|
||
pulse.
|
||
•Aninterrupt (Le.,INTgoeshighwhileINTEis
|
||
enabled) willcausethe8080toexittheHaltstate
|
||
andenterstateT1ontherisingedgeofthenext
|
||
¢1clockpulse.NOTE:Theinterrupt enable(INTE)
|
||
flagmustbesetwhenthehaltstateisentered;
|
||
otherwise, the8080willonlybeabletoexitviaa
|
||
RESETsignal.
|
||
Figure2-12illustrates haltsequencing inflowchart
|
||
form.
|
||
START-UP OFTHE8080CPU
|
||
Whenpowerisapplied initiallytothe8080,thepro
|
||
cessorbeginsoperating immediately. Thecontents ofits
|
||
program counter, stackpointer, andtheotherworking regis
|
||
tersarenaturally subjecttorandom factorsandcannotbe
|
||
specified. Forthisreason,itwillbenecessary tobeginthe
|
||
power-up sequence withRESET.
|
||
Anexternal RESETsignalofthreeclockperioddura
|
||
tion(minimum) restores theprocessor's internal program
|
||
countertozero.Program execution thusbeginswithmem
|
||
orylocation zero,following aRESET. Systems whichre
|
||
quiretheprocessor towaitforanexplicit start-up signal
|
||
willstoreahaltinstruction (EI,HLT)inthefirsttwoloca
|
||
tions.Amanualoranautomatic INTERRUPT willbeused
|
||
forstarting. Inothersystems, theprocessor maybeginex
|
||
ecutingitsstoredprogram immediately. Note,however, that
|
||
theRESET hasnoeffectonstatusflags,oronanyofthe
|
||
processor's working registers (accumulator, registers, or
|
||
stackpointer). Thecontents oftheseregisters remaininde
|
||
terminate, untilinitialized explicitly bytheprogram.
|
||
2-13
|
||
|
||
===PAGE 28===
|
||
TWH TWH
|
||
,...-+---- - - - - - -Tl
|
||
~--..-----~-- ----- -T,
|
||
91
|
||
92
|
||
A1S·0 PC
|
||
07-0
|
||
SYNC
|
||
OBIN
|
||
WAIT
|
||
STATUS
|
||
INFORMATION
|
||
NOTE:®RefertoStatusWordChartonPage2-6
|
||
Figure2-11.HALTTiming
|
||
TOSTATE NO
|
||
TWorT3
|
||
TOSTATE YES
|
||
Tl
|
||
TOSTATETl
|
||
Figure2-12.HALTSequence FlowChart.
|
||
2-14
|
||
|
||
===PAGE 29===
|
||
Tn+i Tn+(i-1) Tn+3 Tn+2 Tn+1
|
||
~~~~t==p----~--·_-~---
|
||
,--~~-----+-----""'----"'~-+---"""Tn
|
||
(1)cP1
|
||
A15.0~__.1
|
||
RESET
|
||
INTERNAL
|
||
RESET
|
||
SYNC-+- ..... ..... -+- -/~-----~---- ....-_....I
|
||
DBIN-+----- .....----- .....----....-----/~-----~---- ....-----I---.....I
|
||
STATUS
|
||
INFORMATION(0
|
||
I I
|
||
11lWHEN RESETSIGNAL ISACTIVE, ALLOFCONTROL OUTPUT SIGNALS WILLBERESETIMMEDIATELY ORSOME
|
||
CLOCKPERIODS LATER. THERESETSIGNAL MUSTBEACTIVE FORAMINIMUM OFTHREECLOCKCYCLES. IN
|
||
THEABOVEDIAGRAM NANDIMAYBEANYINTEGER.
|
||
NOTE:®RefertoStatusWordChartonPage2·6.
|
||
Figure2-13.Reset.
|
||
~.O
|
||
SYNC
|
||
DBIN
|
||
HOLD
|
||
HOLDF/F
|
||
(INTERNAL)
|
||
HLDA
|
||
INTE
|
||
INT
|
||
INTF/F
|
||
(INTERNAL)
|
||
STATUS
|
||
INFORMATIONM1
|
||
TWH TWH TWH TWH TWH TWH TWH T1 T2 T3
|
||
.rL-rL-rL-..rL..-r\l.-r\l.-~~~rL..-
|
||
_J\.-fn.--.Jl.J\.._JrL...J\.JrLJL--.Jl.-JTl-----------------~-"--IJ l-FLO
|
||
FLOATING I----"1-_...-------'----:--~------~----\...~ST_J1
|
||
I
|
||
I\I
|
||
IL
|
||
II \ I
|
||
/'~J\; \' I
|
||
II \ I,
|
||
I INHIBIT INHIBIT \
|
||
INT HOLD
|
||
,),\
|
||
0 K@
|
||
IATING
|
||
NOTE:®RefertoStatusWordChartonPage2·6.
|
||
Figure2-14.Relation between HOLDand'INT intheHALTState.
|
||
2-15
|
||
|
||
===PAGE 30===
|
||
MNEMONIC OPCODE M1[1] M2
|
||
oS S ST3 T5
|
||
xX[3]
|
||
x
|
||
OAA-A, FLAGS[10]xT4
|
||
x
|
||
xxx
|
||
x(RP)-1 ~.(RP)+1 ~~x
|
||
x(OOO)-TMP
|
||
(TMP)+l-ALUx
|
||
(SSS)-TMP
|
||
(A)-ACTx
|
||
(OOOJ-TMP
|
||
(TMP)+1-ALU(SSS)-TMP
|
||
(A)-ACT(A)-ACT(SSS)-TMP
|
||
(A)-ACT(SSS)-TMP
|
||
(A)-ACT(SSS)-TMP
|
||
(A)-ACT(SSS)-TMP
|
||
(HL) ~(SSS)-TMPT3
|
||
PC==PC+1INST-TMP/IR
|
||
PCOUT PC==PC+1 INST-TMP/lR
|
||
STATUST1
|
||
PCOUT
|
||
STATUS
|
||
oooo
|
||
oooo
|
||
oooo
|
||
oS
|
||
o
|
||
o01 0
|
||
S S Soo001
|
||
oo1 1
|
||
o1 0 01 S S S
|
||
o1 0
|
||
o1 0 1o1
|
||
o0
|
||
o1 11 0
|
||
1 0 0 1
|
||
oS S S1 1 1 0
|
||
oS S Soo1 1 0
|
||
o11 01 0
|
||
o0
|
||
oS S So0ooS
|
||
o
|
||
001 0o
|
||
000
|
||
oo
|
||
oo0o0
|
||
oo0 R Po0 R Poo01 0o0000o0000o1 1 1
|
||
000
|
||
000
|
||
1 0 1 0o0 1 0o0 R Po01 0 0
|
||
o00 0001o00 01001 1 0 0o0 R Po0 R Po0 1 1
|
||
o0o0 1o00 0
|
||
o0o0 R P
|
||
o0o1oo
|
||
INRM
|
||
OCRr
|
||
OCRM
|
||
INXrp
|
||
OAOrp[S]
|
||
OAA
|
||
ANArLHLOaddr
|
||
ACIdata
|
||
SBBr
|
||
SBBM
|
||
DCXrpLOAXrp[4]LOAaddr
|
||
AOOM
|
||
AOIdata
|
||
AOCr
|
||
AOCM
|
||
SUBr
|
||
SUBM
|
||
SUIdata
|
||
ANAMSBIdata
|
||
INRrAOOrSTAaddr
|
||
STAXrp[4]LXIrp,data
|
||
SHLOaddrMVIM,data
|
||
XCHGMVIr.,dataMOVM,rMOVr1,r2
|
||
MOVr,M
|
||
SPHL
|
||
2-16
|
||
|
||
===PAGE 31===
|
||
PCOUT
|
||
STATUS[6]
|
||
[9]
|
||
[9]
|
||
[9]M3
|
||
PC=PC+1
|
||
PC=PC+1
|
||
PC=PC+1
|
||
PC=PC+1M4
|
||
2-17M5
|
||
|
||
===PAGE 32===
|
||
MNEMONIC OPCODE Ml[l] M2
|
||
07060504030201DO Tl T2[2] T3 T4 T1 T2[2] T3
|
||
ANIdata 1 11001 10PCOUT PC=PC+ 1INST-TMP/IA (A)-ACT PC=PC+ 1
|
||
STATUS
|
||
XAAr 1010 S S S (A)-ACT (ACT)+(TPM)-A
|
||
(SSS)-TMP
|
||
XRAM 010110 (A)-ACT
|
||
XRIdata 10 10 (A)-ACT PC=PC+ 1
|
||
ORAr 01 1 0SS S (A)-ACT (ACT)+(TMP)-A
|
||
(SSS)-TMP
|
||
ORAM 101 1 01 10 (A)-ACT
|
||
ORIdata 010 (A)-ACT PC=PC+ 1
|
||
CMPr 01 1 S S S (A)-ACT
|
||
(SSS)-TMP
|
||
CMPM 101 1 1 110 (A)-ACT
|
||
CPIdata 11 110 (A)-ACT PC=PC+ 1
|
||
RLC 0 0 0 0 0 (A)-ALU ALU-A, CY
|
||
ROTATE
|
||
RRC 0 0 0 0 1111 (A)-ALU ALU-+A, CY
|
||
ROTATE
|
||
RAL 000 0 (A),CY-ALU ALU-+A, CY
|
||
ROTATE
|
||
AAA 0 0 0 1 11 (A),CY-ALU ALU-+A, CY
|
||
ROTATE
|
||
CMA 0 0 0 11 (A)-A
|
||
CMC 00 11 cy-CY
|
||
STC 0 01 01 l-CY
|
||
JMPaddr 1 100 0 0 X
|
||
Jcondaddr[17] CC C 0 0 PC=PC+ 1
|
||
CALLaddr 00 01 SP=SP-1 PC=PC+ 1
|
||
Ccondaddr[17] 11CC C 0 0 PC=PC+ 1
|
||
RET 00 0 0 X SP=SP+ 1
|
||
Rcondaddr[17] C C C00 0 INST-TMP/IA SP=SP+1
|
||
RSTn 11 N N N 11 q,-+W SP=SP-1 Sp;:SP- 1
|
||
INST-TMP/IR
|
||
PCHL 0 0 0 INST-TMP/IR (HL)
|
||
PUSHrp 1 1A P 0101 SP=SP-1
|
||
PUSHPSW 010 Sp;:SP-1 Sp::SP- 1
|
||
POPrp RP00 0 X Sp;:SP+ 1
|
||
POPPSW 00 0 X Sp;:SP+ 1
|
||
XTHL 11100011 X SP;:SP+1
|
||
INport 110 10 X PC::PC+1
|
||
OUTport 0 00 X PC::PC+1
|
||
EI 10 SETINTEF/F
|
||
01 11110 01 RESETINTEF/F
|
||
HLT 0 0 0 X
|
||
NOP 000000 00PCOUT PC::PC+ 1INST-TMP/IA X
|
||
STATUS
|
||
2-18
|
||
|
||
===PAGE 33===
|
||
M3 M4 M5
|
||
SPOUT SP::SP+ 1
|
||
STATUS[15]SPOUT SP::SP+ 1
|
||
STATUS[15](ACT)+(TMP)-AT1
|
||
WZOUT (WZ)+1-PC
|
||
STATUS[ll]
|
||
PCOUT PC::PC+ 1
|
||
~iA~~[ll,12](WZ)+1-PC
|
||
STATUS[6]
|
||
PCOUT PC::PC+ 1
|
||
~iA~~~[11](WZ)+1-PC
|
||
STATUS[6]
|
||
~~~TUJS[6]PC::PC+ 1
|
||
~iA~~~[11,12](WZ) +1-PC
|
||
~~2~JS[15]Sp::SP+ 1
|
||
~A~~~[ll](WZ)+l-PC
|
||
SPOUT Sp::SP+ 1
|
||
~A~~1[11,12](WZ) +1-PC
|
||
STATUS[15]
|
||
~iA~~~[11](WZ)+1-PC
|
||
STATUS[18]SPOUT
|
||
STATUS[15]
|
||
WZOUT[9[9]
|
||
2-19
|
||
|
||
===PAGE 34===
|
||
NOTES:
|
||
1.Thefirstmemory cycle(M1)isalwaysaninstruction
|
||
fetch;thefirst(oronly)byte,containing theopcode,is
|
||
fetchedduringthiscycle.
|
||
2.IftheREADY inputfrommemory isnothighduring
|
||
T2ofeachmemory cycle,theprocessor willenterawait
|
||
state(TW)untilREADY issampled ashigh.
|
||
3.StatesT4andT5arepresent,asrequired, foropera
|
||
tionswhicharecompletely internaltotheCPU.Thecon
|
||
tentsoftheinternalbusduringT4andT5areavailable at
|
||
thedatabus;thisisdesigned fortestingpurposes only.An
|
||
"X"denotesthatthestateispresent,butisonlyusedfor
|
||
suchinternaloperations asinstruction decoding.
|
||
4.Onlyregisterpairsrp=B(registers BandC)orrp=D
|
||
(registers DandE)maybespecified.
|
||
5.Thesestatesareskipped.
|
||
6.Memory readsub-cycles; aninstruction ordataword
|
||
willberead.
|
||
7.Memory writesub-cycle.
|
||
8.TheREADY signalisnotrequired duringthesecond
|
||
andthirdsub-cycles (M2andM3).TheHOLDsignalis
|
||
accepted duringM2andM3.TheSYNCsignalisnotgene
|
||
ratedduringM2andM3.Duringtheexecution ofDAD,
|
||
M2andM3arerequired foraninternalregister-pair add;
|
||
memory isnotreferenced.
|
||
9.Theresultsofthesearithmetic, logicalorrotatein
|
||
structions arenotmovedintotheaccumulator (A)until
|
||
stateT2ofthenextinstruction cycle.Thatis,Aisloaded
|
||
whilethenextinstruction isbeingfetched; thisoverlapping
|
||
ofoperations allowsforfasterprocessing.
|
||
10.Ifthevalueoftheleastsignificant 4-bitsoftheaccumu
|
||
latorisgreaterthan9oriftheauxjliary carrybitisset,6
|
||
isaddedtotheaccumulator. Ifthevalueofthemostsignifi
|
||
cant4-bitsoftheaccumulator isnowgreaterthan9,~if
|
||
thecarrybitisset,6isaddedtothemostsignificant
|
||
4-bitsoftheaccumulator.
|
||
11.Thisrepresents thefirstsub-cycle (theinstruction
|
||
fetch)ofthenextinstruction cycle.
|
||
2-2012.Ifthecondition wasmet,thecontents oftheregister
|
||
pairWZareoutputontheaddresslines(Ao-1S)insteadof
|
||
thecontents oftheprogram counter (PC).
|
||
13.Ifthecondition wasnotmet,sub-cycles M4andM5
|
||
areskipped; theprocessor insteadproceeds immediately to
|
||
theinstruction fetch(Ml)ofthenextinstruction cycle.
|
||
14.Ifthecondition wasnotmet,sub-cycles M2andM3
|
||
areskipped; theprocessor insteadproceeds immediately to
|
||
theinstruction fetch(M1)ofthenextinstruction cycle.
|
||
15.Stackreadsub-cycle.
|
||
16.Stackwritesub-cycle.
|
||
17.CONDITION CCC
|
||
NZ-notzero(Z=0) 000
|
||
Z -zero(Z=1) 001
|
||
NC-nocarry(CY=0) 010
|
||
C -carry(CY=1) 011
|
||
POparityodd(P=O) 100
|
||
PEparityeven(P=1) 101
|
||
Pplus(S=0) 110
|
||
Mminus(S=1) 111
|
||
18.I/Osub-cycle: theI/Oport's8-bitselectcodeisdupli
|
||
catedonaddresslines0-7(Ao-7)and8-15(AS-1S).
|
||
19.Outputsub-cycle.
|
||
20.Theprocessor willremainidleinthehaltstateuntil
|
||
aninterrupt, aresetoraholdisaccepted. Whenaholdre
|
||
questisaccepted, theCPUenterstheholdmode;afterthe
|
||
holdmodeisterminated, theprocessor returnstothehalt
|
||
state.Afteraresetisaccepted, theprocessor beginsexecu
|
||
tionatmemory location zero.Afteraninterrupt isaccepted,
|
||
theprocessor executes theinstruction forcedontothedata
|
||
bus(usuallyarestartinstruction).
|
||
SSSorDDD Value rp Value
|
||
A 111 B 00
|
||
B 000 D 01
|
||
C 001 H 10
|
||
D 010 SP 11
|
||
E 011
|
||
H 100
|
||
L 101
|
||
|
||
===PAGE 35===
|
||
Thischapterwillillustrate, indetail,howtointerface
|
||
the8080CPUwithMemory andI/O.Itwillalsoshowthe
|
||
benefits andtradeoffs encountered whenusingavarietyof
|
||
system architectures toachieve higherthroughput, de
|
||
creasedcomponent countorminimization ofmemory size.
|
||
8080Microcomputer systemdesignlendsitselftoa
|
||
simple,modular approach. Suchanapproach willyieldthe
|
||
designer areliable, highperformance systemthatcontains a
|
||
minimum component countandiseasytomanufacture and
|
||
maintain.ControlBusAuni-directional setofsignalsthatindicate
|
||
thetypeofactivityincurrentprocess.
|
||
Typeofactivities: 1.Memory Read
|
||
2.Memory Write
|
||
3.I/ORead
|
||
4.I/OWrite
|
||
5.Interrupt Acknowledge
|
||
CPUModule* Contains theCentralProcessing Unit,system
|
||
timingandinterface circuitry toMemory
|
||
andI/Odevices.Theoverallsystemcanbethought ofasasimple
|
||
blockdiagram. Thethree(3)blocksinthediagram repre
|
||
sentthefunctions common toanycomputer system.
|
||
*"Module" referstoafunctional block,itdoesnotref
|
||
erenceaprintedcircuitboardmanufactured byINTEL.
|
||
t"Bus" referstoasetofsignalsgrouped together because
|
||
ofthesimilarity oftheirfunctions.CPU
|
||
MODULE
|
||
Figure3-1.TypicalComputer SystemBlockDiagram
|
||
BasicSystemOperation
|
||
1.TheCPUModule issuesanactivitycommand onthe
|
||
Control Bus.
|
||
2.TheCPUModule issuesabinarycodeontheAddress
|
||
Bustoidentify whichparticular Memory location or
|
||
I/Odevicewillbeinvolved inthecurrent process
|
||
activity.
|
||
3.TheCPUModule receivesortransmits datawiththe
|
||
selected Memory location orI/Odevice.
|
||
4.TheCPUModulereturnstoCDandissuesthenext
|
||
activitycommand.
|
||
ItiseasytoseeatthispointthattheCPUmoduleis
|
||
thecentralelement inanycomputer system.Contains ReadOnlyMemory (ROM)and
|
||
Read/Write Memory (RAM)forprogram and
|
||
datastorage.
|
||
Con"tains circuitry thatallowsthecomputer
|
||
systemtocommunicate withdevices or
|
||
structures existing outsideoftheCPUor
|
||
Memory array.
|
||
forexample: Keyboards, Floppy Disks,
|
||
PaperTape,etc.I/OMemory
|
||
Therearethreebussesthatinterconnect theseblocks:
|
||
DataBust Abi-directional pathonwhichdatacanflow
|
||
between theCPUandMemory orI/O.
|
||
Address BusAuni-directional groupoflinesthatidentify
|
||
aparticular Memory location orI/Odevice.
|
||
3-1
|
||
|
||
===PAGE 36===
|
||
Thefollowing pageswillcoverthedetailed designof
|
||
theCPUModule withthe8080.ThethreeBusses(Data,
|
||
Address andControl) willbedeveloped andtheintercon
|
||
nectiontoMemory andI/Owillbeshown.
|
||
Designphilosophies andsystemarchitectures pre
|
||
sentedinthismanualareconsistent withproduct develop-
|
||
l"Mmentprograms underway atINTELfortheMCS-80. Thus,
|
||
thedesigner whousesthismanualasaguideforhistotal
|
||
systemengineering isassuredthatallnewdevelopments in
|
||
components andsoftware forMCS-80 fromINTELwillbe
|
||
compatible withhisdesignapproach.thedesignandtoachieveoperational characteristics that
|
||
areascloseaspossible tothoseofthe8224and8228.
|
||
Manyauxiliary timingfunctions andfeatures ofthe8224
|
||
and8228aretoocomplex topractically implement in
|
||
standard components, soonlythebasicfunctions ofthe
|
||
8224and8228aregenerated. Sincesignificant benefits in
|
||
systemtimingandcomponent countreduction canbe
|
||
realized byusingthe8224and8228,thisisthepreferred
|
||
methodofimplementation.
|
||
1.8080CPU
|
||
CPUModuleDesign
|
||
TheCPUModulecontains threemajorareas:
|
||
1.The8080CentralProcessing Unit
|
||
2.AClockGenerator andHighLevelDriver
|
||
3.Abi-directional DataBusDriverandSystemControl
|
||
Logic
|
||
Thefollowing willdiscussthedesignofthethree
|
||
majorareascontained intheCPUModule. Thisdesignis
|
||
presented asanalternative totheIntel®8224ClockGener
|
||
atorandIntel8228System Controller. Bystudying the
|
||
alternative approach, thedesigner canmoreclearlyseethe
|
||
considerations involved inthespecification andengineering
|
||
ofthe8224and8228.Standard TTLcomponents andIntel
|
||
generalpurpose peripheral devicesareusedtoimplement2.Theoperation ofthe8080CPUwascovered inpre
|
||
viouschapters ofthismanual, solittlereference will
|
||
bemadetoitinthedesignoftheModule.
|
||
ClockGenerator andHighLevelDriver
|
||
The8080isadynamic device,meaning thatitsinter
|
||
nalstorage elements andlogiccircuitry requirea
|
||
timingreference (Clock), supplied byexternal cir
|
||
cuitry,torefreshandprovidetimingcontrolsignals.
|
||
The8080requires two(2)suchClocks.Theirwave
|
||
formsmustbenon-overlapping, andcomplywiththe
|
||
timingandlevelsspecified inthe8080A.C.andD.C.
|
||
Characteristics, page5-15.
|
||
ClockGenerator Design
|
||
TheClockGenerator consistsofacrystalcontrolled,
|
||
2 25GND AO AO
|
||
+5V20 26Al Al
|
||
11 27-5V A2 A2
|
||
+12V28A329
|
||
30A3
|
||
A4 A4
|
||
AS31AS
|
||
A632A6808033CPU A7 A7
|
||
A834A8ADDRESS BUS
|
||
13 35SYSTEM DMAREO. HOLD A9 A9
|
||
Al01Al0
|
||
All40All
|
||
14A1237A12 SYSTEM INT.REO. tNT
|
||
A1338~13
|
||
INT.ENABLE16INTE A1439A14
|
||
A1536A15
|
||
WR18
|
||
XTAL 170DBIN
|
||
HLDA21
|
||
22 10
|
||
ct>1 DO
|
||
15 9
|
||
eJ>2 01
|
||
028
|
||
CLOCK24WAIT 037BI-DIREC-
|
||
WAITREO. GENERATOR 23 3 TIONAL DATABUS
|
||
DRIVERREADY 04BUSDRIVER412 05
|
||
SYS.RESET RESET 506
|
||
19076
|
||
SYNC
|
||
1STATUS STROBE SYSTEM
|
||
CONTROL
|
||
Figure3-2.8080CPUInterface
|
||
3-2
|
||
|
||
===PAGE 37===
|
||
OSCILLATOR
|
||
CLOCKGENERATOR
|
||
7486
|
||
DB OB
|
||
74163
|
||
DC OC.......--...-------'74S04~20MHz
|
||
330 330
|
||
~""""--01 >-......------------ .......-------- ....OSC
|
||
7486
|
||
READYr-----IIIIII---- SYNCAUXILIARY FUNCTIONS
|
||
WAITREO------41---1 0a
|
||
74574
|
||
ClK'----........--410
|
||
74S74
|
||
ClK0.......-..-.-----.. tf>1A(TTL)74HOO10--+--------- ..4>2(TTL)
|
||
WAVEFORMSGND--+-~
|
||
4>1----u u
|
||
---f1~~~ ~50ns
|
||
4>2--' \250ns , '~__-Ir-
|
||
50ns~t+---.fr-50ns
|
||
4>1A---I ,250ns, ,I
|
||
SYNC ---1'
|
||
,\,.-_---1'\DMAREO--~----IID a
|
||
74S74
|
||
ClKHOLD
|
||
Figure3-3.8080ClockGenerator
|
||
20MHZoscillator, afourbitcounter, andgating
|
||
circuits.
|
||
Theoscillator provides a20MHZsignaltotheinput
|
||
ofafour(4)bit,presettable, synchronous, binary
|
||
counter. Bypresetting thecounter asshowninfigure
|
||
3-3andclocking itwiththe20MHZsignal,asimple
|
||
decoding ofthecounters outputs usingstandard TTL
|
||
gates,provides propertimingforthetwo(2)8080
|
||
clockinputs.
|
||
Notethatthetimingmustactually bemeasured at
|
||
theoutputoftheHighLevelDrivertotakeintoac
|
||
counttheaddeddelaysandwaveform distortions
|
||
withinsuchadevice.positive transition whenbiasedfromthe8080Voo
|
||
supply(12V)buttoachievethelowvoltagespecifi
|
||
cation(VILC).8voltsMax.thedriverisbiasedtothe
|
||
8080Vsssupply(-5V).Thisallowsthedriverto
|
||
swingfromGNDtoVoowiththeaidofasimple
|
||
resistordivider.
|
||
Alowresistance seriesnetwork isaddedbetween the
|
||
driverandthe8080toeliminate anyovershoot ofthe
|
||
pulsedwaveforms. Nowacircuitisapparent thatcan
|
||
easilycomply withthe8080specifications. Infact
|
||
riseandfalltimes ofthisdesignaretypically lessthan
|
||
10ns.
|
||
Figure3-4.HighLevelDriver100n
|
||
-5V.68J.LF+12V
|
||
6
|
||
6S0pF 47n
|
||
cf>1
|
||
cf>1(TTL)---1 2
|
||
MH0026 (SOSOPIN22)
|
||
680pFOR
|
||
¢2(TTL)-) 4EQUIV. 547n¢2
|
||
(8080PIN15)
|
||
3
|
||
15K 15KHighLevelDriverDesign
|
||
Thevoltageleveloftheclocksforthe8080isnot
|
||
TTLcompatible liketheothersignalsthatinputto
|
||
the8080.Thevoltageswingisfrom.6volts(VILC)
|
||
to11volts(VIHC)withrisetimes andfalltimes under
|
||
50ns.TheCapacitive Driveis20pf(max.).Thus,a
|
||
HighLevelDriverisrequired tointerface theoutputs
|
||
oftheClockGenerator (TTL)tothe8080.
|
||
Thetwo(2)outputs oftheClockGenerator areca
|
||
pacitivity coupled toadual-HighLevelclockdriver.
|
||
Thedrivermustbecapable ofcomplying withthe
|
||
8080clockinputspecifications, page5-15.Adriver
|
||
ofthistypeusuallyhaslittleproblem supplying the
|
||
3-3
|
||
|
||
===PAGE 38===
|
||
Auxiliary TimingSignalsandFunctions
|
||
TheClockGenerator canalsobeusedtoprovide
|
||
othersignalsthatthedesigner canusetosimplify
|
||
largesystem timingortheinterface todynamic
|
||
memories.
|
||
Functions suchaspower-on reset,synchronization of
|
||
external requests (HOLD, READY, etc.)andsingle
|
||
step,couldeasilybeaddedtotheClockGenerator to
|
||
furtherenhance itscapabilities.
|
||
Forinstance, the20MHZsignalfromtheoscillator
|
||
canbebuffered sothatitcouldprovidethebasisfor
|
||
communication baudrategeneration.
|
||
TheClockGenerator diagram alsoshowshowtogen
|
||
erateanadvanced timingsignal(l/>1A)thatishandy
|
||
touseinclocking"0"typeflipflops tosynchronize
|
||
external requests. Itcanalsobeusedtogenerate a
|
||
strobe(STSTB) thatisthelatching signalforthesta
|
||
tusinformation whichisavailable ontheDataBusat
|
||
thebeginning ofeachmachine cycle.Asimplegating
|
||
oftheSYNCsignalfromthe8080andtheadvanced
|
||
(l/>1A)willdothejob.SeeFigure3-3.3.Bi-Directional BusDriverandSystemControl Logic
|
||
ThesystemMemory andI/Odevicescommunicate
|
||
withtheCPUoverthebi-directional DataBus.The
|
||
systemControl Busisusedtogatedataonandoff
|
||
theDataBuswithinthepropertimingsequences as
|
||
dictated bytheoperation ofthe8080CPU.Thedata
|
||
linesofthe8080CPU,Memory andI/Odevicesare
|
||
3-state innature,thatis,theiroutputdrivershave
|
||
theabilitytobeforcedintoahigh-impedance mode
|
||
andare,effectively, removed fromthecircuit.This'3
|
||
statebustechnique allowsthedesignertoconstruct a
|
||
systemaroundasingle,eight(8)bitparallel, bi-direc
|
||
tionalDataBusandsimplygatetheinformation on
|
||
oroffthisbusbyselecting ordeselecting (3-stating)
|
||
Memory andI/OdeviceswithsignalsfromtheCon
|
||
trolBus.
|
||
Bi-Directional DataBusDriverDesign
|
||
The8080DataBus(07-00) hastwo(2)majorareas
|
||
ofconcern forthedesigner:
|
||
1.InputVoltagelevel(V1H)3.3voltsminimum.
|
||
2.OutputDriveCapability (tOL)1.7rnAmaximum.
|
||
OBO
|
||
OB1
|
||
OB2
|
||
OB3
|
||
OB4
|
||
DB5
|
||
DB6
|
||
DB7BUSEN-
|
||
DO2,4r- 3
|
||
015,7r- 6
|
||
9,11r- 8216 1002
|
||
0312,14r- 13
|
||
OlENCS
|
||
15?«1
|
||
042,4] 3
|
||
055,7r- 6
|
||
9,11r- 8216 1006
|
||
0712,14r- 13
|
||
OlENCS
|
||
OBIN ~I15)' ?1...,
|
||
3 4INTAQ.»--I....--
|
||
5 6WO- -
|
||
07 8STACK-9821210HLTA-16 15OUT
|
||
~Q.»--18 17M1-20 191NP
|
||
22 21MEMRc=[y--
|
||
------!112[13
|
||
STSTB Vee
|
||
-
|
||
WR...... 1 I
|
||
...... ----(>0.-=0--808
|
||
Figure3-5.8080SystemControl
|
||
3-4
|
||
|
||
===PAGE 39===
|
||
Theinputlevelspecification impliesthatanysemi
|
||
conductor memory orI/Odeviceconnected tothe
|
||
8080DataBusmustbeabletoprovideaminimum of
|
||
3.3voltsinitshighstate.Mostsemiconductor mem
|
||
oriesandstandard TTLI/Odeviceshaveanoutput
|
||
capability ofbetween 2.0and2.8volts,obviously a
|
||
directconnection ontothe8080DataBuswouldre
|
||
quirepullupresistors, whosevalueshouldnotaffect
|
||
thebusspeedorstressthedrivecapability ofthe
|
||
memory orI/Ocomponents.
|
||
The80S0Aoutputdrivecapability (lOl)1.9mAmax.
|
||
issufficient forsmallsystems whereMemory sizeand
|
||
I/Orequirements areminimal andtheentiresystemis
|
||
contained onasingleprintedcircuitboard.Mostsys
|
||
temshowever, takeadvantage ofthehigh-perfor
|
||
mancecomputing powerofthe8080CPUandthusa
|
||
moretypicalsystemwouldrequiresomeformofbuf
|
||
feringonthe80S0DataBustosupportalargerarray
|
||
ofMemory andI/Odeviceswhicharelikelytobeon
|
||
separate boards.
|
||
Adevicespecifically designed todothisbuffering
|
||
function istheINTEL®8216,a(4)fourbitbi-direc
|
||
tionalbusdriverwhoseinputvoltageleveliscompat
|
||
iblewithstandard TTLdevicesandsemiconductor
|
||
memory components, andhasoutputdrivecapability
|
||
of50mAoAtthe8080side,the8216hasa"high"
|
||
outputof3.65voltsthatnotonlymeetstheS080
|
||
inputspecbutprovides thedesigner withaworsecase
|
||
350mVnoisemargin.
|
||
ApairofS216'sareconnected directlytothe8080
|
||
DataBus(07-00) asshowninfigure3-5.Notethat
|
||
theOBINsignalfromthe8080isconnected tothe
|
||
direction controlinput(01EN)sothecorrectflowof
|
||
dataonthebusismaintained. Thechipselect(CS)of
|
||
theS216isconnected toBUSENABLE (BUSEN) to
|
||
allowforDMAactivities bydeselecting theDataBus
|
||
Bufferandforcingtheoutputs oftheS216'sinto
|
||
theirhighimpedance (3-state) mode.Thisallows
|
||
otherdevicestogainaccesstothedatabus(DMA).
|
||
SystemControl LogicDesign
|
||
TheControl Busmaintains discipline ofthebi-direc
|
||
tionalDataBus,thatis,itdetermines whattypeof
|
||
devicewillhaveaccesstothebus(Memory orI/O)
|
||
andgenerates signalstoassurethatthesedevices
|
||
transfer DatawiththeSOSOCPUwithintheproper
|
||
timing"windows" asdictated bytheCPUoperational
|
||
characteristics.
|
||
Asdescribed previously, the8080issuesStatusinfor
|
||
mationatthebeginning ofeachMachine Cycleonits
|
||
DataBustoindicate whatoperation willtakeplace
|
||
duringthatcycle.Asimple(8)bitlatch,likean
|
||
INTEL®8212,connected directly tothe80S0Data
|
||
Bus(07-00) asshowninfigure3-5willstorethe
|
||
3-5Statusinformation. Thesignalthatloadsthedata
|
||
intotheStatusLatchcomesfromtheClockGener
|
||
ator,itisStatusStrobe(STSTB) andoccursatthe
|
||
startofeachMachine Cycle.
|
||
NotethattheStatusLatchisconnected ontothe
|
||
SOSODataBus(07-00) beforetheBusBuffer.Thisis
|
||
tomaintain theintegrity oftheDataBusandsimplify
|
||
Control BustiminginDMAdependent environments ..
|
||
Asshowninthediagram, asimplegatingoftheout
|
||
putsoftheStatusLatchwiththeDBINandWR
|
||
signalsfromtheS080generate the(4)fourControl
|
||
signalsthatmakeupthebasicControl Bus.
|
||
Thesefoursignals:1.Memory Read(MEMR)
|
||
2.Memory Write(MEMW)
|
||
3.I/ORead(I/OR)
|
||
4.I/OWrite(I/OW)
|
||
TM
|
||
connect directlytotheMCS-80component "family"
|
||
ofROMs,RAMsandI/Odevices.
|
||
Afifthsignal,Interrupt Acknowledge (lNTA) is
|
||
addedtotheControl Busbygatingdataoffthe
|
||
StatusLatchwiththeDBINsignalfromtheS080
|
||
CPU.ThissignalisusedtoenabletheInterrupt
|
||
Instruction PortwhichholdstheRSTinstruction
|
||
ontotheDataBus.
|
||
OthersignalsthatarepartoftheControl Bussuchas
|
||
WO,StackandM1arepresenttoaidinthetestingof
|
||
theSystemandalsotosimplify interfacing theCPU
|
||
todynamic memories orverylargesystemsthatre
|
||
quireseverallevelsofbusbuffering.
|
||
Address BufferDesign
|
||
TheAddress Bus(A15-AO)ofthe8080,liketheData
|
||
Bus,issufficient tosupport asmallsystemthathasa
|
||
moderate sizeMemory andI/Ostructure, confined to
|
||
asinglecard.Toexpandthesizeofthesystemthat
|
||
theAddress Buscansupport asimplebuffercanbe
|
||
added,asshowninfigure3-6.TheINTEL®S212 or
|
||
8216isanexcellent deviceforthisfunction. They
|
||
provide lowinputloading (.25mA),highoutput
|
||
driveandinsertaminimal delayintheSystem
|
||
Timing.
|
||
NotethatBUSENABLE (BUSEN) isconnected to
|
||
thebufferssothattheyareforcedintotheirhigh
|
||
impedance (3-state) modeduringDMAactivities so
|
||
thatotherdevicescangainaccesstotheAddress Bus.
|
||
|
||
===PAGE 40===
|
||
INTERFACING THE8080CPUTOMEMORY
|
||
ANDI/ODEVICES
|
||
The8080interfaces withstandard semiconductor
|
||
Memory components andI/Odevices. Intheprevious text
|
||
thepropercontrol signalsandbuffering weredeveloped
|
||
whichwillproduce asimplebussystemsimilartothebasic
|
||
systemexample shownatthebeginning ofthischapter.
|
||
InFigure3-6asimple,butexact8080'typicalsystem
|
||
isshownthatcanbeusedasaguideforany8080system,
|
||
regardless ofsizeorcomplexity. Itisa"threebus"archi
|
||
tecture, usingthesignalsdeveloped intheCPUmodule.
|
||
NotethatMemory andI/Odevicesinterface inthe
|
||
samemannerandthattheirisolation isonlyafunction of
|
||
thedefinition oftheRead-Write signalsontheControl Bus.
|
||
Thisallowsthe8080systemtobeconfigured sothatMem
|
||
oryandI/Oaretreatedasasinglearray(memory mapped
|
||
I/O)forsmallsystemsthatrequirehighthruput andhave
|
||
lessthan32Kmemory size.Thisapproach willbebrought
|
||
outlaterinthechapter.Thisfeatureeliminates theneedforextraequipment like
|
||
tapereadersanddiskstoloadprograms initially, anim
|
||
portantaspectinsmallsystemdesign.
|
||
Interfacing standard ROMs,suchasthedevicesshown
|
||
inthediagram issimpleanddirect.TheoutputDatalines
|
||
areconnected tothebi-directional DataBus,theAddress
|
||
inputstietotheAddress buswithpossible decoding ofthe
|
||
mostsignificant bitsasIIchipselects" a~dtheMEMRsignal
|
||
fromtheControl Busconnected toa"chipselect"ordata
|
||
buffer.Basically, theCPUissuesanaddressduringthefirst
|
||
portionofaninstruction ordatafetch(Tl&T2).This
|
||
valueontheAddress Busselectsaspecific location within
|
||
theROM,thendepending ontheROM'sdelay(accesstime)
|
||
thedatastoredattheaddressed location ispresentatthe
|
||
Dataoutputlines.Atthistime(T3)theCPUDataBusis
|
||
inthe"inputMode"andthecontrollogicissuesaMemory
|
||
Readcommand (MEMR) thatgatestheaddressed dataon
|
||
totheDataBus.
|
||
RAMINTERFACE
|
||
ROMINTERFACE
|
||
AROMisadevicethatstoresdataintheformof
|
||
Program orotherinformation suchas"look-up tables"and
|
||
isonlyreadfrom,thusthetermReadOnlyMemory. This
|
||
typeofmemory isgenerallY' non-volatile, meaning that
|
||
whenthepowerisremoved theinformation isretained.ARAMisadevicethatstoresdata.Thisdatacanbe
|
||
program, active"look-up tables," temporary valuesorex
|
||
ternalstacks.Thedifference between RAMandROMis
|
||
thatdatacanbewritten intosuchdevicesandarein
|
||
essence, Read/Write storageelements. RAMsdonothold
|
||
theirdatawhenpowerisremoved sointhecasewherePro
|
||
gramor"look-up tables"dataisstoredamethodtoload
|
||
HOLDREO
|
||
WRDO-D7DBIN HLDA AO-A15
|
||
{}D"---_~rl {[-DL...-.--_n '0o::=c
|
||
CONTROL BUS(6)8102A·4
|
||
8107B·4
|
||
8210
|
||
8222RAMs
|
||
51018101-2
|
||
8111·2
|
||
8102-28302
|
||
8308
|
||
8316AROMs8702A
|
||
8704
|
||
8708
|
||
DATABUS(8)!r-:--------"1
|
||
I8212 ADDRESS
|
||
II8205 BUFFERSI II DECODER I
|
||
lL.83..1~ (OP~I£.N~~..J
|
||
u___ LCJJ~)7 I
|
||
ADDRESS BUS(16)
|
||
8251 I/O
|
||
COMMUNICATION
|
||
INTERFACE8212
|
||
8255I/O
|
||
PERIPHERAL
|
||
INTERFACE8214
|
||
8212PRIORITY
|
||
INTERRUPT
|
||
Figure3-6.Microcomputer System
|
||
3-6
|
||
|
||
===PAGE 41===
|
||
RAMmemory mustbeprovided, suchas:Floppy Disk,
|
||
PaperTape,etc.
|
||
TheCPUtreatsRAMinexactlythesamemanneras
|
||
ROMforaddressing datatoberead.Writingdataisvery
|
||
similar;theRAMisissuedanaddressduringthefirstpor
|
||
tionoftheMemory Writecycle(T1&T2)inT3whenthe
|
||
datathatistobewrittenisoutputbytheCPUandisstable
|
||
onthebusanMEMW command isgenerated. TheMEMW
|
||
signalisconnected totheR/WinputoftheRAMand
|
||
strobesthedataintotheaddressed location.
|
||
InFigure3-7atypicalMemory systemisillustrated
|
||
toshowhowstandard semiconductor components interface
|
||
tothe8080bus.Thememory arrayshownhas8Kbytes
|
||
• ®(8bits/byte) ofROMstorage, uSingfourIntel8216As
|
||
and512bytesofRAMstorage, usingIntel8111static
|
||
RAMs.Thebasicinterface tothebusstructure detailed
|
||
hereiscommon toalmostanysizememory. Theonlyad
|
||
ditionthatmighthavetobemadeforlargersystems is
|
||
morebuffers(8216/8212) anddecoders (8205)forgener
|
||
ating"chipselects."Thememories chosenforthisexample haveanaccess
|
||
timeof850nS(max)toillustrate thatslower,economical
|
||
devicescanbeeasilyinterfaced tothe8080withlittleef
|
||
fectonperformance. Whenthe8080isoperated froma
|
||
clockgenerator withatCYof500nStherequired memory
|
||
accesstimeisApprox. 450-550 nS.Seedetailed timing
|
||
specification Pg.5-16.Usingmemory devicesofthisspeed
|
||
suchasIntel@8308, 8102A,8107A, etc.theREADY input
|
||
tothe·8080CPUcanremain"high"because no"wait"
|
||
statesarerequired. Notethatthebusinterface tomemory
|
||
showninFigure3-7remainsthesame.However, ifslower
|
||
memories aretobeused,suchasthedevices illustrated
|
||
(8316A, 8111)thathaveaccesstimesslowerthanthemin
|
||
imumrequirement asimplelogiccontroloftheREADY
|
||
inputtothe8080CPUwillinsertanextra"waitstate"that
|
||
isequaltooneormoreclockperiods asanaccesstime
|
||
"adjustment" deiaytocompensate. Theeffectoftheextra
|
||
"wait"stateisnaturally aslowerexecution timeforthe
|
||
instruction. Asingle"wait"changes thebasicinstruction
|
||
cycleto2.5microSeconds.
|
||
8K+512
|
||
RAM8K o
|
||
ROM
|
||
MEMORY MAP
|
||
ROM
|
||
RAM-----------, ---------- ....#4.:.- ...........
|
||
#3;;. ..-.
|
||
#2
|
||
#1
|
||
8111
|
||
FiJW001/01-4AO-A78111
|
||
R/W001/01-4 AO-A7
|
||
AO-A78316A
|
||
01-08CS3
|
||
CS2
|
||
AO-Al0
|
||
All
|
||
A12
|
||
_01.--_0 DATABUSIsiJL.-..--_IJL--.------L----_DL----
|
||
CONTROL BUS(6)_-.-ill n 11_
|
||
ADDRESS BUS(16)
|
||
Figure3-7.TypicalMemory Interface
|
||
3-7
|
||
|
||
===PAGE 42===
|
||
I/OINTERFACE
|
||
Figure3-9.Isolated I/O.
|
||
MemoryMappedI/O
|
||
Itiseasytoseethatfromthelistofpossible "new"
|
||
instructions thatthistypeofI/Oarchitecture couldhavea
|
||
drasticeffectonincreased systemthroughput. Itisconcep
|
||
tuallymoredifficult tounderstand thanIsolated I/Oandit
|
||
doeslimitmemory addressspace,butMemory Mapped I/O
|
||
canmeanasignificant increase inoverallspeedandatthe
|
||
sametimereducing re~uired program memory area.I/OR}
|
||
TOI/ODEVICES
|
||
~----I/OWMEMR}TOMEMORY__ DEVICES
|
||
~----MEMW
|
||
(InputPorttoanyRegister)
|
||
(Output anyRegistertoPort)
|
||
(Output immediate datatoPort)
|
||
(InputtoACC)
|
||
(Output fromACCtoPort)
|
||
(1~BitInput)
|
||
(16BitOutput)
|
||
(AddPorttoACC)
|
||
("AND" PortwithACC)SYSTEM
|
||
CONTROL
|
||
(8228)
|
||
Examples:
|
||
MOVr,M
|
||
MOVM,r
|
||
MVIM
|
||
LOA
|
||
STA
|
||
LHLO
|
||
SHLO
|
||
ADDM
|
||
ANAMByassigning anareaofmemory addressspaceasI/Oa
|
||
powerful architecture canbedeveloped thatcanmanipulate
|
||
I/Ousingthesameinstructions thatareusedtomanipulate
|
||
memory locations. Thus,a"new"instruction setiscreated
|
||
thatisdevotedtoI/Ohandling.
|
||
AsshowninFigure3-10,newcontrolsignalsaregene
|
||
ratedbygatingtheMEMRandMEMWsignalswithA15,the
|
||
mostsignificant addressbit.ThenewI/Ocontrolsignalscon
|
||
nectinexactlythesamemannerasIsolated I/O,thusthe
|
||
systembuscharacteristics areunchanged.
|
||
Byassigning A15astheI/O"flag",asimplemethodof
|
||
I/Odiscipline ismaintained:
|
||
IfA15isa"zero"thenMemory isactive.
|
||
IfA15isa"one"thenI/Oisactive.
|
||
Otheraddressbitscanalsobeusedforthisfunction. A15was
|
||
chosenbecause itisthemostsignificant addressbitsoitis
|
||
easiertocontrol withsoftware andbecause itstillallows
|
||
memory addressing of32K.
|
||
I/Odevicesarestillconsidered addressed IIports"but
|
||
insteadoftheAccumulator astheonlytransfer medium any
|
||
oftheinternal registers canbeused.Allinstructions that
|
||
couldbeusedtooperateonmemory locations canbeused
|
||
inI/O.GeneralTheory
|
||
ISOLATED I/O
|
||
~--------------------I
|
||
1 ME;;RYT!
|
||
o ~6 :c:=J i
|
||
Ir---------------------j
|
||
!IMEMORYT I/OT!
|
||
I MEMORY MAPPED I/O I ~ J
|
||
Figure3-8.Memory/I/O Mapping.
|
||
IsolatedI/O
|
||
InFigure3-9thesystemcontrolsignals,previously de
|
||
tailedinthischapter, areshown. Thi~typeofI/Oarchitecture
|
||
separates thememory addressspacefromtheI/Oaddress
|
||
spaceandusesaconceptually simpletransfertoorfromAc
|
||
cumulator technique. Suchanarchitecture iseasytounder
|
||
standbecause I/Ocommunicates onlywiththeAccumulator
|
||
usingtheINorOUTinstructions. Alsobecauseoftheisola
|
||
tionofmemory andI/O,thefulladdressspace(65K)isun
|
||
effected byI/Oaddressing.Asinanycomputer basedsystem,the8080CPUmust
|
||
beabletocommunicate withdevicesorstructures thatexist
|
||
outside itsnormalmemory array.Devices likekeyboards,
|
||
papertape,floppydisks,printers, displays andothercontrol
|
||
structures areusedto'inputinformation intothe8080CPU
|
||
anddisplayorstoretheresultsofthecomputational activity.
|
||
Probably themostimportant andstrongest featureof
|
||
the8080Microcomputer Systemistheflexibility andpower
|
||
ofitsI/Ostructure andthecomponents thatsupportit.There
|
||
aremanywaystostructure theI/Oarraysothatitwill"fit"
|
||
thetotalsystemenvironment tomaximize efficiency and
|
||
minimize component count.
|
||
Thebasicoperation oftheI/Ostructure canbestbe
|
||
viewedasanarrayofsinglebytememory locations thatcan
|
||
beReadfromorWritteninto.The8080CPUhasspecialin
|
||
structions devoted tomanaging suchtransfers (IN,OUT).
|
||
Theseinstructions generally isolatememory andI/Oarrays
|
||
sothatmemory address spaceisnoteffected bytheI/O
|
||
structure andthegeneralconcept isthatofasimpletransfer
|
||
toorfromtheAccumulator withanaddressed "PORT". An
|
||
othermethodofI/Oarchitecture istotreattheI/Ostructure
|
||
aspartoftheMemory array.Thisisgenerally referredtoas
|
||
"Memory Mapped I/O"andprovides thedesigner witha
|
||
powerful new"instruction set"devotedtoI/Omanipulation.
|
||
3-8
|
||
|
||
===PAGE 43===
|
||
10--------...--- MEMRThesecondexample usesMemory Mapped I/Oand
|
||
linearselecttoshowhowthirteen devices(8255)canbead
|
||
dressedwithouttheuseofextradecoders. Theformatshown
|
||
couldbethesecondandthirdbytesoftheLDAorSTAin
|
||
structions oranyotherinstructions usedtomanipulate I/O
|
||
usingtheMemory Mapped technique.
|
||
ItiseasytoseethatsuchaflexibleI/Ostructure, that
|
||
canbe"tailored" totheoverallsystemenvironment, provides
|
||
thedesigner withapowerful tooltooptimize efficiency and
|
||
minimize component count.}TO
|
||
MEMORY
|
||
DEVICES
|
||
I/OR(MMJ-
|
||
TOI/O
|
||
DEVICES
|
||
I/OW(MM)I/OR}NOT
|
||
_USED
|
||
IIOWr>-----.---+---- MEMW
|
||
SYSTEM
|
||
CONTROL
|
||
(8228)
|
||
EXAMPLE #2
|
||
}PORTSELECTS
|
||
'-- }DEVICE SELECTS
|
||
"'------------ 1/0FLAGI=I/O
|
||
0=MEMORYDEVICESELECTS
|
||
ADDRESSES -13-82555
|
||
(39PORTS-312BITS)I/OAddressing
|
||
Withbothsystems ofI/Ostructure theaddressing of
|
||
eachdevicecanbeconfigured tooptimize efficiency andre
|
||
ducecomponent count.Onemethod, themostcommon, is
|
||
todecodetheaddressbusintoexclusive "chipselects"that
|
||
enabletheaddressed I/Odevice,similartogenerating chip
|
||
selectsinmemory arrays.
|
||
Another method iscalled"Iinearselect".Inthismethod,
|
||
insteadofdecoding theAddress Bus,asingular bitfromthe
|
||
busisassigned astheexclusive enableforaspecific I/0de
|
||
vice.Thismethod, ofcourse,limitsthenumber ofI/Ode
|
||
vicesthatcanbeaddressed buteliminates theneedforextra
|
||
decoders, animportant consideration insmallsystemdesign.
|
||
Asimpleexample illustrates thepowerofsuchaflexi
|
||
bleI/Ostructure. Thefirstexample illustrates theformatof
|
||
thesecondbyteoftheINor0UTinstruction usingtheIso
|
||
latedI/Otechnique. ThedevicesusedareIntel®8255 Pro
|
||
grammable Peripheral Interface unitsandarelinearselected.
|
||
Eachdevicehasthreeportsandfromtheformatitcanbe
|
||
seenthatsixdevicescanbeaddressed without additional de
|
||
coders.Figure3-10.MemoryMappedI/O.
|
||
Figure3-12.Memory MappedI/O-(LinearSelect(8255)
|
||
EXAMPLE #1
|
||
I/OInterface Example
|
||
}PORTSELECTS
|
||
'-- }DEVICE SELECTS
|
||
ADDRESSES - 6 -82555
|
||
(18PORTS-144BITS)
|
||
Figure3-11.IsolatedI/O-(LinearSelect)(8255)InFigure3-16atypicalI/Osystemisshownthatusesa
|
||
varietyofdevices(8212,8251and8255).Itcouldbeused
|
||
tointerface theperipherals aroundanintelligent CRTtermi
|
||
nals;keyboards, display, andcommunication interface. An
|
||
otherapplication couldbeinaprocesscontroller tointerface
|
||
sensors, relays,andmotorcontrols. Thelimitation oftheap
|
||
plication areaforsuchacircuitissolelythatofthedesigners
|
||
imagination.
|
||
TheI/Ostructure showninterfaces tothe8080CPU
|
||
usingthebusarchitecture developed previously inthischap
|
||
ter.EitherIsolatedorMemory Mapped techniques canbe
|
||
used,depending onthesystemI/Oenvironment.
|
||
The8251provides aserialdatacommunication inter
|
||
facesothatthesystemcantransmitandreceivedataover
|
||
communication linkssuchastelephone lines.
|
||
3-9
|
||
|
||
===PAGE 44===
|
||
Thetwo(2)8255sprovidetwentyfourbitseachof
|
||
programmable I/Oda~aandcontrolsothatkeyboards, sen
|
||
sors,papertape,etc.,canbeinterfaced tothesystem.C/DCONTROL
|
||
_____________________ 8251SELECT
|
||
(ACTIVE LOW)
|
||
Figure3-13.8251Format.O-DATA
|
||
1-COMMANDThethree8212scanbeusedtodrivelonglinesorLED
|
||
indicators duetotheirhighdrivecapability. (15mA)
|
||
________________________ 8212#1SELECT
|
||
(ACTIVE HIGH)
|
||
___________ 8212#2SELECT
|
||
(ACTIVE HIGH)
|
||
_____________ 8212#3SELECT
|
||
(ACTIVE HIGH)
|
||
Figure3-15.8212Format.
|
||
}PORTSELECT
|
||
'--- 8255#1SELECT
|
||
(ACTIVE LOW)
|
||
"------- 8(~g::~~i~E~;rOO-PORTA
|
||
01-PORTB
|
||
10-PORTC
|
||
11-COMMANDAddressing thestructure isdescribed intheformatsil
|
||
lustrated inFigures3-13,3-14,3-15.LinearSelectisusedso
|
||
thatnodecoders arerequiredthus,eachdevicehasanex
|
||
clusive"enablebit".
|
||
Theexample showshowapowerful yetflexible I/O
|
||
structure canbecreatedusingaminimum component count
|
||
withdevicesthatareallmembers ofthe8080Microcomputer
|
||
System.
|
||
Figure3..14.8255Format.
|
||
SERIALDATA
|
||
COMMUNICATION
|
||
#1
|
||
8255#2
|
||
8255
|
||
D~.DocsAoA,
|
||
DATABUS
|
||
CONTROL BUS8251
|
||
8212
|
||
#38212
|
||
#28212
|
||
#1
|
||
MD MD MD
|
||
Figure3-16.TypicalI/OInterface.
|
||
3-10
|
||
|
||
===PAGE 45===
|
||
Acomputer, nomatterhowsophisticated, canonly
|
||
dowhatitis"told"todo.One"tells"thecomputer what
|
||
todoviaaseriesofcodedinstructions referredtoasaPro
|
||
gram.Therealmoftheprogrammer isreferred toasSoft
|
||
ware,incontrast totheHardware thatcomprises theactual
|
||
computer equipment. Acomputer's software referstoallof
|
||
theprograms thathavebeenwrittenforthatcomputer.
|
||
Whenacomputer isdesigned, theengineers provide
|
||
theCentralProcessing Unit(CPU)withtheabilitytoper
|
||
formaparticular setofoperations. TheCPUisdesigned
|
||
suchthataspecificoperation isperformed whentheCPU
|
||
controllogicdecodes aparticular instruction. Consequently,
|
||
theoperations thatcanbeperformed byaCPUdefinethe
|
||
computer's Instruction Set.
|
||
Eachcomputer instruction allowstheprogrammer to
|
||
initiatetheperformance ofaspecificoperation. Allcom
|
||
putersimplement certainarithmetic operations intheirin
|
||
struction set,suchasaninstruction toaddthecontents of
|
||
tworegisters. Oftenlogicaloperations (e.g.,0Rthecon
|
||
tentsoftworegisters) andregisteroperateinstructions (e.g.,
|
||
increment aregister) areincluded intheinstruction set.A
|
||
computer's instruction setwillalsohaveinstructions that
|
||
movedatabetween registers, between aregisterandmemory,
|
||
andbetween aregisterandanI/Odevice.Mostinstruction
|
||
setsalsoprovide Conditional Instructions. Aconditional
|
||
·instruction specifies anoperation tobeperformed onlyif
|
||
certainconditions havebeenmet;forexample, jumptoa
|
||
particular instruction iftheresultofthelastoperation was
|
||
zero.Conditional instructions provide aprogram witha
|
||
decision-making capability.
|
||
Bylogically organizing asequence ofinstructions into
|
||
acoherent program, theprogrammer can"tell"thecom
|
||
putertoperform averyspecificandusefulfunction.
|
||
Thecomputer, however, canonlyexecute programs
|
||
whoseinstructions areinabinarycodedform(Le.,·aseries
|
||
of1'sandD's),thatiscalledMachine Code.Because it
|
||
wouldbeextremely cumbersome toprogram inmachine
|
||
code,programming languages havebeendeveloped. There
|
||
4-1areprograms available whichconverttheprogramming lan
|
||
guageinstructions intomachine codethatcanbeinter
|
||
pretedbytheprocessor.
|
||
Onetypeofprogramming language isAssembly lan
|
||
guage.Auniqueassembly language mnemonic isassignedto
|
||
eachofthecomputer's instructions. Theprogrammer can
|
||
writeaprogram (calledtheSourceProgram) usingthese
|
||
mnemonics andcertainoperands; thesourceprogram is
|
||
thenconverted intomachine instructions (calledtheObject
|
||
Code).Eachassembly language instruction isconverted into
|
||
onemachine codeinstruction (1ormorebytes)byan
|
||
Assembler program. Assembly languages are usually ma
|
||
chinedependent (Le.,theyareusuallyabletorunononly
|
||
onetypeofcomputer).
|
||
THE8080INSTRUCTION SET
|
||
The8080instruction setincludes fivedifferent types
|
||
ofinstructions:
|
||
•DataTransfer Group-move databetween registers
|
||
orbetween memory andregisters
|
||
•Arithmetic Group-add,subtract, increment or
|
||
decrement datainregisters orinmemory
|
||
•logical Group-AND,OR,EXCLUSIVE-OR,
|
||
compare, rotateorcomplement datainregisters
|
||
orinmemory
|
||
•BranchGroup-conditional andunconditional
|
||
jumpinstructions, subroutine callinstructions and
|
||
returninstructions
|
||
•Stack,I/OandMachine ControlGroup-includes
|
||
I/Oinstructions, aswellasinstructions formain
|
||
tainingthestackandinternalcontrolflags.
|
||
Instruction andDataFormats:
|
||
Memory forthe8080isorganized into8-bitquanti
|
||
ties,calledBytes.Eachbytehasaunique16-bitbinary
|
||
addresscorresponding toitssequential position inmemory.
|
||
|
||
===PAGE 46===
|
||
Condition Flags:
|
||
Therearefivecondition flagsassociated withtheexe
|
||
cutionofinstructions onthe8080.TheyareZero,Sign,
|
||
Parity,Carry,andAuxiIiaryCarry,andareeachrepresented
|
||
byal-bitregisterintheCPU.Aflagis"set"byforcingthe
|
||
bitto1;"reset"byforcingthebittoO.
|
||
Unlessindicated otherwise, whenaninstruction af
|
||
fectsaflag,itaffectsitinthefollowing manner:
|
||
Zero: Iftheresultofaninstruction hasthe
|
||
value0,thisflagisset;otherwise itis
|
||
reset.address wherethedataislocated (the
|
||
high-order bitsoftheaddressareinthe
|
||
firstregisterofthepair,thelow-order
|
||
bitsinthesecond).
|
||
•Immediate -Theinstruction contains thedatait
|
||
self.Thisiseitheran8-bitquantity ora
|
||
16-bitquantity (leastsignificant bytefirst,
|
||
mostsignificant bytesecond).
|
||
Unlessdirected byaninterrupt orbranchinstruction,
|
||
theexecution ofinstructions proceeds through consecu
|
||
tivelyincreasing memory locations. Abranchinstruction
|
||
canspecifytheaddressofthenextinstruction tobeexe
|
||
cutedinoneoftwoways:
|
||
•Direct-Thebranchinstruction contains thead
|
||
dressofthenextinstruction tobeexe
|
||
cuted.(Except forthe'RST'instruction,
|
||
byte2contains thelow-order addressand
|
||
byte3thehigh-order address.)
|
||
•Register indirect -Thebranchinstruction indi
|
||
catesaregister-pair whichcontains the
|
||
addressofthenextinstruction tobeexe
|
||
cuted.(Thehigh-order bitsoftheaddress
|
||
areinthefirstregisterofthepair,the
|
||
low-order bitsinthesecond.)
|
||
TheRSTinstruction isaspecialone-byte callinstruc
|
||
tion(usually usedduringinterrupt sequences). RSTin
|
||
cludesathree-bit field;program control istransferred to
|
||
theinstruction whoseaddress iseighttimesthecontents
|
||
ofthisthree-bit field.The8080candirectly addressupto65,536bytesofmem
|
||
ory,whichmayconsistofbothread-only memory (ROM)
|
||
elements andrandom-access memory (RAM)elements (read/
|
||
writememory).
|
||
Oatainthe8080isstoredintheformof8-bitbinary
|
||
integers:
|
||
OATAWORO
|
||
II 1 1 I 1 I I I07060504 03 02D100
|
||
MSB LSB
|
||
Whenaregisterordatawordcontains abinarynum
|
||
ber,itisnecessary toestablish theorderinwhichthebits
|
||
ofthenumber arewritten. IntheIntel8080,BIT0isre
|
||
ferredtoastheLeastSignificant Bit(LSB),andBIT7(of
|
||
an8bitnumber) isreferredtoastheMost Significant Bit
|
||
(MSB).
|
||
The8080program instructions maybeone,twoor
|
||
threebytesinlength.Multiple byteinstructions mustbe
|
||
storedinsuccessive memory locations; theaddressofthe
|
||
firstbyteisalwaysusedastheaddressoftheinstructions.
|
||
Theexactinstruction formatwilldependontheparticular
|
||
operation tobeexecuted.
|
||
SingleByteInstructions
|
||
Two-Byte Instructions
|
||
ByteOne1_0_7_' 'I__0.......JoIOpCode
|
||
ByteTwoID7I IDoIOataor
|
||
-,-------------, Address
|
||
Three-Byte Instructions
|
||
ByteOneI_D_7_11_00IOpCode
|
||
ByteTwoID71IDoI)Oata
|
||
or
|
||
ByteThreeID7I IDoIAddress
|
||
Addressing Modes:
|
||
Oftenthedatathatistobeoperated onisstoredin
|
||
memory. Whenmulti-byte numeric dataisused,thedata,
|
||
likeinstructions, isstoredinsuccessive memory locations,
|
||
withtheleastsignificant bytefirst,followed byincreasingly
|
||
significant bytes.The8080hasfourdifferent modesfor
|
||
addressing datastoredinmemory orinregisters:
|
||
•Oirect-Bytes2and3oftheinstruction contain
|
||
theexactmemory addressofthedata
|
||
item(thelow-order bitsoftheaddressare
|
||
inbyte2,thehigh-order bitsinbyte3).
|
||
•Register -Theinstruction specifies theregisteror
|
||
register-pair inwhichthedataislocated.
|
||
•Register Indirect -Theinstruction specifies areg
|
||
ister-pair whichcontains thememory
|
||
4-2Sign:
|
||
Parity:
|
||
Carry:Ifthemostsignificant bitoftheresultof
|
||
theoperation hasthevalue1,thisflagis
|
||
set;otherwise itisreset.
|
||
Ifthemodulo2sumofthebitsofthere
|
||
sultoftheoperation is0,(Le.,ifthe
|
||
resulthasevenparity), thisflagisset;
|
||
otherwise itisreset(Le.,iftheresulthas
|
||
oddparity).
|
||
Iftheinstruction resulted inacarry
|
||
(fromaddition), oraborrow(fromsub
|
||
traction oracomparison) outofthehigh
|
||
orderbit,thisflagisset;otherwise itis
|
||
reset.
|
||
|
||
===PAGE 47===
|
||
accumulator Register A
|
||
addr 16-bitaddressquantity
|
||
data 8-bitdataquantitySymbols andAbbreviations:
|
||
Thefollowing symbols andabbreviations areusedin
|
||
thesubsequent description ofthe8080instructions:
|
||
SYMBOLS MEANINGAuxiliary Carry:Iftheinstruction causedacarryout
|
||
ofbit3andintobit4oftheresulting
|
||
value,theauxiliary carryisset;otherwise
|
||
itisreset.Thisflagisaffected bysingle
|
||
precision additions, subtractions, incre
|
||
ments,decrements, comparisons, andlog
|
||
icaloperations, butisprincipally used
|
||
withadditions andincrements preceding
|
||
aDAA(Decimal AdjustAccumulator)
|
||
instruction.
|
||
LogicalAND
|
||
Exclusive 0R
|
||
Inclusive OR
|
||
Addition
|
||
Two'scomplement subtraction
|
||
Multiplication
|
||
"Isexchanged with"
|
||
Theone'scomplement (e.g.,(A))
|
||
Therestartnumberathrough7
|
||
Thebinaryrepresentation 000through 111
|
||
forrestartnumber0through7respectively."1stransferred to"
|
||
n
|
||
NNN*()
|
||
/\
|
||
V
|
||
V
|
||
+rh Thefirst(high-order) registerofadesignated
|
||
registerpair.
|
||
rl Thesecond (low-order) registerofadesig
|
||
natedregisterpair.
|
||
PC 16-bitprogram counter register (PCHand
|
||
PClareusedtorefertothehigh-order and
|
||
low-order 8bitsrespectively).
|
||
SP 16-bitstackpointer register (SPHandSPL
|
||
areusedtorefertothehigh-order andlow
|
||
order8bitsrespectively).
|
||
rm Bitmoftheregister r(bitsarenumber7
|
||
throughafromlefttoright).
|
||
Z,S,P,CY,AC Thecondition flags:
|
||
Zero,
|
||
Sign,
|
||
Parity,
|
||
Carry,
|
||
andAuxiliary Carry,respectively.
|
||
Thecontents ofthememory location orreg
|
||
istersenclosed intheparentheses.
|
||
DODorSSSREGISTER NAME
|
||
111 A
|
||
000 B
|
||
001 C
|
||
010 D
|
||
all E
|
||
100 H
|
||
101 L16-bitdataquantity
|
||
Thesecondbyteoftheinstruction
|
||
Thethirdbyteoftheinstruction
|
||
8-bitaddressofanI/Odevice
|
||
Oneoftheregisters A,B,C,D,E,H,L
|
||
Thebitpatterndesignating oneoftheregis
|
||
tersA,B,C,D,E,H,L (DDD=destination, SSS=
|
||
source):data16
|
||
byte2
|
||
byte3
|
||
port
|
||
r,rl,r2
|
||
DDD,SSS
|
||
Oneoftheregisterpairs:
|
||
Brepresents theB,CpairwithBasthehigh
|
||
orderregisterandCasthelow-order register;
|
||
Drepresents theD,EpairwithDasthehigh
|
||
orderregisterandEasthelow-order register;
|
||
Hrepresents theH,LpairwithHasthehigh
|
||
orderregisterandLasthelow-order register;
|
||
SPrepresents the16-bitstackpointer
|
||
register.
|
||
Thebitpatterndesignating oneoftheregis
|
||
terpairsB,D,H,SP:rp
|
||
RP
|
||
RP
|
||
00
|
||
01
|
||
10
|
||
11REGISTER PAIR
|
||
B-C
|
||
D-E
|
||
H-L
|
||
SPDescription Format:
|
||
Thefollowing pagesprovide adetailed description of
|
||
theinstruction setofthe8080.Eachinstruction isde
|
||
scribedinthefollowing manner:
|
||
1.TheMAC80assembler format, consisting of
|
||
theinstruction mnemonic andoperand fields,is
|
||
printedinBOLDFACE ontheleftsideofthefirst
|
||
line.
|
||
2.Thenameoftheinstruction isenclosed inparen
|
||
thesisontherightsideofthefirstline.
|
||
3.Thenextline(s)contain asymbolic description
|
||
oftheoperation oftheinstruction.
|
||
4.Thisisfollowed byanarative description ofthe
|
||
operation oftheinstruction.
|
||
5.Thefollowing line(s)containthebinaryfieldsand
|
||
patternsthatcomprise themachine instruction.
|
||
4-3
|
||
|
||
===PAGE 48===
|
||
6.Thelastfourlinescontainincidental information
|
||
abouttheexecution oftheinstruction. Thenum
|
||
berofmachine cyclesandstatesrequired toexe
|
||
cutetheinstruction arelistedfirst.Iftheinstruc
|
||
tionhastwopossible execution times,asina
|
||
Conditional Jump·,bothtimeswillbelisted,sep
|
||
aratedbyaslash.Next,anysignificant dataad
|
||
dressing modes'(seePage4-2)arelisted.Thelast
|
||
linelistsanyofthefiveFlagsthatareaffectedby
|
||
theexecution oftheinstruction.
|
||
DataTransfer Group:
|
||
Thisgroupofinstructions transfers datatoandfrom
|
||
registers andmemory. Condition flagsarenotaffected by
|
||
anyinstruction inthisgroup.MVIr,data (MoveImmediate)
|
||
(r)~(byte2)
|
||
Thecontentofbyte2oftheinstruction ismovedto
|
||
registerr.
|
||
MVIM,data (Movetomemory immediate)
|
||
((H)(L))~(byte2)
|
||
Thecontentofbyte2oftheinstruction ismovedto
|
||
thememory location whoseaddress isinregistersH
|
||
andL.MOVr1,r2 (MoveRegister)
|
||
(r1)"'- (r2)
|
||
Thecontentofregisterr2ismovedtoregisterr1.
|
||
0IDIDIDSSIS
|
||
'.1f'.\Cyc·'es: 1
|
||
States: 5
|
||
Addressing: register
|
||
Flags: noneoI0
|
||
datao1 ' 1I0
|
||
MOVr,M (Movefrommemory)
|
||
(r)~((H)(L))
|
||
Thecontentofthememory location, whoseaddress
|
||
isinregistersHandL,ismovedtoregisterr.Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:3
|
||
10
|
||
immed.lreg. indirect
|
||
none
|
||
1II0
|
||
MOVM,r(Movetomemory)
|
||
((H)(L))~ (r)
|
||
Thecontentofregisterrismovedtothememory lo
|
||
cationwhoseaddressisinregistersHandL.
|
||
o '1ICycles:
|
||
States:
|
||
Addressing:
|
||
Flags:2
|
||
7
|
||
reg.indirect
|
||
noneLXIrp,data16 (Loadregisterpairimmediate)
|
||
(rh)~(byte3),
|
||
(rl)~(byte2)
|
||
Byte3oftheinstruction ismovedintothehigh-order
|
||
register(rh)oftheregisterpairrp.Byte2ofthein
|
||
struction ismovedintothelow-order register(rl)of
|
||
theregisterpairrp.
|
||
oIoIR1pIoIoIoI1
|
||
low-order data
|
||
high-order data
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:2
|
||
7
|
||
reg.indirect
|
||
none
|
||
4-4Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:3
|
||
10
|
||
immediate
|
||
none
|
||
|
||
===PAGE 49===
|
||
high-order addroI0I 1 I 1 111 0I 1 I 0
|
||
low-order addrLOAaddr (LoadAccumulator direct)
|
||
(A)~((byte3)(byte2))
|
||
Thecontent ofthememory location, whoseaddress
|
||
isspecified inbyte2andbyte3oftheinstruction, is
|
||
movedtoregisterA.
|
||
0I0I1I0I0T0T1I0
|
||
low-order addr
|
||
high-order addr
|
||
5
|
||
16
|
||
direct
|
||
noneCycles:
|
||
States:
|
||
Addressing:
|
||
Flags:SHLDaddr (StoreHandLdirect)
|
||
((byte3)(byte2))~(L)
|
||
((byte3)(byte 2)+1)~(H)
|
||
ThecontentofregisterLismovedtothememory Jo
|
||
cationwhoseaddress isspecified inbyte2andbyte
|
||
3.ThecontentofregisterHismovedtothesucceed
|
||
ingmemory location.
|
||
4
|
||
13
|
||
direct
|
||
noneCycles:
|
||
States:
|
||
Addressing:
|
||
Flags:
|
||
LOAXrp (Loadaccumulator indirect)
|
||
(A)~ ((rp))
|
||
Thecontent ofthememory location, whoseaddress
|
||
isintheregisterpairrp,ismovedtoregisterA.Note:
|
||
onlyregisterpairsrp=B(registers BandC·)orrp=D
|
||
(registers DandE)maybespecified.
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:STAaddr (StoreAccumulator direct)
|
||
((byte3)(byte 2))~(A)
|
||
Thecontent oftheaccumulator ismovedtothe
|
||
memory location whoseaddress isspecified inbyte
|
||
2andbyte3oftheinstruction.
|
||
0I0I1I1I0I0I1r0
|
||
low-order addr
|
||
high-order addroI0IRp
|
||
2
|
||
7
|
||
reg.indirect
|
||
none
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:4
|
||
13
|
||
dire<;t
|
||
noneSTAXrp (Storeaccumulator indirect)
|
||
((rp))~(A)
|
||
ThecontentofregisterAismovedtothememory lo
|
||
cationwhoseaddress isintheregisterpairrp.Note:
|
||
onlyregisterpairsrp=B(registers BandC)orrp=D
|
||
(registers DandE)maybespecified.
|
||
oI0IR
|
||
XCHG (Exchange HandLwithDandE)
|
||
(H)~(D)
|
||
(L)~(E)
|
||
Thecontents ofregistersHandLareexchanged with
|
||
thecontents ofregisters DandE.LHLDaddr (LoadHandLdirect)
|
||
(L)~((byte3)(byte2))
|
||
(H)~((byte3)(byte2)+1)
|
||
Thecontent ofthememory location, whoseaddress
|
||
isspecified inbyte2andbyte3oftheinstruction, is
|
||
movedtoregisterL.Thecontentofthememory loca
|
||
tionatthesucceeding address ismovedtoregisterH.
|
||
f
|
||
0I0I1I0I1I0I1T0
|
||
low-order addr
|
||
high-order addrCycles:
|
||
States:
|
||
Addressing:
|
||
Flags:
|
||
I1I02
|
||
7
|
||
reg.indirect
|
||
none
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:5
|
||
16
|
||
direct
|
||
noneCycles:
|
||
States:
|
||
Addressing:
|
||
Flags:1
|
||
4
|
||
register
|
||
none
|
||
4-5
|
||
|
||
===PAGE 50===
|
||
ADCr (AddRegister withcarry)
|
||
(A)~(A)+(r)+(CY)
|
||
Thecontent ofregisterrandthecontentofthecarry
|
||
bitareaddedtothecontentoftheaccumulator. The
|
||
resultisplacedintheaccumulator.
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:Arithmetic Group:
|
||
Thisgroupofinstructions performs arithmetic oper
|
||
ationsondatainregisters andmemory.
|
||
Unlessindicated otherwise, allinstructions inthis
|
||
groupaffecttheZero,Sign,Parity, Carry,andAuxiliary
|
||
Carryflagsaccordingtothestandard rules.
|
||
All~ubtraction operations areperformed viatwo's
|
||
complement arithmetic andsetthecarryflagtoonetoin
|
||
dicateaborrowandclearittoindicate noborrow.1I0I0o
|
||
1
|
||
4
|
||
register
|
||
Z,S,P,CY,AC
|
||
ADDr (AddRegister)
|
||
(A)~(A)+(r)
|
||
Thecontentofregisterrisaddedtothecontentofthe
|
||
accumulator. Theresultisplacedintheaccumulator.
|
||
1IoIooI0ADCM (Addmemory withcarry)
|
||
(A)~(A)+((H)(L))+(CY)
|
||
Thecontent ofthememory location whoseaddressis
|
||
contained intheHandLregisters andthecontent of
|
||
theCYflagareaddedtotheaccumulator. Theresult
|
||
isplacedintheaccumulator.
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:1
|
||
4
|
||
register
|
||
Z,S,P,CY,ACCycles:
|
||
States:
|
||
Addressing:
|
||
Flags:2
|
||
7
|
||
reg.indirect
|
||
Z,S,P,CY,ACo
|
||
ACIdata (Addimmediate withcarry)
|
||
(A)~(A)+(byte2)+(CY)
|
||
Thecontentofthesecondbyteoftheinstruction and
|
||
thecontent oftheCYflagareaddedtothecontents
|
||
oftheaccumulator. Theresultisplacedinthe
|
||
accumulator.
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:ADDM (Addmemory)
|
||
(A)...- (A)+((H)(L))
|
||
Thecontent ofthememory location whoseaddress
|
||
iscontained intheHandLregisters isaddedtothe
|
||
content oftheaccumulator. Theresultisplacedin
|
||
theaccumulator.
|
||
1I0I000 0
|
||
Cycles: 2
|
||
States: 7
|
||
Addressing: reg.indirect
|
||
Flags: Z,S,P,CY,AC1II0o
|
||
data
|
||
2
|
||
7
|
||
immediate
|
||
Z,S,P,CY,ACo
|
||
ADIdata (Addimmediate)
|
||
(A)~(A)+(byte2)
|
||
Thecontent ofthesecondbyteoftheinstruction is
|
||
addedtothecontent oftheaccumulator. Theresult
|
||
isplacedintheaccumulator.
|
||
1I1I0SUBr (Subtract Register)
|
||
(A)~(A)-(r)
|
||
Thecontent ofregister rissubtracted fromthecon
|
||
tentoftheaccumulator. Theresultisplacedinthe
|
||
accumulator.
|
||
data
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:2
|
||
7
|
||
immediate
|
||
Z,S,P,CY,AC
|
||
4-61I0I0 0iSISIS
|
||
Cycles: 1
|
||
States: 4
|
||
Addressing: register
|
||
Flags: Z,S,P,CY,AC
|
||
|
||
===PAGE 51===
|
||
SUBM (Subtract memory)
|
||
(A)~(A)-((H)(L))
|
||
Thecontent ofthememory location whoseaddress is
|
||
contained intheHandLregisters issubtracted from
|
||
thecontent oftheaccumulator. Theresultisplaced
|
||
intheaccumulator.SBIdata (Subtract immediate withborrow)
|
||
(A)~(A)-(byte2)-(CY)
|
||
Thecontents ofthesecondbyteoftheinstruction
|
||
andthecontents oftheCYflagarebothsubtracted
|
||
fromtheaccumulator. Theresultisplacedinthe
|
||
accumulator.
|
||
Cycles:
|
||
States:
|
||
Addressi ng:
|
||
Flags:o
|
||
2
|
||
7
|
||
reg.indirect
|
||
Z,S,P,CY,ACo1II0
|
||
data
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:2
|
||
7
|
||
immediate
|
||
Z,S,P,CY,ACo
|
||
INRr (Increment Register)
|
||
(r)~(r)+1
|
||
Thecontent ofregister risincremented byone.
|
||
Note:Allcondition flagsexceptCYareaffected.SUIdata (Subtract immediate)
|
||
(A)~(A)-(byte2)
|
||
Thecontent ofthesecondbyteoftheinstruction is
|
||
subtracted fromthecontent oftheaccumulator. The
|
||
resultisplacedintheaccumulator.
|
||
o
|
||
data D1r0I0
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:2
|
||
7
|
||
immediate
|
||
Z,S,P,CY,ACCycles:
|
||
States:
|
||
Addressi ng:
|
||
Flags:1
|
||
5
|
||
register
|
||
Z,S,P,AC
|
||
INRM (Increment memory)
|
||
((H)(L))~((H)(L))+1
|
||
Thecontent ofthememory location whoseaddress
|
||
iscontained intheHandLregisters isincremented
|
||
byone.Note:Allcondition flagsexceptCYare
|
||
affected.SBBr (Subtract Register withborrow)
|
||
(A)~(A)-(r)-(CY)
|
||
Thecontent ofregister randthecontent oftheCY
|
||
flagarebothsubtracted fromtheaccumulator. The
|
||
resultisplacedintheaccumulator.
|
||
1I0I0 SISISI
|
||
Cycles: 1
|
||
States: 4
|
||
Addressing: register
|
||
Flags: Z,S,P,CY,ACoI0
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:o
|
||
3
|
||
10
|
||
reg.indirect
|
||
Z,S,P,ACoo
|
||
SBaM (Subtract memory withborrow)
|
||
(A)~(A)-((H)(L))-(CY)
|
||
Thecontent ofthememory location whoseaddress is
|
||
contained intheHandLregisters andthecontent of
|
||
theCYflagarebothsubtracted fromtheaccumula
|
||
tor.Theresultisplacedintheaccumulator.
|
||
1I0,
|
||
01I1I1I0I
|
||
Cycles: 2
|
||
States: 7
|
||
Addressing: reg.indirect
|
||
Flags: Z,S,P,CY,AC
|
||
4-7OCRr (Decrement Register)
|
||
(r)~(r)-1
|
||
Thecontent ofregister risdecremented byone.
|
||
Note:Allcondition flag~exceptCYareaffected.
|
||
0I0IDIDDI1I0I1
|
||
Cycles: 1 .f'
|
||
States: 5
|
||
Addressing: register
|
||
Flags: Z,S,P,AC
|
||
|
||
===PAGE 52===
|
||
OCRM (Decrement memory)
|
||
((H)(L))..-((H)(L))- 1
|
||
Thecontentofthememory locationwhoseaddressis
|
||
contained intheHandLregisters isdecremented by
|
||
one.Note:Allcondition flagsexceptCYareaffected.OAA (Decimal AdjustAccumulator)
|
||
Theeight-bit number intheaccumulator isadjusted
|
||
toformtwofour-bit Binary-Coded-Decimal digitsby
|
||
thefollowing process:
|
||
1.Ifthevalueoftheleastsignificant 4bitsofthe
|
||
accumulator isgreaterthan9oriftheACflag
|
||
isset,6isaddedtotheaccumulator.
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:3
|
||
10
|
||
reg.indirect
|
||
Z,S,P,AC2.Ifthevalueofthemostsignificant 4bitsofthe
|
||
accumulator isnowgreaterthan9,oriftheCY
|
||
flagisset,6isaddedtothemostsignificant 4
|
||
bitsoftheaccumulator.
|
||
NOTE: Allflagsareaffected.
|
||
INXrp (Increment registerpair)
|
||
(rh)(rl)..-(rh)(rl)+1
|
||
Thecontentoftheregisterpairrpisincremented by
|
||
one.Note:Nocondition flagsareaffected.Cycles:
|
||
States:
|
||
Flags:o
|
||
1
|
||
4
|
||
Z,S,P,CY,AC
|
||
OCXrp (Decrement registerpair)
|
||
(rh)(rl)..-(rh)(rl)-1
|
||
Thecontentoftheregisterpairrpisdecremented by
|
||
one.Note:Nocondition flagsareaffected.ANAr (ANDRegister)
|
||
(A)~(A)/\(r)
|
||
Thecontent ofregisterrislogically andedwiththe
|
||
content oftheaccumulator. Theresultisplacedin
|
||
theaccumulator. TheCYflagiscleared.
|
||
S
|
||
1
|
||
4
|
||
register
|
||
Z,S,P,CY,ACaIsIs
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:LogicalGroup:
|
||
Thisgroupofinstructions performs logical(Boolean)
|
||
operations ondatainregisters andmemory andoncondi
|
||
tionflags.
|
||
Unlessindicated otherwise, allinstructions inthis
|
||
groupaffecttheZero,Sign,Parity,Auxiliary Carry,and
|
||
Carryflagsaccording tothestandard rules.
|
||
I11
|
||
5
|
||
register
|
||
none
|
||
I0I
|
||
1
|
||
5
|
||
register
|
||
noneCycles:
|
||
States:
|
||
Addressing:
|
||
Flags:
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:
|
||
DADrp (AddregisterpairtoHandL)
|
||
(H)(L)..-(H)(L)+(rh)(rl)
|
||
Thecontentoftheregisterpairrpisaddedtothe
|
||
content oftheregisterpairHandL.Theresultis
|
||
placedintheregisterpairHandL.Note:Onlythe
|
||
CYflagisaffected. Itissetifthereisacarryoutof
|
||
thedoubleprecision add;otherwise itisreset..ANAM (ANDmemory)
|
||
(A)~(A)/\((H)(L))
|
||
Thecontents ofthememory location whoseaddress
|
||
iscontained intheHandLregisters islogically anded
|
||
withthecontent oftheaccumulator. Theresultis
|
||
placedintheaccumulator. TheCYflagiscleared.
|
||
I0I1aaI1, 1Ia
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:3
|
||
10
|
||
register
|
||
CYCycles:
|
||
States:
|
||
Addressing:
|
||
Flags:2
|
||
7
|
||
reg.indirect
|
||
Z,S,P,CY,AC
|
||
4-8
|
||
|
||
===PAGE 53===
|
||
ANIdata (ANDimmediate)
|
||
(A)~(A)/\(byte2)
|
||
Thecontent ofthesecondbyteoftheinstruction is
|
||
logicaJly andedwiththecontents oftheaccumulator.
|
||
Theresultisplacedintheaccumulator. TheCYand
|
||
ACflagsarecleared.ORAr (ORRegister)
|
||
(A)~(A)V(r)
|
||
Thecontent ofregister risinclusive-OR'd withthe
|
||
content oftheaccumulator. Theresultisplacedin
|
||
theaccumulator. TheCYandACflagsarecleared.
|
||
I1oI0I1I1I0I0II1
|
||
XRAr (Exclusive ORRegister)
|
||
(A)~(A)V(r)
|
||
Thecontent ofregister risexclusive-or'd withthe
|
||
content oftheaccumulator. Theresultisplacedin
|
||
theaccumulator. TheCYandACflagsarecleared.ORAM (ORmemory)
|
||
(A)~(A)V((H)(L))
|
||
Thecontent ofthememory location whoseaddressis
|
||
contained intheHandLregisters isinclusive-OR'd
|
||
withthecontent oftheaccumulator.Theresultis
|
||
placedintheaccumulator. TheCYandACflagsare
|
||
cleared.
|
||
I0I1I1o1
|
||
4
|
||
register
|
||
Z,S,P,CY,AC
|
||
I1Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:
|
||
IaI12
|
||
7
|
||
immediate
|
||
Z,S,P,CY,ACdata
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:1
|
||
4
|
||
register
|
||
Z,S,P,CY,ACCycles:
|
||
States:
|
||
Addressing:
|
||
Flags:2
|
||
7
|
||
reg.indirect
|
||
Z,S,P,CY,AC
|
||
XRAM (Exclusive ORMemory)
|
||
(A)~(A)V((H)(L))
|
||
Thecontent ofthememory location whoseaddress
|
||
iscontained intheHandLregisters isexclusive-O R'd
|
||
withthecontent oftheaccumulator. Theresultis
|
||
placedintheaccumulator. TheCYandACflagsare
|
||
cleared.ORIdata (ORImmediate)
|
||
(A)~(A)V(byte2)
|
||
Thecontent ofthesecondbyteoftheinstruction is
|
||
inclusive-OR'd withthecontent oftheaccumulator.
|
||
Theresultisplacedintheaccumulator. TheCYand
|
||
ACflagsarecleared.
|
||
11
|
||
I0 o I0 data
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:2
|
||
7
|
||
reg.indirect
|
||
Z,S,P,CY,ACCycles:
|
||
States:
|
||
Addressing:
|
||
Flags:2
|
||
7
|
||
immediate
|
||
Z,S,P,CY,AC
|
||
XRIdata (Exclusive ORimmediate)
|
||
(A)~(A)V(byte2)
|
||
Thecontent ofthesecondbyteoftheinstruction is
|
||
exclusive-O R'dwiththecontent oftheaccumulator.
|
||
Theresultisplacedintheaccumulator. TheCYand
|
||
ACflagsarecleared.
|
||
.1~_1_1~ 0__1--..1__'_1_1_1_1_0_
|
||
. dataCMPr (Compare Register)
|
||
(A)(r)
|
||
Thecontent ofregister rissubtracted fromtheac
|
||
cumulator. Theaccumulator remains unchanged. The
|
||
condition flagsaresetasaresultofthesubtraction.
|
||
TheZflagissetto1if(A)=(r).TheCYflagissetto
|
||
1if(A)<(r).
|
||
I0I1
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:2
|
||
7
|
||
immediate
|
||
Z,S,P,CY,ACCycles:
|
||
States:
|
||
Addressing:
|
||
Flags:1
|
||
4
|
||
register
|
||
Z,S,P,CY,AC
|
||
4-9
|
||
|
||
===PAGE 54===
|
||
CPIdata (Compare immediate)
|
||
(A)(byte2)
|
||
Thecontent ofthesecondbyteoftheinstruction is
|
||
subtracted fromtheaccumulator. Thecondition flags
|
||
aresetbytheresultofthesubtraction. TheZflagis
|
||
setto1if(A)=(byte2).TheCYflagissetto1if
|
||
(A)<(byte2).CMPM (Compare memory)
|
||
(A)((H)(L))
|
||
Thecontent ofthememory location whoseaddress
|
||
iscontained intheHandLregisters issubtracted
|
||
fromtheaccumulator. Theaccumulator remains un
|
||
changed. Thecondition flagsaresetasaresultofthe
|
||
subtraction. TheZflagissetto1if(A)=((H)(L)).
|
||
TheCYflagissetto1if(A)<((H)(L)).
|
||
Cycles: 1
|
||
States: 4
|
||
Flags: CY0I0I0I0I,I1I,
|
||
Cycles: 1
|
||
States: 4
|
||
Flags: CY
|
||
oI1I , I , oI0I0I ,RAL (Rotate leftthrough carry)
|
||
(An+,)..-(An);(CY)..-(A7)
|
||
(AO)"- (CY)
|
||
Thecontent oftheaccumulatorisrotated leftone
|
||
position through theCYflag.Theloworderbitisset
|
||
equaltotheCYflagandtheCYflagissettothe
|
||
valueshiftedoutofthehighorderbit.OnlytheCY
|
||
flagisaffected.RRC (Rotate right)
|
||
(An)~(An-,);(A7)~(AO)
|
||
(CY)~(AO)
|
||
Thecontent oftheaccumulatorisrotatedrightone
|
||
position. ThehighorderbitandtheCYflagareboth
|
||
settothevalueshiftedoutoftheloworderbitposi
|
||
tion.OnlytheCYflagisaffected.
|
||
oI
|
||
2
|
||
7
|
||
reg.indirect
|
||
Z,S,P,CY,ACCycles:
|
||
States:
|
||
Addressing:
|
||
Flags:o
|
||
, I, I
|
||
data
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:2
|
||
7
|
||
immediate
|
||
Z,S,P,CY,ACRAR (Rotate rightthrough carry)
|
||
(An)~(An+l);(CY)..- (AO)
|
||
(A7)~(CY)
|
||
Thecontent oftheaccumulator isrotatedrightone
|
||
position through theCYflag.Thehighorderbitisset
|
||
totheCYflagandtheCYflagissettothevalue
|
||
shiftedoutoftheloworderbit.OnlytheCYflagis
|
||
affected.
|
||
Cycles: 1
|
||
States: 4
|
||
Flags: CY
|
||
RLC (Rotate left)
|
||
(An+l)~(An);(AO)~(A7)
|
||
(CY)~(A7)
|
||
Thecontent oftheaccumulator isrotated leftone
|
||
position. TheloworderbitandtheCYflagareboth
|
||
settothevalueshiftedoutofthehighorderbitposi
|
||
tion.OnlytheCYflagisaffected.CMA (Complement accumulator)
|
||
(A)~(A)
|
||
Thecontents oftheaccumulator arecomplemented
|
||
(zerobitsbecome 1,onebitsbecome 0).Noflagsare
|
||
affected.
|
||
oI0I1I0I1I , I ,
|
||
Cycles: 1
|
||
States: 4
|
||
Flags: CYCycles: ,
|
||
States: 4
|
||
Flags: none
|
||
4-10
|
||
|
||
===PAGE 55===
|
||
CMC (Complement carry)
|
||
(CY)~ (CY)
|
||
TheCYflagiscomplemented. Nootherflagsare
|
||
affected.dressisspecified inbyte3andbyte2ofthecurrent
|
||
instruction.
|
||
I1I0I0I0I0I1I1 1
|
||
low-order addr
|
||
high-order addra ,0 ,
|
||
Cycles:
|
||
States:
|
||
Flags:1
|
||
4
|
||
CYCycles:
|
||
States:
|
||
Addressing:
|
||
Flags:3
|
||
10
|
||
immediate
|
||
none
|
||
STC (Setcarry)
|
||
(CY)~1
|
||
TheCYflagissetto1.Nootherflagsareaffected.
|
||
0I0I0I1I1
|
||
Cycles: 1
|
||
States: 4
|
||
Flags: CYJcondition addr (Conditional jump)
|
||
If(CCC),
|
||
(PC)~(byte3)(byte2)
|
||
Ifthespecified condition istrue,control istrans
|
||
ferredtotheinstruction whoseaddressisspecified in
|
||
byte3andbyte2ofthecurrent instruction; other
|
||
wise,controlcontinues sequentially.
|
||
"
|
||
1I1ICICICI0I1I0
|
||
low-order addr
|
||
high-order addr
|
||
BranchGroup:
|
||
Thisgroupofinstructions alternormal sequential
|
||
program flow.
|
||
Condition flagsarenotaffected byanyinstruction
|
||
inthisgroup.
|
||
Thetwotypesofbranchinstructions areuncondi
|
||
tionalandconditional. Unconditional transfers simplyper
|
||
formthespecified operation onregister PC(theprogram
|
||
counter). Conditional transfers examine thestatusofoneof
|
||
thefourprocessor flagstodetermineifthespecified branch
|
||
istobeexecuted. Theconditions thatmaybespecified are
|
||
asfollows:
|
||
~
|
||
1I1I0I0I1T1I0I1
|
||
low-order addr
|
||
high-ord~r addrCALLaddr (Call)
|
||
((SP)-1)~(PCH)
|
||
((SP)-2)~(PCl)
|
||
(SP)~(SP) -2
|
||
(PC)~(byte3)(byte2)
|
||
Thehigh-order eightbitsofthenextinstruction ad
|
||
dressaremovedtothememory location whose
|
||
address isonelessthanthecontent ofregister SP.
|
||
Thelow-order eightbitsofthenextinstruction ad
|
||
dressaremovedtothememory location whose
|
||
address istwolessthanthecontent ofregister SP.
|
||
Thecontent ofregisterSPisdecremented by2.Con
|
||
trolistransferred totheinstruction whoseaddress is
|
||
specified inbyte3andbyte2ofthecurrent
|
||
instruction.3
|
||
10
|
||
immediate
|
||
noneCycles:
|
||
States:
|
||
Addressing:
|
||
Flags:
|
||
CCC
|
||
000
|
||
001
|
||
010
|
||
011
|
||
100
|
||
101
|
||
110
|
||
111NZ-notzero(Z=0)
|
||
2 -zero(2=1)
|
||
NC-nocarry(CY=0)
|
||
C -carry(CY=1)
|
||
PO-parityodd(P=0)
|
||
PE-parityeven(P=1)
|
||
P -plus(S=0)
|
||
M-minus(S=1)CONDITION
|
||
JMPaddr (Jump)
|
||
(PC)~(byte3)(byte2)
|
||
Control istransferred totheinstruction whosead-Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:5
|
||
17
|
||
immediate/reg. indirect
|
||
none
|
||
4-11
|
||
|
||
===PAGE 56===
|
||
Ccondition addr (Condition call)
|
||
If(CCC),
|
||
((SP)-1)~(PCH)
|
||
((SP)-2)~(PCl)
|
||
(SP)~(SP)-2
|
||
(PC)~(byte3)(byte2)
|
||
Ifthespecified condition istrue,theactionsspecified
|
||
intheCAllinstruction (seeabove)areperformed;
|
||
otherwise, controlcontinues sequentially.
|
||
1 '1ICICIcI1IoI0
|
||
low-order addr
|
||
high-order addrRSTn (Restart)
|
||
((SP)-1)~(PCH)
|
||
((SP)-2)~(PCl)
|
||
(SP)~(SP)-2
|
||
(PC)~8*(NNN)
|
||
Thehigh-order eightbitsofthenextinstruction ad
|
||
dressaremovedtothememory location whose
|
||
address isonelessthanthecontent ofregister SP.
|
||
Thelow-order eightbitsofthenextinstruction ad
|
||
dressaremovedtothememory location whose
|
||
address istwolessthanthecontent ofregister SP.
|
||
Thecontent ofregister SPisdecremented bytwo.
|
||
Control istransferred totheinstruction whosead
|
||
dressiseighttimesthecontent ofNNN.
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:3/5
|
||
11/17
|
||
immediate/reg. indirect
|
||
none1I NNINI1I
|
||
3
|
||
11
|
||
reg.indirect
|
||
none
|
||
RET (Return)
|
||
(PCl)~((SP));
|
||
(PCH)~((SP)+1);
|
||
(SP)~(SP)+2;
|
||
Thecontent ofthememory location whoseaddress
|
||
isspecified inregister SPismovedtothelow-order
|
||
eightbitsofregister PC.Thecontent ofthememory
|
||
location whoseaddress isonemorethanthecontent
|
||
ofregister SPismovedtothehigh-order eightbitsof
|
||
register PC.ThecontentofregisterSPisincremented
|
||
by2.Program Counter AfterRestart
|
||
1II0I0
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:3
|
||
10
|
||
reg.indirect
|
||
nonePCHL (JumpHandlindirect -moveHandLtoPC)
|
||
(PCH)~(H)
|
||
(PCl)~(l)
|
||
Thecontent ofregister Hismovedtothehigh-order
|
||
eightbitsofregister PC.Thecontent ofregister lis
|
||
movedtothelow-order eightbitsofregisterPC.
|
||
Rcondition (Conditional return)
|
||
If(CCC),
|
||
(PCl)~((SP))
|
||
(PCH)~((SP)+1)
|
||
(SP)~(SP)+2
|
||
Ifthespecified condition istrue,theactionsspecified
|
||
intheRETinstruction (seeabove)areperformed;
|
||
otherwise, controlcontinues sequentially.1I1Io '
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:o,.0I1
|
||
1
|
||
5
|
||
register
|
||
none
|
||
1IIccIcI0I0I0
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:1/3
|
||
5/11
|
||
reg.indirect
|
||
none
|
||
4-12
|
||
|
||
===PAGE 57===
|
||
Stack,I/O,andMachineControlGroup: FLAGWORD
|
||
Thisgroupofinstructions performs I/O,manipulates
|
||
theStack,andaltersinternalcontrolflags.
|
||
Unlessotherwise specified, condition flagsarenot
|
||
affected byanyinstructions inthisgroup.D1Do
|
||
PUSHrp (Push)
|
||
((SP)-1)~(rh)
|
||
((SP)-2)~(rl)
|
||
(SP)~(SP)-2
|
||
Thecontent ofthehigh-order registerofregisterpair
|
||
rpismovedtothememory location whoseaddress is
|
||
onelessthanthecontent ofregisterSP.Thecontent
|
||
ofthelow-order registerofregister pairrpismoved
|
||
tothememory location whoseaddress istwoless
|
||
thanthecontent ofregisterSP.Thecont~nt ofreg
|
||
isterSPisdecremented by2.Note:Register pair
|
||
rp=SPmaynotbespecified ..POPrp (Pop)
|
||
(rl)~((SP))
|
||
(rh)~((SP)+1)
|
||
(SP)~(SP)+2
|
||
Thecontent ofthememory location, whoseaddress
|
||
isspecified bythecontentofregisterSP,ismovedto
|
||
thelow-order registerofregister pairrp.Thecontent
|
||
ofthememory location, whoseaddress isonemore
|
||
thanthecontent ofregisterSP,ismovedtothehigh
|
||
orderregisterofregister pairrp.Thecontent ofreg
|
||
isterSPisincremented by2.Note:Register pair
|
||
rp=SPmaynotbespecified.
|
||
3
|
||
10
|
||
reg.indirect
|
||
none1I1IRPI0 0
|
||
Cycles: 3
|
||
States: 11
|
||
Addressing: reg.indirect
|
||
Flags: noneI1 P
|
||
Cycles:
|
||
States:
|
||
Addressi ng:
|
||
Flags:oooI1
|
||
PUSHPSW (Pushprocessor statusword)
|
||
((SP)-1)~(A)
|
||
((SP)-2)0..-(CY),((SP)-2)1~1
|
||
((SP)-2)2~(P),((SP)-2)3~0
|
||
((SP)-2)4~(AC),((SP)-2)5~0
|
||
((SP)-2)6..-(Z),((SP)-2)7~(S)
|
||
(SP)~(SP)- 2
|
||
Thecontent ofregister Aismovedtothememory
|
||
location whoseaddress isonelessthanregister SP.
|
||
Thecontents ofthecondition flagsareassembled
|
||
intoaprocessor statuswordandthewordismoved
|
||
tothememory location whoseaddress istwoless
|
||
thanthecontent ofregisterSP.Thecontent ofreg
|
||
isterSPisdecremented bytwo.POPPSW (Popprocessor statusword)
|
||
(CY)~((SP))O
|
||
(P)..-((SP))2
|
||
(AC)~((SP))4
|
||
(Z)~((SP))6
|
||
(S)~((SP))7
|
||
(A)...-((SP)+1)
|
||
(SP)...-(SP)+ 2
|
||
Thecontent ofthememory location whoseaddress
|
||
isspecified bythecontent ofregister SPisusedto
|
||
restorethecondition flags.Thecontent ofthemem
|
||
orylocation whoseaddress isonemorethanthe
|
||
content ofregister SPismovedtoregister A.The
|
||
contentofregisterSPisincremented by2.
|
||
3
|
||
10
|
||
reg.indirect
|
||
Z,S,P,CY,AeoI1
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:I1
|
||
3
|
||
11
|
||
reg.indirect
|
||
noneCycles:
|
||
States:
|
||
Addressing:
|
||
Flags:1I1I
|
||
4-13
|
||
|
||
===PAGE 58===
|
||
XTHL (Exchange stacktopwithHandL)
|
||
(L)~((SP))
|
||
(H)~((SP)+1)
|
||
Thecontent oftheLregisterisexchanged withthe
|
||
content ofthememory location whoseaddress is
|
||
specified bythecontentofregisterSP.Thecontent
|
||
oftheHregisterisexchanged with thecontentofthe
|
||
memory location whoseaddress isonemorethanthe
|
||
contentofregisterSP.EI (Enableinterrupts)
|
||
Theinterrupt systemisenabledfollowing theexecu
|
||
tionofthenextinstruction.
|
||
1I I1,
|
||
0I1I1
|
||
Cycles: 1
|
||
States: 4
|
||
Flags: none
|
||
1I I0oo
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:5
|
||
18
|
||
reg.indirect
|
||
none01 (Disableinterrupts)
|
||
Theinterrupt system isdisabled immediately fol
|
||
lowingtheexecution ofthe01instruction.
|
||
11010'111
|
||
SPHL (MoveHLtoSP)
|
||
(SP)~(H)(L)
|
||
Thecontents ofregistersHandL(16bits)aremoved
|
||
toregisterSP.Cycles: 1
|
||
States: 4
|
||
Flags: none
|
||
INport (Input)
|
||
(A)~(data)
|
||
Thedataplacedontheeightbitbi-directional data
|
||
busbythespecified portismovedtoregisterA.1I1I
|
||
Cycles:
|
||
States:
|
||
Addressing:
|
||
Flags:o
|
||
1
|
||
5
|
||
register
|
||
noneoHLT (Halt)
|
||
Theprocessor isstopped. Theregisters andflagsare
|
||
unaffected.
|
||
0I1I0I1I1I0
|
||
Cycles: 1
|
||
States: 7
|
||
Flags: none
|
||
1II0II1I0I1I1
|
||
portNOP (Noop)
|
||
Nooperation isperformed. Theregisters andflags
|
||
areunaffected.
|
||
Cycles: 3
|
||
States: 10
|
||
Addressing: direct
|
||
Flags: none
|
||
OUTport (Output)
|
||
(data)~(A)
|
||
ThecontentofregisterAisplacedontheeightbit
|
||
bi-directional databusfortransmission tothespec
|
||
ifiedport.0I0I000000
|
||
Cycles: 1
|
||
States: 4
|
||
Flags: none
|
||
o
|
||
porto
|
||
Cycles: 3
|
||
States: 10
|
||
Addressing: direct
|
||
Flags: none
|
||
4-14
|
||
|
||
===PAGE 59===
|
||
INSTRUCTION SET
|
||
Summary ofProcessor Instructions
|
||
Instruction Code[11 Clock121 Instruction Code[11 Clock[21
|
||
Mnemonic Description try06Os0403020,DOCycles Mnemonic Description 0706Os04 03020,DOCycles
|
||
MOVr1,r2Moveregistertoregister 010 00S S S 5 RZ Returnonzero 100'10 0 0 5/11
|
||
MOVM,r Moveregistertomemory 0111 0S SS7 RNZ Returnonnozero 1 0 0 0 0 C05/11
|
||
MOVr,M Movememorytoregister 0 1 0 0 0 1 107 RP Returnonpositive 11 10 0 0 0 5/11
|
||
HlT Halt 01 1 1 01 107 RM Returnonminus 111100 0 5/11
|
||
MVIrMoveimmediate register 0 0 0 001107 RPE Returnonparityeven 11010 0 0 5/11
|
||
MVIM Moveimmediate memory 00110 11010 RPO Returnonparityodd 1 10000 0 5/11
|
||
INRrIncrement register 0 0 00010 0 5 RST Restart 1 A A A 1 1111
|
||
OCRrDecrement register 000 0 010 1 5 IN Input 101101 1 10
|
||
INRMIncrement memory 0 01 1010 0 10 OUT Output 1010 01110
|
||
OCRMDecrement memory 0 0 1 10 1 0 1 10 lXIBloadImmediate register 0 0 0 0 0 0110
|
||
ADOr AddregistertoA 10 0 0 0 S SS4 PairB&C
|
||
AOCr AddregistertoAwithcarry 10 0 0 1 S S S 4 LXI0Loadimmediate register 10
|
||
SUBrSubtractregisterfromA 10010S S S 4 Pair0&E
|
||
SBBrSubtractregisterfromA 10 0 1 1 S SS4 LXIHLoadimmediate register 10
|
||
withborrow PairH&L
|
||
ANArAndregisterwithA 0 S S S 4 lXISPloadimmediate stackpointer 10
|
||
XRArExclusive OrregisterwithA 0 S S S 4 PUSHBPushregisterPairB&Con 11
|
||
OIiAr OrregisterwithA 0 SS S 4 stack
|
||
CMPr CompareregisterwithA 0 S S S 4 PUSH0PushregisterPair0&Eon 11
|
||
ADDMAddmemorytoA 0 1 1 0 7 stack
|
||
AOCMAddmemorytoAwithcarry 0 1 107 PUSHHPushregisterPairH&lon 11
|
||
SUBMSubtractmemoryfromA 0 1 107 stack
|
||
SBBMSubtractmemoryfromA 0 1 107 PUSHPSWPushAandFlags 11
|
||
withborrow onstack
|
||
ANAMAndmemorywithA 0 00 POPBPopregisterpairB&Coff 10
|
||
XRAMExclusive OrmemorywithA 0 0 1 stack
|
||
ORAMOrmemorywithA 0 1 0 POP0Popregisterpair0&Eoff 10
|
||
CMPM ComparememorywithA 0 1 1 stack
|
||
AOI Addimmediate toA 1 0 0 POPHPopregisterpairH&Loff 10
|
||
ACI Addimmediate toAwith 1 01 stack
|
||
carry POPPSWPopAandFlags 10
|
||
SUI Subtractimmediate fromA offstack
|
||
SBI Subtractimmediate fromA STA StoreAdirect 13
|
||
withborrow lOA LoadAdirect 13
|
||
ANI Andimmediate withA XCHG Exchange 0&E,H&L 4
|
||
XRI Exclusive Orimmediate with Registers
|
||
A XTHl Exchange topofstack,H&l1110 0 0 1118
|
||
ORI Orimmediate withA 1 0 SPHL H&Ltostackpointer 1 1 1 1 100 1 5
|
||
CPI Compareimmediate withA1 1 PCHL H&Ltoprogramcounter 111010 0 1 5
|
||
RLC RotateAleft 0 0 DADBAddB&CtoH&L 0 0 0 0 1 0 0110
|
||
RRC RotateAright 0 1 DAD0Add0&EtoH&L l:'0 0 1 100110RAl RotateAleftthroughcarry 0 0 DADHAddH&LtoH&L 001010 0 1 10
|
||
RAR RotateArightthrough 0 1 DADSPAddstackpointertoH&L00 1 1 10 0110carrySTAXBStoreAindirect 0 0 0 000107JMP Jumpunconditional 00 0 0 1 1 10 STAX0StoreAindirect 0 0 0 1 00 10 7JC Jumponcarry 01 10 1 0 10 LOAXBloadAindirect 0 0 0 0 1 0 1 0 7JNC Jumponnocarry 01 001 0 10 lOAX0LoadAindirect 0001101 0 7JZ Jumponzero 0 0 101010 INXBIncrement B&Cregisters 0 00 000115JNZ Jumponnozero 0 0 001010 INX0Increment 0&Eregisters 00 0 1 0 0115JP Jumponpositive 11001010 INXHIncrement H&Lregisters 0 0 10 00 115JM Jumponminus 11101010 INXSPIncrement stackpointer 0 0 1 1 0 0 1 1 5JPE Jumponparityeven 10101010 DCXBDecrement B&C 00 0 0 10115JPO Jumponparityodd 10 001010 DCX0Decrement 0&E 0 0 01 10 115CALL Callunconditional 0 0 1 10117 DCXHDecrement H&L 001010115CC Calloncarry 01 110 0 11/17 DCXSPDecrement stackpointer 0 0 1 1 10 1 1 5CNC Callonnocarry 01 0 1 0011/17 CMA Complement A 0010111 1 4CZ Callonzero 0 0 1 1 0 0 11/17 STC Setcarry 00 1 101114CNZ Call0nnozero 00010011/17 CMC Complement carry 0 0 1 1 1 1 114CP Callonpositive 1 1 010011/17 OAA DecimaladjustA 0 0 1 001 114CM Callonminus 11 110 0 11/17 SHlD StoreH&ldirect 0 0 1 0001016CPE Callonparityeven 101 10011/17 LHLO loadH&Ldirect 0010 1 0 1 016CPO Callonparityodd 1 0 010011/17 EI EnableInterrupts 111 110114RET Return 00100110 01 Disableinterrupt 1 1 1 10 0 1 14
|
||
RC Returnoncarry 01 10005/11 NOP No-operation 0000 000 0 4RNC Returnonnocarry 0 1 00005/11
|
||
NOTES: 1.DDDorSSS-000B -001C-010D -011E -100H -101L -110Memory -111A.
|
||
2.Twopossiblecycletimes,(5/11)indicate instruction cyclesdependent oncondition flags.
|
||
4-15
|
||
|
||
===PAGE 60===
|
||
CPUGroup
|
||
8224ClockGenerator 5-1
|
||
8228SystemController . . . . . . . . . . . . . . . . . . . . . . . 5-7
|
||
8080ACentralProcessor 5-13
|
||
8080A-1 CentralProcessor (1.3#ls)••..•.••.••.••.• 5-20
|
||
8080A-2 CentralProcessor (1.5#ls)•...•..•..•.••.. 5-24
|
||
MBOBOA CentralProcessor (_55°to+125°C) 5-29
|
||
ROMs
|
||
8702AErasablePROM(256x8). . . . . . . . . . . . . . . . . 5-37
|
||
8708/8704 ErasablePROM(1Kx8). . . . . . . . . . . . . . . 5-45
|
||
8302MaskROM(256x8) 5-51
|
||
8308MaskROM(1Kx8). . . . . . . . . . . . . . . . . . . . . . 5-59
|
||
8316AMaskROM(2Kx8). . . . . . . . . . . . . . . . . . . . . 5-61
|
||
RAMs
|
||
8101-2StaticRAM(256x4) 5-67
|
||
8111-2StaticRAM(256x4) 5-71
|
||
8102-2StaticRAM(1Kx1). . . . . . . . . . . . . . . . . . . . 5-75
|
||
8102A-4 StaticRAM(1Kx1). . . . . . . . . . . . . . . . . . . 5-79
|
||
81078-4 Dynamic RAM(4Kx1). . . . . . . . . . . . . . . . . 5-83
|
||
5101StaticCMOSRAM(256x4). . . . . . . . . . . . . . . . 5-91
|
||
8210Dynamic RAMDriver.. . . . . . . . . . . . . . . . . . . . 5-95
|
||
8222Dynamic RAMRefreshController 5-99
|
||
I/O
|
||
82128-BitI/OPort. . . . . . . . . . . . . . . . . . . . . . . . . . 5-101
|
||
8255Programmable Peripheral Interface . . .5-113
|
||
8251Programmable Communication Interface. . . . . . . . 5-135
|
||
Peripherals
|
||
8205OneofEightDecoder . . . . . . . . . . . . . . . . . . . . . 5-147
|
||
8214PriorityInterrupt ControlUnit 5-153
|
||
8216/8226 4-8itBi-Directional BusDriver. . . . . . . . . . . 5-163
|
||
ComingSoon
|
||
8253Programmable IntervalTimer.. . . . . . . . . . . . . . . 5-169
|
||
8257Programmable DMAController 5-171
|
||
8259Programmable InterruptController . . . . . . . . . . . . 5-173
|
||
|
||
===PAGE 61===
|
||
8224
|
||
8228
|
||
8080ACPUGroup
|
||
8080A-1
|
||
8080A-2
|
||
M8080-A
|
||
|
||
===PAGE 62===
|
||
|
||
|
||
===PAGE 63===
|
||
SchottkyBipolar8224
|
||
CLOCKGENERATOR ANDDRIVER
|
||
FOR8080ACPU
|
||
•SingleChipClockGenerator/Driver
|
||
for8080ACPU
|
||
•Power-Up ResetforCPU
|
||
•ReadySynchronizing Flip-Flop
|
||
•Advanced StatusStrobe•Oscillator OutputforExternal
|
||
SystemTiming
|
||
•C.rystalControlled forStableSystem
|
||
Operation
|
||
•Reduces SystemPackage Count
|
||
The8224isasinglechipclockgenerator/driver forthe8080ACPU.Itiscontrolled byacrystal,selectedby
|
||
thedesigner,tomeetavarietyofsystemspeedrequirements.
|
||
Alsoincluded arecircuitstoprovidepower-up reset,advancestatusstrobeandsynchronization ofready.
|
||
The8224provides thedesignerwithasignificant reduction ofpackages usedtogenerate clocksandtiming
|
||
for8080A.
|
||
PINNAMES
|
||
RESIN RESETINPUT
|
||
RESET RESETOUTPUT
|
||
RDYIN READYINPUT
|
||
READY READYOUTPUT
|
||
SYNC SYNCINPUT
|
||
STSTB STATUSSTB
|
||
(ACTIVE lOW)
|
||
rPl!8080
|
||
rP2 CLOCKSXTAl1ICONNECTIONS
|
||
XTAl2 FORCRYSTAL
|
||
TANK USEDWITHOVERTONE XTAL
|
||
OSC OSCILLATOR OUTPUT
|
||
rP2(TTL) rP2elK(TTLlEVEL)
|
||
Vee +5V
|
||
Voo +12V
|
||
GND OV
|
||
5-1
|
||
|
||
===PAGE 64===
|
||
SCHOTTKY BIPOLAR 8224
|
||
FUNCTIONAL DESCRIPTION
|
||
General
|
||
The8224isasinglechipClockGenerator/Driver forthe
|
||
S080ACPU.Itcontains acrystal-controlled oscillator, a
|
||
"dividebynine"counter, twohigh-level driversandseveral
|
||
auxiliary logicfunctions.
|
||
Oscillator
|
||
Theoscillator circuitderivesitsbasicoperating frequency
|
||
fromanexternal, seriesresonant, fundamental modecrystal.
|
||
Twoinputsareprovided forthecrystalconnections (XTAL1,
|
||
XTAL2).
|
||
Theselection oftheexternal crystalfrequency depends
|
||
mainlyonthespeedatwhichthe8080Aistoberunat.
|
||
Basically, theoscillator operates at9timesthedesiredpro
|
||
cessorspeed.
|
||
Asimpleformulatoguidethecrystalselection is:
|
||
CrystalFrequency =-'-times9
|
||
tCY
|
||
Example' :(500nstCY)
|
||
2mHztimes9=18mHz*
|
||
Example 2:(800nstCY)
|
||
'.25mHz times9='1.25mHz
|
||
Another inputtotheoscillator isTANK.Thisinputallows
|
||
theuseovertone modecrystals. Thistypeofcrystalgen
|
||
erallyhasmuchlowerIIgain"thanthefundamental typeso
|
||
anexternal LCnetwork isnecessary toprovidetheadditional
|
||
"gain"forproperoscillator operation. Theexternal LCnet
|
||
workisconnected totheTANKinputandisACcoupledto
|
||
ground.SeeFigure4.
|
||
Theformula fortheLCnetwork is:
|
||
F=__l__
|
||
21TVLCThewaveforms generated bythedecodegatingfollowa
|
||
simple2-5-2digitalpattern. SeeFigure2.Theclocksgen
|
||
erated;phase1andphase2,canbestbethoughtofascon
|
||
sistingof"units"basedontheoscillator frequency. Assume
|
||
thatone"unit"equalstheperiodoftheoscillator frequency.
|
||
Bymultiplying thenumberof"units"thatarecontained in
|
||
apulsewidthordelay,timestheperiodoftheoscillator fre
|
||
quency,theapproximate timeinnanoseconds canbederived.
|
||
Theoutputs oftheclockgenerator areconnected totwo
|
||
highleveldriversfordirectinterface tothe80S0ACPU.A
|
||
TTLlevelphase2isalsobroughtoutct>2(TTL)forexternal
|
||
timingpurposes. Itis'especially usefulinDMAdependant
|
||
activities. Thissignalisusedtogatetherequesting deviceon
|
||
tothebusoncethe8080ACPUissuestheHoldAck
|
||
nowledgement (HLOA).
|
||
Severalothersignalsarealsogenerated internally sothat
|
||
optimum timingoftheauxiliary flip-flops andstatusstrobe
|
||
(STSTB) isachieved.
|
||
Theoutputoftheoscillator isbuffered andbrought out
|
||
onElSC(pin12)sothatothersystemtimingsignalscanbe
|
||
derivedfromthisstable,crystal-controlled source.
|
||
*Whenusingcrystalsabove10mHzasmallamountoffrequency
|
||
"trimming" maybenecessary toproduce theexactdesiredfre
|
||
quency.Theaddition ofasmallselectedcapacitance (3pF-10pF)
|
||
inserieswiththecrystalwillaccomplish thisfunction.4>,1UNIT=o~c.
|
||
FREQ.
|
||
ClockGenerator
|
||
TheClockGenerator consists ofasynchronous IIdivideby
|
||
nine"counter andtheassociated decodegatingtocreatethe
|
||
waveforms ofthetwo8080Aclocksandauxiliary timing
|
||
signals.
|
||
5-2EXAMPLE: (8080tCY=500ns)
|
||
OSC=18mHz/55ns
|
||
4>1=110ns(2x55ns)
|
||
cP2=275ns(5x55ns)
|
||
4>2-4>,=110ns(2x55ns)
|
||
|
||
===PAGE 65===
|
||
SCHOTTKY BIPOLAR 8224
|
||
STSTB(StatusStrobe)
|
||
Atthebeginning ofeachmachine cycletheaOaOACPUis
|
||
suesstatusinformation onitsdatabus.Thisinformation
|
||
tellswhattypeofactionwilltakeplaceduringthatmachine
|
||
cycle.Bybringing intheSYNCsignalfromtheCPU,and
|
||
gatingitwithaninternal timingsignal(<1>1A),anactivelow
|
||
strobecanbederivedthatoccursatthestartofeachma
|
||
chinecycleattheearliestpossible moment thatstatusdata
|
||
isstableonthebus.TheSTSTBsignalconnects directlyto
|
||
the8228SystemController.
|
||
Thepower-on R-esetalsogenerates STSTB, butofcourse,
|
||
foralongerperiodoftime.Thisfeatureallowsthe8228to
|
||
beautomatically resetwithout additional pinsdevoted for
|
||
thisfunction.TheREADY inputtothe8080ACPUhascertaintiming
|
||
specifications suchas"set-up andhold"thus,anexternal
|
||
synchronizing flip-flop isrequired. The8224hasthisfeature
|
||
built-in.TheROYINinputpresents theasynchronous "wait
|
||
request" tothe"0"typeflip-flop. Byclocking theflip-flop
|
||
with<1>20,asynchronized READY signalatthecorrectin
|
||
putlevel,canbeconnected directlytothea080A.
|
||
Thereasonforrequiringanexternal flip-flop tosynchro
|
||
nizethe"waitrequest" ratherthaninternally inthe8080
|
||
CPUisthatduetotherelatively longdelaysofMOSlogic
|
||
suchanimplementation would"rob"thedesigner ofabout
|
||
200nsduringthetimehislogicisdetermining ifa"wait"
|
||
isnecessary. Anexternal bipolarcircuitbuiltintotheclock
|
||
generator eliminates mostofthisdelayandhasnoeffecton
|
||
component count.
|
||
'912
|
||
5
|
||
"----- STSTB(TO8228PIN1)°1r --,3.10pFI I (ONLVNEEDEDL__.JABOVE10MHz)
|
||
1314 15
|
||
1122
|
||
1015
|
||
423
|
||
82246
|
||
312
|
||
T
|
||
GNDOSC
|
||
<fJ2(TTL)
|
||
GND,------....,
|
||
1
|
||
I
|
||
I
|
||
I
|
||
1:11-=
|
||
I
|
||
ILn7--
|
||
F=-'
|
||
21rJLC
|
||
USEDONLV
|
||
FOROVERTONE
|
||
CRYSTALSAnexternal RCnetwork isconnected totheRESINinput.
|
||
Theslowtransition ofthepowersupplyriseissensedbyan
|
||
internalSchmittTrigger.Thiscircuit converts theslowtrans
|
||
itionintoaclean,fastedgewhenitsinputlevelreachesa
|
||
predetermined value.TheoutputoftheSchmitt Trigger is
|
||
connected toa"0"typeflip-flop thatisclocked with<1>20
|
||
(aninternal timingsignal).Theflip-flop issynchronously
|
||
resetandanactivehighlevelthatcomplies withtheaOaOA
|
||
inputspecisgenerated. FormanualswitchtypesystemRe
|
||
setcircuits, anactivelowswitchclosingcanbeconnected
|
||
totheRESINinputinaddition tothepower-on RCnet
|
||
network.Power-On ResetandReadyFlip-Flops
|
||
Acommon function ina080AMicrocomputer systems isthe
|
||
generation ofanautomatic systemresetandstart-up upon
|
||
initialpower-on. The8224hasabuiltinfeaturetoaccomp
|
||
lishthisfeature.
|
||
5-3
|
||
|
||
===PAGE 66===
|
||
SCHOTTKY BIPOLAR 8224
|
||
D.C.Characteristics
|
||
TA=O°Cto70°C;Vee=+5.0V±5%;Voo=+12V±5%.
|
||
Limits
|
||
Symbol Parameter Min. Typ. Max. Units TestConditions
|
||
IF InputCurrentLoading -.25 rnA VF=.45V
|
||
IR InputLeakageCurrent 10 J.lA VR=5.25V
|
||
Ve InputForwardClampVoltage 1.0 V 'e=-5mA
|
||
VIL Input"Low"Voltage .8 V Vee=5.0V
|
||
VIH Input"High"Voltage 2.6 V ResetInput
|
||
2.0 AllOtherInputs
|
||
VIH-VIL REDINInputHysteresis .25 mV Vee=5.0V
|
||
VOL Output"Low"Voltage .45 V (if>1,if>2),Ready,Reset,STSTB
|
||
IOl=2.5mA
|
||
.45 V AllOtherOutputs
|
||
IOl=15mA
|
||
VOH Output"High"Voltage
|
||
if>1,if>2 9.4 V IOH=-100J.lA
|
||
READY, RESET 3.6 V IOH=-1o0J.lA
|
||
AllOtherOutputs 2.4 V IOH=-lmA
|
||
Ise[1] OutputShortCircuitCurrent -10 -60 rnA Vo=OV
|
||
(AllLowVoltageOutputsOnly) Vee=5.0V
|
||
Icc PowerSupplyCurrent 115 rnA
|
||
100 PowerSupplyCurrent 12 rnA
|
||
Note:1.Caution, cP1andcP2outputdriversdonothaveshortcircuitprotection
|
||
CRYSTAL REQUIREMENTS
|
||
Tolerance: .005%atO°C-70°C
|
||
Resonance: Series(Fundamental) *
|
||
LoadCapacitance: 20-35pF
|
||
Equivalent Resistance: 75-20ohms
|
||
PowerDissipation (Min):4mW
|
||
*Withtankcircuituse3rdovertone mode.
|
||
5-4
|
||
|
||
===PAGE 67===
|
||
SCHOTTKY BIPOLAR 8224
|
||
A.C.Characteristics
|
||
vcc=+5.0V±5%;Voo=+12.0V±5%;TA=O°Cto70°C
|
||
Limits Test
|
||
Symbol Parameter Min. Typ. Max. Units Conditions
|
||
tq,1 cP1PulseWidth2tcy--20ns9
|
||
t</>2 cP2PulseWidth5tcy_35ns
|
||
9
|
||
t01 cP1tocP2Delay 0 ns
|
||
t02 cP2tocP1Delay2tcyCL=20pFto50pF --14ns9
|
||
t03 cP1tocP2Delay2tcy2tcy+20ns
|
||
9 9
|
||
tR cP1andcP2RiseTime 20
|
||
tF cP1andcP2FallTime 20
|
||
to</>2 cP2tocP2(TTL)Delay -5 +15 ns cP2TTl,Cl=30
|
||
R1=300Q
|
||
R2=600Q
|
||
toss cP2toSTSTBDelay6tcy_30ns 6tcy
|
||
9 9
|
||
tpw STSTBPulseWidth tcy_15ns STSTB,Cl=15pF
|
||
9 R1=2K
|
||
tORSRDYINSetupTimeto 50ns_4tcyR2=4K
|
||
StatusStrobe 9
|
||
tORHRDYINHoldTime 4tcy
|
||
AfterSTSTB 9
|
||
tORRDYINorRESINto 4tcy_25ns Ready&Reset
|
||
cP2Delay 9 Cl=10pF
|
||
R1=2K
|
||
R2=4K
|
||
tCLK ClKPeriodtcy
|
||
9
|
||
fmaxMaximum Oscillating27 MHzFrequency
|
||
Cin InputCapacitance 8 pFVcC=+5.0V
|
||
Voo=+12V
|
||
VBIAS=2.5V
|
||
f=1MHz
|
||
INPUT>---......---- ....
|
||
GND
|
||
5-5
|
||
|
||
===PAGE 68===
|
||
SCHOTTKY BIPOLAR 8224
|
||
WAVEFORMS
|
||
.........----to2-----..r1'4------t</l2---~~-------------tey---------------.I
|
||
<l>2fTTL)
|
||
SYNC
|
||
(FROM8080A)
|
||
RDYINORRESIN~--------toss-------.....-----
|
||
t..-----tORH------.t
|
||
READYOUT
|
||
RESETOUT
|
||
VOLTAGE MEASUREMENT POINTS: cP1,cP2Logic"0"=1.0V,Logic"1"=8.0V.Allothersignalsmeasured at1.5V.
|
||
EXAMPLE:
|
||
A.C.Characteristics (FortCY=488.28ns)
|
||
TA=O°Cto70°C;Voo=+qV±5%;Voo=+12V±5%.
|
||
Limits
|
||
Symbol Parameter Min. Typ. Max. Units TestConditions
|
||
Q>1PuIseWidth-tcy=488.28ns~1 89 ns
|
||
t4>2 Q>2PulseWidth 236 ns
|
||
t01 Delay4>1to4>2 0 ns
|
||
t02 Delay4>2to4>1 95 ns_Q>1&Q>2Loadedto
|
||
t03 Delay4>,to4>2LeadingEdges 109 129 nsCL=20to50pF
|
||
tr OutputRiseTime 20 ns
|
||
tf OutputFallTime 20 ns-
|
||
toss Q>2toSTSTBDelay 296 326 ns
|
||
tOcP2' 4>2to4>2(TTL)Delay -5 +15 ns
|
||
tpw StatusStrobePuIseWidth 40 nsReady&ResetLoaded
|
||
tORS RDYINSetupTimeto STSTB -167 ns to2mA/10pF
|
||
tORH RDYINHoldTimeafterSTSTB 217 ns Allmeasurements
|
||
READYorRESET 192 nsreferenced to1.5VtORunlessspecifiedtoQ>2Delayotherwise.
|
||
fMAX Oscillator Frequency 18.432.MHz
|
||
5-6
|
||
|
||
===PAGE 69===
|
||
Schottky Bipolar8228
|
||
SYSTEM CONTROLLER ANDBUSDRIVER
|
||
FOR8080ACPU
|
||
•Sing.leChipSystemControlfor
|
||
MCS:SO Systems
|
||
•Built-inBi-Directional BusDriver
|
||
forDataBusIsolation
|
||
•AllowstheuseofMultipleByte
|
||
Instructions (e.g.CAL:L)for
|
||
Interrupt Acknowledge•UserSelected SingleLeve,1Interrupt
|
||
Vector(RST7)
|
||
•28PinDualIn-LinePackage
|
||
•Reduces SystemPackage Count
|
||
The8228isasinglechipsystemcontroller andbusdriverforMCS-80.Itgenerates allsignalsrequiredto
|
||
directlyinterface MCS-80familyRAM,ROM,andI/Ocomponents.
|
||
Abi-directional busdriverisincludedtoprovidehighsystemTTLfan-out.Italsoprovides isolationofthe
|
||
8080databusfrommemory andI/O.Thisallowsfortheoptimization ofcontrolsignals,enabling thesys
|
||
temsdeisgnertouseslowermemory andI/O.Theisolationofthebusdriveralsoprovidesforenhanced
|
||
systemnoiseimmunity.
|
||
Auserselectedsinglelevelinterrupt vector(RST7)isprovidedtosimplifyrealtime,interrupt driven,small
|
||
systemrequirements. The8228alsogenerates thecorrectcontrolsignalstoallowtheuseofmultiple byte
|
||
instructions (e.g.,CALL)inresponse toanINTERRUPT ACKNOWLEDGE bythe8080A.Thisfeature
|
||
permitslarge,interrupt drivensystemstohaveanunlimited numberofinterrupt levels.
|
||
The8228isdesigned tosupportawidevarietyofsystembusstructures andalsoreducesystempackage
|
||
countforcosteffective, reliable,designoftheMCS-80 systems.
|
||
STSTB~----------
|
||
DBIN-.0--------------1
|
||
WR-.0-------------011
|
||
HLDA~-------------ISYSTEM OATABUS
|
||
DRIVER CONTROL8228BLOCKDIAGRAM
|
||
BI·DIRECTIONAL
|
||
BUSDRIVERPINCONFIGURATION
|
||
STSTB Vee
|
||
HLDA I/OW CPU
|
||
MEMWDATA
|
||
WR BUS
|
||
OBIN IIOR
|
||
OB4 MEMR
|
||
04 INTA
|
||
OB7 BUSEN
|
||
07 06
|
||
OB3 OB6
|
||
03 05
|
||
DB2 DBS
|
||
02 01
|
||
DB~ OB1
|
||
GND 0'
|
||
PINNAMES
|
||
07·00 DATABUS(8080SIDE)
|
||
OB7·DBO DATABUS(SYSTEM SIDE)
|
||
IIOR 1/0READ
|
||
I!OW 1/0WRITE
|
||
MEMR MEMORY READ
|
||
MEMW MEMORY WRITE
|
||
DBIN DBIN(FROM8080)INTA INTERRUPT ACKNOWLEDGE
|
||
HLOA HLDA(FROM8080)
|
||
WR WR(FROM8080)
|
||
BUSEN BUSENABLE INPUT
|
||
STSTB STATUS STROBE (FROM8224)
|
||
Vee +5V
|
||
GNDaVOLTS
|
||
5-7
|
||
|
||
===PAGE 70===
|
||
SCHOTTKY BIPOLAR 8228
|
||
FUNCTIONAL DESCRIPTION
|
||
General
|
||
The8228isasinglechipSystemController andDataBus
|
||
driverforthe8080Microcomputer System. Itgenerates all
|
||
controlsignalsrequiredtodirectlyinterface MCS-80™ family
|
||
RAM,ROM,andI/Ocomponents.
|
||
Schottky Bipolartechnology isusedtomaintain lowdelay
|
||
timesandprovide highoutputdrivecapability tosupport
|
||
smalltomedium systems.
|
||
Bi-Directional BusDriver
|
||
Aneightbit,bi-directional busdriverisprovided tobuffer
|
||
the8080databusfromMemory andI/Odevices.The8080A
|
||
databushasaninputrequirement of3.3volts(min)and
|
||
candrive(sink)amaximum currentof1.9mA.The8228
|
||
databusdriverassuresthattheseinputrequirements will
|
||
benotonlymetbutexceeded forenhanced noiseimmunity.
|
||
Also,onthesystemsideofthedriveradequate drivecur
|
||
rentisavailable (10mATyp.)sothatalargenumberof
|
||
Memory andI/Odevicescanbedirectly connected tothe
|
||
bus.
|
||
TheBi-Directional BusDriveriscontrolled bysignal~from
|
||
theGatingArraysothatproperbusflowismaintained and
|
||
itsoutputs canbeforcedintotheirhighimpedance state
|
||
(3-state) forDMAactivities.
|
||
StatusLatch
|
||
Atthebeginning ofeachmachine cyclethe8080CPUissues
|
||
"status" information onitsdatabusthatindicates thetype
|
||
ofactivitythatwilloccurduringthecycle.The8228stores
|
||
thisinformation intheStatusLatchwhentheSTSTBinput
|
||
goes"low".TheoutputoftheStatusLatchisconnected to
|
||
theGatingArrayandispartoftheControlSignalgeneration.GatingArray
|
||
TheGatingArraygenerates controlsignals(MEMR,MEMW,
|
||
I/OR,I/OWandINTA)bygatingtheoutputsoftheStatus
|
||
Latchwithsignalsfromthe8080CPU(DBIN,WR,and
|
||
HLDA).
|
||
The"read"controlsignals(MEMR,I/ORandINTA)are
|
||
derived fromthelogicalcombination oftheappropriate
|
||
StatusBit(orbits)andtheDBINinputfromthe8080CPU.
|
||
The"write" controlsignals(MEMW,I/OW)arederived
|
||
fromthelogicalcombination oftheappropriate StatusBit
|
||
(orbits)andtheWRinputfromthe8080CPU.
|
||
AllControl Signalsare"activelow"anddirectly interface
|
||
toMCS-80 familyRAM,ROMandI/Ocomponents.
|
||
TheINTAcontrolsignalisnormally usedtogatethe"inter
|
||
ruptinstruction port"ontothebus.Italsoprovides a
|
||
specialfeatureinthe8228.Ifonlyonebasicvectorisneed
|
||
edintheinterrupt structure, suchasinsmallsystems, the
|
||
8228canautomatically insertaRST7instruction ontothe
|
||
busatthepropertime.Tousethisoption,simplyconnect
|
||
theINTAoutputofthe8228(pin23)tothe+12volt
|
||
supplythrough aseriesresistor (1Kohms).Thevoltageis
|
||
sensedinternally bythe8228andlogicis"set-up" sothat
|
||
whentheDBINinputisactiveaRST7instruction isgated
|
||
ontothebuswhenaninterrupt isacknowledged. This
|
||
featureprovides asingleinterrupt vectorwithnoadditional
|
||
components, suchasaninterrupt instruction port.
|
||
WhenusingCALLasanInterrupt instruction the8228
|
||
willgenerate anINTApulseforeachofthethreebytes.
|
||
TheBUSEN (BusEnable) inputtotheGatingArrayisan
|
||
asynchronous inputthatforcesthedatabusoutputbuffers
|
||
andcontrolsignalbuffersintotheirhigh-impedance state
|
||
ifitisa"one".IfBUSEN isa"zero"normaloperation of
|
||
thedatabufferandcontrolsignalstakeplace.
|
||
SYSTEM DATABUSCPU
|
||
DATA
|
||
BUS8228BLOCKDIAGRAM
|
||
BI-OIRECTIONAL
|
||
BUSDRIVER
|
||
DRIVER CONTROL
|
||
STSTB----. --J
|
||
DBIN----.-------------41
|
||
WR--.-------------011
|
||
HLDA----.--------------1
|
||
5-8GATING
|
||
ARRAY
|
||
|
||
===PAGE 71===
|
||
SCHOTTKY BIPOLAR 8228
|
||
DATABUS
|
||
INTA
|
||
MEMR
|
||
MEMWCONTROL BUS
|
||
I/OR
|
||
I/OW3
|
||
CONTROL
|
||
BUSEN__....22a_18WRn-------.....,
|
||
DBINt-=-1.:....7----..-----,
|
||
HDLA ~2;.;.1~_--.
|
||
8080A °O~10~~-I
|
||
CPU 011-9--l~-I
|
||
°2~8--l~~ .....
|
||
031-7--l~-I
|
||
041-3--l~-I
|
||
°51-4--l~-I
|
||
06.-5--l~~-I
|
||
07.-6--l~~-I...._-----
|
||
(FROM8224)STATUSSTROBE--...c1II
|
||
STATUS WORDCHART
|
||
TYPEOFMACHINE CYCLE
|
||
I
|
||
STATUS WORD
|
||
DOINTAo0 0 0 0 0 0 1 0 1
|
||
WO
|
||
STACK
|
||
HLTA
|
||
OUT1 1 0 1 0 1 0 1 1 1
|
||
o0 0 1 1 0 0 0 0 0
|
||
o0 0 0 0 0 0 0 1 1
|
||
o0 0 0 0 0 1 0 0 0
|
||
05
|
||
INP1 0 0 0 0 0 0 1 0 1
|
||
o0 0 0 0 1 0 0 0 0
|
||
MEMR 1 1 0 1 0 0 0 0 1 0
|
||
---INTA
|
||
L..-- (NONE)
|
||
INTA
|
||
~------ I/OW
|
||
'------------ I/OR
|
||
'-------------- MEMW
|
||
L...-- MEMR
|
||
'------------------ MEMW
|
||
L....- MEMR
|
||
'-------------------- MEMR_CONTROL
|
||
SIGNALS
|
||
5-9
|
||
|
||
===PAGE 72===
|
||
SCHOTTKY BIPOLAR 8228
|
||
WAVEFORMS
|
||
DBINSTATUS STROBE
|
||
INTA,lOR,MEMR
|
||
DURING HLDAHLDA--------+----+-----'18080DATABUS
|
||
-----...".I'~~+--,.,.I"--------------------
|
||
lOWORMEMW8080BUSDURING READ·- - - - - - - - -
|
||
8080BUSDURING WRITESYSTEM BUSDURING READ
|
||
SYSTEM BUSDURING WRITE- - - - - - - - - <~
|
||
we1=
|
||
SYSTEM BUSENABLE. j1
|
||
.-tE~r
|
||
SYSTEM BUSOUTPUTS - - - - - - - - - - - - - - - <t-- > - - - - - - - - - - - - - -
|
||
VOLTAGE MEASUREMENT POINTS: 00-07(whenoutputs) Logic"0"=0.8V,Logic"1"=3.0V.Allothersignalsmeasured
|
||
at1.5V.
|
||
A.C.Characteristics TA=O°cto70°C;Vee=5V±5%.
|
||
Limits
|
||
Symbol Parameter Min.Max.Units Condition
|
||
tpw WidthofStatusStrobe 22 ns
|
||
tss SetupTime,StatusInputsDo-D7 8 ns
|
||
tSH HoldTime,StatusInputsDo-D7 5 ns
|
||
toe DelayfromSTSTBtoanyControlSignal 2060nsCL=100pF
|
||
tRR DelayfromDBINtoControlOutputs 30nsCL=100pF
|
||
tRE DelayfromDBINtoEnable/Disable 8080Bus 45nsCL=25pF
|
||
tAD DelayfromSystemBus·to8080BusduringRead 30nsCL=25pF
|
||
tWA DelayfromWRtoControlOutputs 545nsCL=100pF
|
||
tWE DelaytoEnableSystemBusDBo-DB7 afterSTSTB 30nsCL=100pF
|
||
two Delayfrom8080BusDo-D7toSystemBus nsCL=100pF
|
||
DBo-DB7 duringWrite 540
|
||
tE DelayfromSystemBusEnabletoSystemBusDBo-DB7 30nsCL=100pF
|
||
tHO HLDAtoReadStatusOutputs 25ns
|
||
tos SetupTime,SystemBusInputstoHLDA 10 ns
|
||
tOH HoldTime,SystemBusInputstoHLDA 20\nsCL=100pF
|
||
5-10
|
||
|
||
===PAGE 73===
|
||
SCHOTTKY BIPOLAR 8228
|
||
D.C.Characteristics TA=O°cto70°C;Vee=5V±5%.
|
||
Limits
|
||
Symbol Parameter Min.Typ.[1]Max. Unit TestConditions
|
||
Ve InputClampVoltage,AllInputs .75-1.0 V Vee=4.75V; le=-5mA
|
||
IF InputLoadCurrent,
|
||
STSTB 500 IlA Vee=5.25V
|
||
02&06 750 IlA VF=O.45V
|
||
Do,01, 04,Os, IlA
|
||
&07 250
|
||
AllOtherInputs 250 IlA
|
||
IR InputLeakageCurrent
|
||
STSTB 100 IlA Vee=5.25V
|
||
OBo-OB7 20 IlA VR=5.25V
|
||
AllOtherInputs 100 p.A
|
||
VTH InputThreshold Voltage, AUInputs 0.8 2.0 V VCC=5V
|
||
Icc PowerSupplyCurrent 140190 mA VCC=5.25V
|
||
VOL OutputLowVoltage,
|
||
00-07 .45 V VCC=4.75V; IOl=2mA
|
||
AllOtherOutputs .45 V IOl=10mA
|
||
VOH OutputHighVoltage,
|
||
00-07 3.63.8 V VcC=4.75V; IOH=-10p.A
|
||
AllOtherOutputs 2.4 V IOH=-1mA
|
||
los ShortCircuitCurrent,AllOutputs 15 90 mA Vec=5V
|
||
10(off)OffStateOutputCurrent,
|
||
AllControlOutputs 100 IlA Vce=5.25V; VO=5.25
|
||
-100 p.A VO=·45V
|
||
liNT INTACurrent 5 mA (SeeFigurebelow)
|
||
Note1:TypicalvaluesareforTA=2Soeandnominal supplyvoltages.
|
||
Capacitance Thisparameter isperiodically sampled andnot100%.test,ed.
|
||
Limits
|
||
Symbol Parameter Min.Typ.£1] Max.Unit
|
||
elN InputCapacitance 8 12pF
|
||
GoUTOutputCapacitance7 15pFControlSignals
|
||
I/OI/OCapacitance8 15pF(0orOB)
|
||
TESTCONDITIONS: VBIAS=2.5V,Vcc=S.OV, TA=2Soe,f=1MHz.
|
||
Note2:For00-07:R1=4Kn,R2=oon,
|
||
cL=25pF.Forallotheroutputs:
|
||
R1=500n,R2=1Kn,CL=100pF.
|
||
5-118228
|
||
23
|
||
INTA
|
||
INTATestCircuit(forRST7)
|
||
|
||
===PAGE 74===
|
||
SCHOTTKY BIPOLAR 8228
|
||
ADDRESS BUS
|
||
DBO
|
||
DB1
|
||
DB2
|
||
DB3
|
||
DATABUSDB4
|
||
DBs
|
||
DB6
|
||
D~
|
||
INTA
|
||
MEMR
|
||
MEMW CONTROL BUS
|
||
I/OR
|
||
I/OW2 25 -
|
||
GND.·Ao Ao20 26A1+5V A111 27
|
||
A2-5V A228 29
|
||
--A3+12V·A3
|
||
30
|
||
A4A4
|
||
31
|
||
As AS
|
||
32
|
||
A6A68080A 33
|
||
A7CPU A7 I-34
|
||
AS AS13 35
|
||
Ag SYSTEM DMAREO.·HOLD Ag
|
||
1
|
||
A10A10
|
||
40
|
||
A11A1137
|
||
A1214 A12SYSTEM INT.REO. •INT38A13A13
|
||
16 39A14INT.ENABLE ......- INTE A14
|
||
36
|
||
A1SA1S18
|
||
WRP-
|
||
17DBIN
|
||
413(') r,;D1TAl21HDLA
|
||
21 14 15
|
||
22 13 1110 15 13 ----. cP1
|
||
DO DB.12 10 15
|
||
cfJ2 9 17 16 ~
|
||
01,.
|
||
624 8 12 11 ~~ WAIT O2 8228.
|
||
38224 4 23 7 10BI-DIRECTIONAL9
|
||
REArJY 03,. ~CLOCK3 6BUSDRIVER 5GENERATOR04 .2DRIVER 1 1219 18 -..0 RESET 4 .Os 95 21 20 ----.06 .165 19 6 8 7 ----.
|
||
SYNC 07,.8 --28------- 23 ---.n-- +5V~
|
||
~4r14.....GND---'" ....,
|
||
STATUS STROBE1SYSTEM26.n h
|
||
"""CONTROL~5
|
||
22
|
||
~7 BUSEN ·-c
|
||
!"oFRESIN
|
||
+12V
|
||
+5V
|
||
GNDTANK
|
||
OSC
|
||
cfJ2(TTL)
|
||
RDYIN
|
||
8080ACPUStandard Interface
|
||
5-12
|
||
|
||
===PAGE 75===
|
||
intel® SiliconGateMOS8080A
|
||
SINGLECHIPa-BITN-CHANNEL MICROPROCESSOR
|
||
The8080Aisfunctionally andelectrically compatible withtheIntel®8080.
|
||
•TTLDriveCapability
|
||
•2J.LsInstruction Cycle
|
||
•Powerful Problem Solving
|
||
Instruction Set
|
||
•SixGeneral Purpose Registers
|
||
andanAccumulator
|
||
•SixteenBitProgram Counter for
|
||
DirectlyAddressing upto64KBytes
|
||
ofMemory•SixteenBitStackPointerandStack
|
||
Manipulation Instructions forRapid
|
||
Switching oftheProgram Environment
|
||
•Decimal,Binary andDouble
|
||
Precision Arithmetic
|
||
•AbilitytoProvidePriorityVectored
|
||
Interrupts
|
||
•512DirectlyAddressed I/OPorts
|
||
TheIntel®8080Aisacomplete 8-bitparallelcentralprocessing unit(CPU).Itisfabricated onasingleLSIchipusingIntel's
|
||
n-channel silicongateMOSprocess. Thisofferstheuserahighperformance solutiontocontrolandprocessing applications.
|
||
The8080Acontains six8-bitgeneralpurposeworking registers andanaccumulator. Thesixgeneralpurpose registers maybe
|
||
addressed individually orinpairsproviding bothsingleanddoubleprecision operators. Arithmetic andlogicalinstructions set
|
||
orresetfourtestableflags.Afifthflagprovides decimalarithmetic operation.
|
||
The8080Ahasanexternal stackfeaturewherein anyportionofmemory maybeusedasalastin/firstoutstacktostore/
|
||
retrievethecontents oftheaccumulator, flags,program counterandallofthesixgeneralpurpose registers. Thesixteenbit
|
||
stackpointercontrols theaddressing ofthisexternal stack.Thisstackgivesthe8080Atheabilitytoeasilyhandlemultiple
|
||
levelpriorityinterrupts byrapidlystoringandrestoring processor status.Italsoprovides almostunlimited subroutine nesting.
|
||
Thismicroprocessor hasbeendesigned tosimplify systemsdesign.Separate 16-lineaddressand8-linebi-directional data
|
||
bussesareusedtofacilitate easyinterface tomemory andI/O.Signalstocontroltheinterface tomemory andI/Oarepro
|
||
videddirectly bythe8080A.Ultimate controloftheaddressanddatabussesresideswiththeHOLDsignal.Itprovides the
|
||
abilitytosuspend processor operation andforcetheaddressanddatabussesintoahighimpedance state.ThispermitsOR
|
||
tyingthesebusseswithothercontrolling devicesfor(DMA)directmemory accessormUlti-processor operation.
|
||
:.,.
|
||
;
|
||
.:',
|
||
".
|
||
..,
|
||
....
|
||
.,.
|
||
:/",',"
|
||
:·i.'
|
||
,<'.,
|
||
<:
|
||
:::.
|
||
·:i··.
|
||
:,.W(8) Z (8)
|
||
TEMPREG. TEMPREG.
|
||
B(8) C(8)
|
||
REG. REG.
|
||
D(8) E (8)
|
||
REG. REG.
|
||
H (8) L (8)'\'
|
||
REG. REG.
|
||
STACKPOINTER(16)
|
||
(16)
|
||
PROGRAM COUNTER
|
||
.:..TIMING
|
||
.'.'...,::'>;'/:;):".,:;:", ':~',:, '.;:':' ;
|
||
,.'H:.: ':~, •.'."'.o;?oo .'H.;>::.... c·...'<1:,: ,:,'.:.•..
|
||
'.:.:
|
||
.~:?:.
|
||
:..
|
||
...•
|
||
:'..':.'t.;.;)it~:'
|
||
'';','':;;:"'.,.':':J:....::;."..
|
||
>:.~.;
|
||
..r·: ACCUMULATOR
|
||
:.... (8)
|
||
./:, <~'>:'.~
|
||
ACCUMULATOR
|
||
.-,;LATCH (8)
|
||
.~
|
||
5-13
|
||
|
||
===PAGE 76===
|
||
·SILICON GATEMOS8080'A- .
|
||
8080AFUNCTIONAL PINDEFINITION
|
||
Thefollowing describes thefunction ofallofthe8080AI/Opins.
|
||
Severalofthedescriptions refertointernaltimingperiods.
|
||
_. .
|
||
A15.AO(oU1putthree-state)
|
||
ADDRESS BUS;.the addressbusprovides theaddresstomemory
|
||
(upto64K8-bitwords)ordenotestheI/Odevicenumberforup
|
||
to256inputand256outputdevices. Aoistheleastsignificant
|
||
address.bit.
|
||
OJ-D.o(input/output three-state)
|
||
DATABUS;thedatabusprovides bi-directional. communication
|
||
.between theCPU,memory, andI/O.devicesforinstructions and
|
||
datatransfers. Also,duringthefirstclockcycleofeachmachine
|
||
cycle,the8080Aoutputs astatuswordonthedatabusthatde.
|
||
_scribesthecurrentmachine cycle.Doistheleastsignificant bit.
|
||
SYNC(output)
|
||
SYNCHRONlZING SIGNAL; theSYNCpinprovides asignalto
|
||
indicatethebeginning-of eachmachine cycle.
|
||
DBIN(output)
|
||
DATABUSIN;theDBINsignalindicates toexternal circuitsthat
|
||
thedatabusisintheinputmode.Thissignalshouldbeusedto
|
||
enablethegatingofdataontothe8080Adatabusfrommemory
|
||
orI/O.A101
|
||
GNO 2
|
||
043
|
||
054
|
||
°6~5
|
||
076
|
||
037
|
||
O~ 8
|
||
01.0 9
|
||
DO0 10
|
||
-5V 11
|
||
RESET 12
|
||
HOLD 13
|
||
INT 14
|
||
4>2 15
|
||
INTE0 16
|
||
OBIN0 17
|
||
WR 18
|
||
SYNC 19
|
||
+5V 20
|
||
-.
|
||
PinConfigurationINTE~
|
||
8080A40__~'-JIA11
|
||
39 A14
|
||
38 A13
|
||
37 A12
|
||
36 0 A15
|
||
35 0 Ag
|
||
34 As
|
||
33 0 A7
|
||
32 A6
|
||
31 As
|
||
30 0A4
|
||
29 A3
|
||
28 +12V
|
||
27 A2
|
||
26 A1
|
||
25 Ao
|
||
24 WAIT
|
||
23 READY
|
||
22 4>1
|
||
21 HLOA
|
||
REAPV(input)
|
||
READY; theREADY signalindicates tothe8080Athatvalid
|
||
memory orinputdataisavailable onthe8080Adatabus.This
|
||
signalisusedtosynchronize t.heCPUwithslowermemory orI/O
|
||
devices. Ifaftersending anaddressoutthe8080Adoesnotre
|
||
ceiveaREADY input,the8080AwillenteraWAITstateforas
|
||
longastheREADY lineislow.READY canalsobeusedtosingle
|
||
steptheCPU.
|
||
YlJAIT(output)
|
||
WAIT;theWAITsignalacknowledges thatth~CPUisinaWAIT
|
||
s~ate.
|
||
WR(output)
|
||
WRITE; theWRsignalisusedformemory WRITEorI/Ooutput
|
||
control. ThedataonthedatabusisstablewhiletheWRsignalis
|
||
activelow(WR=0).
|
||
.HOLD(input)
|
||
HOLD;theHOLDsignalrequests' theCPUto'entertheHOLD
|
||
state.TheHOLDstateallowsanexternal devicetogaincontrol
|
||
ofthe8080Aaddressanddatabusassoonasthe8080Ahascom
|
||
pleteditsuseofthesebusesforthecurrentmachine cycle.Itis
|
||
recognized underthefollowing conditions:
|
||
•theCPUisintheHALTstate.
|
||
•theCPUisintheT2orTWstateandtheREADYsignalisactive.
|
||
Asaresultofentering theHOLDstf'tetheCPUADDRESS BUS.
|
||
(A15-AO) andDATABUS(07-00)willbeintheirhighimpedance
|
||
state.TheCPUacknowledges itsstatewiththeHOLDAC
|
||
KNOWLEDGE (HLDA) pin.
|
||
HLOA(output)
|
||
HOLDACKNOWLEDGE; theHLDAsignalappears inresponse
|
||
totheHOLD'signaland!ndicates thatthedataandaddressbuswillgotothehighimpedance state.TheHLOAsignalbeginsat:
|
||
•T3forREADmemoryorinput.
|
||
•TheClockPeriodfollowing T3forWRITEmemory orOUT
|
||
PUToperation.
|
||
Ineithercase,theHLOAsignalappearsaftertherisingedgeof4>1
|
||
andhighimpedance occursaftertherisingedgeof4>2.
|
||
INTE(output)
|
||
INTERRUPTENABLE; indicates thecontentoftheinternalinter
|
||
ruptenableflip/flop. Thisflip/flop maybesetorresetbytheEn
|
||
able.andDisable Interrupt instructions andinhibitsinterrupts
|
||
frombeingaccepted bytheCPUwhenitisreset.Itisauto-
|
||
,matically reset(dfsab'ling furtherinterrupts) -attimeT1ofthein-
|
||
struction fetchcycle(M1)whenaninterrupt isaccepted andis
|
||
alsoresetbytheRESETsignal.
|
||
INT(input)
|
||
INTERR.UPT REQUEST; theCPUrecognizes aninterrupt re
|
||
questonthislineattheendofthecurrentinstruction orwhile
|
||
halted.IftheCPUisintheHOLDstateoriftheInterrupt Enable
|
||
flip/flop isresetitwillnothonortherequest.
|
||
RESET(input)[1]
|
||
RESET; whiletheRESETsignalisactivated, thecontentofthe
|
||
program counter iscleared. AfterRESET, theprogram willstart
|
||
atlocation 0inmemory.theINTEandHLDAflip/flops arealso
|
||
reset.Notethattheflags,accumulator, stackpointer,andregisters
|
||
arenotcleared.
|
||
VssGroundReference.
|
||
VDD+12±5%Volts.
|
||
Vee+5±5%Volts.
|
||
Vss-5±5%Volts(substrate bias).
|
||
,l/>1,'l/>2 2externally supplied clockphases.(nonTTLcompatible)
|
||
5-14
|
||
|
||
===PAGE 77===
|
||
SILICON GATEMOS8080A
|
||
ABSOLUTE MAXIMUM RATINGS·
|
||
Temperature UnderBias ' O°Cto+70°C
|
||
StorageTemperatu re. . . . . . . . . . . . . . . _65°Cto+150°C
|
||
AllInputorOutputVoltages
|
||
WithRespecttoVSS -0~3Vto+20V
|
||
Vcc,VooandVSSWithRespecttoVss -0.3Vto+20V
|
||
.PowerDissipation 1.5W*COMMENT: Stressesabovethoselistedunder''Absolute Maxi
|
||
mumRatings" maycausepermanent damage tothedevice.
|
||
Thisisastressratingonlyandfunctional operation ofthede
|
||
viceattheseoranyotherconditions abovethoseindicated in
|
||
theoperational sectionsofthisspecification isnotimplied.Ex
|
||
posuretoabsolute maximum ratingconditions forextended
|
||
periodsmayaffectdevicereliability .
|
||
D.C.CHARACTERISTICS
|
||
TA=O°Cto70°C,VOO=+12V±5%,Vcc=+5V±5%,Vss=-5V±5%,Vss=OV,UnlessOtherwise Noted.
|
||
Symbol Parameter Min. Typ. Max.Unit TestCondition
|
||
VILC ClockInputLowVoltage Vss-1 Vss+0.8 V
|
||
VIHC ClockInputHighVoltage 9.0 Voo+1 V
|
||
VIL InputLowVol~age Vss-1 VsstO.8 V
|
||
VIH InputHighVoltage 3.3 Vcc+1 V
|
||
VOL OutputLowVqltage 0.45- V}IOl=1.9mAonalloutputs,
|
||
VOH OutputHighVoltage 3.7 VIOH=-150~A.
|
||
100(AV)Avg.PowerSupplyCurrent(Voo) 4070mA
|
||
ICC(AV)Avg.PowerSupply Current (Vcc) 60 80mA}Operation
|
||
TCy=.48J.1sec
|
||
ISB(AV) Avg.PowerSupplyCurrent(Vss) .01 1mA
|
||
IlL InputLeakage ±10 J.1A VSS~VIN~Vcc
|
||
ICl ClockLeakage ±10 J.1AVss~VCLOCK ~VDD
|
||
IDL[2] DataBusLeakageinInputMode -100 ~A VSS~VIN~Vss+0.8V
|
||
-2.0 mA
|
||
Vss+0.8V~VIN ~Vcc
|
||
IFLAddressandDataBusLeakage +10
|
||
~AVADoR/oATA =VCC
|
||
Dl:IringHOLD -100VADOR/DATA =Vss+0.45V
|
||
CAPACITANCE
|
||
TA=25°C VCC=Voo=Vss=OV,Vss=-5V
|
||
Symbol Parameter Typ. Max.Unit TestCondition
|
||
Cq> ClockCapacitance 1725pffc=1MHz
|
||
CIN InputCapacitance 610pfUnmeasured Pins
|
||
COUTOutputCapacitance 10 20 pfReturned toVss
|
||
NOTES:
|
||
1.TheRESETsignalmustbeactiveforaminimum of3clockcycles.
|
||
2.WhenDSINishighandVIN>VIHaninternalactivepullupwill
|
||
beswitchedontotheDataSus.
|
||
3.~Isupply/~TA=-O.45%t C.
|
||
5-15TYPICAL SUPPLY CURRENT VS.
|
||
TEMPERATURE, NORMALIZED.[3]1.5,..-----r-----,-----_
|
||
...zwa:a:
|
||
::»(,)1.0t----~~=------+__--~
|
||
>..Ja.a.::»
|
||
U)
|
||
0.50~---+2&.-5 ----+5"'-0---' ......1+75
|
||
AMBIENT TEMPERATURE (Oe)
|
||
DATABUSCHARACTERISTIC
|
||
DURING DB"IN
|
||
MAX
|
||
°O~------------~
|
||
Vee
|
||
|
||
===PAGE 78===
|
||
SILICON GATEMOS8080A
|
||
A.C.CHARACTERISTICS
|
||
TA=O°Cto70°C,VOO=+12V±5%,VCC=+5V±5%,Vas=-5V±5%,Vss=OV,UnlessOtherwise Noted
|
||
Symbol Parameter Min.Max.Unit TestCondition
|
||
tCy[3] ClockPeriod 0.482.0J1sec
|
||
tr,tf·ClockRiseandFallTime 050nsec
|
||
~1 f/J1PulseWidth 60 nsec
|
||
tq,2 cf>2Pu.lseWidth 220 nsec
|
||
t01 Delayep1 toep2 0 nsec
|
||
.t02 DelaylP2tol/>, 70 nsec
|
||
t03 Delayep, toep2LeadingEdges 80 nsec
|
||
tOA[2]AddressOutputDelayFrom ~2 200nsec}Cl=100pf
|
||
to.D[2]DataOutputDelayFromf/J2 220nsec
|
||
toC[2] Signal'OutputDelayFromep1,orep2(SYNC,WR,WArT, HLDA) 120nsec}Cl=50pftOF[2]DBINDelayFromlP2 25140nsec
|
||
tOI[1] DelayforInputBustoEnterInputMode tOFnsec
|
||
tOS1 .Data Set~pTimeDuring ~1andDBIN 30 nsec
|
||
TIMINGWAVEFORMS [14](Note:Timingmeasurements aremadeatthefollowing reference voltages: CLOCK"1"=8.0V
|
||
"0"=1.0V;INPUTS"1"=3.3V,110"=0.8V;OUTPUTS "1"=2.0V,"0"=0.8V.)
|
||
(/>,
|
||
SYNC·
|
||
DBIN
|
||
READY
|
||
WAIT
|
||
HOLD
|
||
HLDA
|
||
INT
|
||
INTEtCY-I-.to,.---.~~1
|
||
If\ r~ JF\ iF\
|
||
.-t<l>2~1
|
||
j~ }~~ ~jJ-....h... F- ~~
|
||
~ ~~H
|
||
~to3..1 !O2~
|
||
___ I.
|
||
~r..
|
||
~tOA-.I--..;.. --------- ~----------f
|
||
tAW
|
||
~too--' ~tOII......... ---itoHI"'-...-tOO-'
|
||
~r· 4=.....-"r-DATAIN~.JDATAOUT,,"".J--t 1-----------I ,--------- ~--
|
||
--.tos,...- ~I--towr---.
|
||
T -t-~tOS2-'
|
||
~tocl~ ---..toc1..-
|
||
-r 1-
|
||
~tOF~ ~tOF
|
||
-----------~t
|
||
toc.........1 .
|
||
ItHl~
|
||
-------------I=@t--;f!1~-~:'J>tRS toc..........1
|
||
tH-..--X- l-
|
||
toc---"1.- tH-.1.----J@I
|
||
~I~;~~
|
||
--X@,.
|
||
tiS1=-=~~
|
||
tH--. ~
|
||
.5-16
|
||
|
||
===PAGE 79===
|
||
SILICON GATEMOS8080A
|
||
A.C.CHARACTERISTICS (Continued)
|
||
TA=O°Cto70°C,Voo=+12V±5%,Vee=+5V±5%,Vss=-5V'±5%,V55 =OV,UnlessOtherwise Noted
|
||
Symbol Parameter Min.Max.Unit TestCondition
|
||
t052 DataSetupTimeto~2DuringDBIN 150 nsec
|
||
tOH(1)DataHoldTimeFrom ~2DuringDBIN [1] nsec
|
||
tiE[2)INTEOutputDelayFrom ~2 200nsec CL'=50pf
|
||
tRS READYSetupTimeDuring ~2 120 nsec
|
||
tH5 HOLDSetupTimeto~2 140 nsec
|
||
tiS INTSetupTimeDuring ~2(During cP1inHaltMode) 120 nsec
|
||
tH HoldTimeFrom ~2(READY, INT,HOLD) 0 nsec
|
||
tFO DelaytoFloatDuringHold(AddressandData~us) 120nsec
|
||
tAW[2)AddressStablePriortoWR-[5] nsec
|
||
tow[2)OutputDataStablePriortoWR [6] nsec
|
||
tWD[2] OutputDataStableFromWR [7] nsec
|
||
tWf\[2] ,AddressStableFromWR [7] nsec~CL=100pf:Address, Data
|
||
.-- CL=50pf:WR,HLDA,DBIN
|
||
tHF[2] HLDAtoFloatDelay [8] nsec
|
||
tWF[2] WRtoFloatDelay [9] nsec
|
||
tAH[2] AddressHoldTimeAfterDBINDuringHLDA -20 nsec--
|
||
+5V
|
||
TYPICAL ~OUTPUT DELAYVS.ACAPACITANCE
|
||
+20r-----~-----r----~---__.
|
||
+1002.1K
|
||
+50 o
|
||
.:1.CAPACITANCE (pf)
|
||
(CACTUAL - CSPEC)-50lit..s
|
||
>+10«..Jw
|
||
C
|
||
~0
|
||
:;)
|
||
Q.
|
||
~
|
||
:;)-100
|
||
<1
|
||
-20
|
||
-1003.tCY=t03+tr~2+t4>2+tf~2+t02+trit>1;>480ns.8080A
|
||
OUTPUTNOTES:
|
||
1.Datainputshouldbeenabledwith'OBINstatus.Nobusco~f1ictcanthenoccuranddataholdtimeisassured.
|
||
tOH=50nsortOF,whichever isless.
|
||
2.LoadCircuit.
|
||
4.Thefollowing arerelevantwheninterfacing the8080AtodeviceshavingVIH=3.3V:
|
||
a)Maximum outputrisetimefrom.8Vto3.3V=100ns@CL=SPEC.
|
||
b)Outputdelaywhenmeasured to3.0V ==SPEC+60ns @CL==SPEC.
|
||
c)IfCL"*SPEC,add.6ns/pFifCL>CSPEC,subtract.3ns/pF(frommodified delay)ifCL<CSPEC.
|
||
5.tAW=2tCY-t03-tr</>2-140nsec.
|
||
6.•tow=tCY-t03-tr</>2-l70nsec.
|
||
7.IfnotHLOA,two=tWA=t03+tr</>2+10ns.IfHLOA,two=twA=twF.
|
||
8.tHF==t03+trc/>2-50ns.
|
||
9.twF=t03+trc/>2-10ns
|
||
10.DatainmustbestableforthisperiodduringOBIN·T3.BothtOS1andtOS2mustbesatisfied.'
|
||
11.ReadysignalmustbestableforthisperiodduringT2orTW.(Mustbeexternally synchronized.)
|
||
12.HoldsignalmustbestableforthisperiodduringT2orTWwhenenteringholdmode,andduringT3,T4,TS
|
||
andTWHwheninholdmode.(External synchronization isnotrequired.)
|
||
13.Interrupt signalmustbestableduringthisperiodofthelastclockcycleofanyinstruction inordertobe
|
||
recognized onthefollowing instruction. (External synchronization isnotrequired.)
|
||
14.Thistimingdiagram,showstimingrelationships only;itdoesnotrepresent anyspecificmachinecycle.07.00~
|
||
SYNC
|
||
OBIN
|
||
WR
|
||
toc
|
||
READY
|
||
WAIT
|
||
HOLDs-
|
||
toc...-
|
||
HLDA
|
||
~INT
|
||
I-t:1- INTE
|
||
5-17
|
||
|
||
===PAGE 80===
|
||
SILICON GATEMOS8080A
|
||
INSTRUCTION SET
|
||
Theaccumulator groupinstructions includearithmetic and
|
||
logicaloperators withdirect,indirect, andimmediate ad
|
||
dressing modes.
|
||
Move,load,and·storeinstruction groupsprovidetheability
|
||
tomoveeitheraor16bitsofdatabetween memory,' the
|
||
sixworking registers andtheaccumulator usingdirect,in
|
||
direct,and'immediate addressing modes.
|
||
Theabilitytobranchtodifferent portions oftheprogram
|
||
isprovided withjump,jumpconditional, andcomputed
|
||
jumps.Alsotheabilitytocalltoandreturnfromsub
|
||
routines isprovided bothconditionally andunconditionally.
|
||
TheRESTART (orsinglebytecallinstruction) isusefulfor
|
||
interrupt vectoroperation.
|
||
OOl:Jbleprecision operators suchasstackmanipulation and
|
||
doubleaddinstructions extendboththearithmetic and
|
||
interrupt handlingcapability ofthea080A.Theabilitytoincrement anddecrement memory, thesixgeneralregisters
|
||
andtheaccumulator isprovided aswellasextended incre
|
||
mentanddecrement instructions tooperateontheregister
|
||
pairsandstackpointer. Further capability isprovided by
|
||
theabilitytorotatetheaccumulator I~ftorrightthrough
|
||
oraroundthecarrybit.
|
||
Inputandoutputmaybeaccomplished usingmemory ad
|
||
dressesasI/Oportsorthedirectly addressed I/Oprovided
|
||
forinthe8080Ainstruction set.
|
||
Thefollowing specialinstruction groupcompletes the8080A
|
||
instruction set:theNOPinstruction, HALTtostoppro
|
||
cessorexecution andtheOAAinstructions providedecimal
|
||
arithmetic capability.STCallowsthecarryflagtobedi
|
||
rectlyset,andtheCMCinstruction allowsittobecomple
|
||
mented.CMAcomplements thecontents oftheaccumulator
|
||
andXCHGexchanges thecontents oftwo16-bitregister
|
||
pairsdirectly.
|
||
DataandInstruction Formats
|
||
Datainthea080Aisstoredintheformofa-bitbinaryintegers. Alldatatransfers tothesystemdatabuswillbeinthe
|
||
sameformat.
|
||
10706Os04030201001
|
||
OATAWORO
|
||
Theprogram instructions maybeone,two,orthreebytesinlength.Multiple byteinstructions mustbestored
|
||
insuccessive wordsinprogram memory. Theinstruction formats thendependontheparticular operation
|
||
executed.
|
||
OneByteInstructions
|
||
TwoByteInstructions
|
||
10.706OsD4°3°2°1DOIOPCODE
|
||
107°6OsD4°3°2°1DOIOPERANO
|
||
ThreeByteInstructions
|
||
107°6Os04°3°2°1DOIOPCOOE
|
||
107°6Os04°3°201DOILOWADDRESS OROPERAND 1
|
||
10706Os0403°2°1DOIHIGHADDRESS OROPERANO 2TYPICAL INSTRUCTIONS
|
||
Registertoregister, memory refer
|
||
ence,arithmetic orlogical,rotate,
|
||
return,push,pop,enableordisable
|
||
Interrupt instructions
|
||
Immediate modeorI/Oinstructions
|
||
Jump,callordirectloadandstore
|
||
instructions
|
||
Forthe8080Aalogic"1"isdefinedasahighlevelandalogic110"isdefinedasalowlevel.
|
||
6-18
|
||
|
||
===PAGE 81===
|
||
SILICON GATEMOS8080.A
|
||
INSTRUCTION SET
|
||
Summary ofProcessor Instructions
|
||
Instruction Code[1J Clock[2] Instruction Code(1) Clock[2J
|
||
Mnemonic Description D7D6OsD4D3020,DoCycles Mnemonic Description D706Os04Da~0,DoCycles
|
||
MOVr1.r2Moveregistertoregister 010 0 0 S SS5 RZ Returnonzero 110 0,0 005/11
|
||
MOVM,r Moveregistertomemory 0 1 11 0SSS7 RNZ Returnonnozero 110 000C05/11
|
||
MOVr,M Movememorytoregister 0 100 01107 RP Returnonpositive 1 1 1 100 005/11
|
||
.HLT Halt 0 11 10 1107 RM Returnonminus 1 1 1 1 1 0 005/11
|
||
MVIrMoviimmediate register 0 000 01 107 RPE Returnonparityeven 1 11010005/11
|
||
MVIM Moveimmediate memory 001 1011010 RPO Returnonparityodd 1110 00005/11
|
||
lNRr Incrementregister 0 000 010 0 5 RST Restart 1 1A A A 11 1 11
|
||
OCRr Decrement register 0 000 010 1 5 IN Input 1 1011 01 1 10
|
||
INRMIncrementmemory 0 01 1010 0 10 OUT Output 11 0 1001110
|
||
OCRMDecrement memory 0 0 110 1 0 110 LXIB Loadimmediate register 000 0 0 00110
|
||
ADDrAddregistertoA 10'000S S S 4 PairB&C
|
||
ADCr AddregistertoAwithcarry 10 0 01S S S 4 LXIO Loadimmediate register 0 0 0 000 10
|
||
SUBrSubtractregisterfromA 1001 0S S S 4- PairD&E
|
||
SaBrSubtractregisterfromA 1001 1S S S 4 LXIH Loadimmediate register 0 0 0 00 0 10
|
||
withborrow PairH&L
|
||
ANAr AndregisterwithA 01 0 0 S S S ,4 LXISP Loadimmediate stackpointer 0 0 1100 0 10
|
||
XRAr ExclusiveOrregisterwithA 01 0 1 S SS4 PUSHaPushregisterPairB&Con1 100 01 0 11
|
||
ORAr .0rregisterwithA 0110S SS4 stack
|
||
CMPr CompareregisterwithA 0111SS'S4 PUSH0PushregisterPair0&Eon 000 11
|
||
ADOM AddmemorytoA 0 0 00 1107 stack
|
||
ADCM AddmemorytoAwithcarry 00011 107 PUSHHPushregisterPairH&Lon 000 11
|
||
SUBMSubtractmemoryfromA 00'101107 stack
|
||
SBBMSubtractmemoryfromA 0 0 11 1 1 07 PUSHPSWPushAandFlags 00 11
|
||
withborrow onstack
|
||
ANAM AndmemorywithA 01 0 0 07 POPBPopregisterpairB&Coff 0 0 0 0 0 10
|
||
XRAM Exclusive0rmemorywithA 01O.1 0 7 stack
|
||
ORAM OrmemorywithA 0110 07 POPD Popregisterpair0&Eoff 0 0 0O' 10
|
||
CMPM ComparememorywithA 011 1 07 stack
|
||
ADI Addimmediate toA 100 0 07 POPHPo.pregisterpairH&Loff 0 00 0 10
|
||
ACI Addimmediate toAwith 10 01 07 stack
|
||
carry POPPSWPopAandFlags 0 0 0 10
|
||
SUI Subtractimmediate fromA 00 0 offstack
|
||
SBI Subtractimmediate fromA 0 1 0 STA StoreAdtrect 00 100013
|
||
withborrow LOA LoadAdirect 00 11 0 013
|
||
ANI Andimmediate withA 0 0 0 XCHG Exchange0&E,H&L 1 1 0 1014
|
||
XRI Exclusive Orimmediate with 0 1 0 Registers
|
||
A XTHL Exchang~topofstack,H&L1110 0 0 1118
|
||
ORI Orimmediate withA 11 1 10 0 7 SPHL H&Ltostackpointer 11 1 1 1 00 1 5
|
||
CPI Compareimmediate withA1 1 1 1 1 07 PCHL H&Ltoprogramcounter 1110 1 0 015
|
||
RLC RotateAleft 00,000 1 4 DADBAddB&CtoH&L 0000 100 1 10
|
||
RRC RotateAright 0 0 0 0 1 1 4 DAD0Add0&EtoH&L 0 0011 0 0 1 10
|
||
RAL RotateAleftthroughcarry 0 0010 14 DADHAddH&LtoH&L 00101 00110
|
||
RAR RotateArightthrough 0 0 0 1l' 14 DADSPAddstackpointertoH&L0 0 1 11 0 0 1 10
|
||
carry STAXB StoreAindirect 0 0 0 0 0 0 1 0 7
|
||
JMP Jumpunconditional 100001110 STAX0StoreAindirect 000 100107
|
||
JC JumponcarrY 1011 01010 LOAXB LoadAindirect 00 0 0 1 0 1 07
|
||
JNC Jumponnocarry 101 0 0 1010 LoAXO LoadAindirect 0 0 0 1 1 0 1 07
|
||
JZ Jumponzero 10010 1010 INXBIncrement B&Cregisters 0 0 0 00 011 5
|
||
JNZ Jumponnozero 100 00 1010 INXDIncrement 0&Eregisters 000 1001 1 5
|
||
JP Jumponpositive 1 1 1001010 INXHIncrement H&Lregisters 001000115
|
||
JM Jumponminus 111 101010 INXSP Increment stackpointer 001 10 011'5
|
||
JPE Jumponparityeven 11 0101010 OCXBDecrement B&C 0 0 0 0 1 0 115
|
||
JPO Jumponparityodd 1 1 0 0 0 10.10 ,OCX0Decrement 0&E 000 1 1 0 1 1 5
|
||
CALL Callunconditional 100 11 0117 OCXHDecrement H&L 0 0 10 1011 5
|
||
CC Calloncarry 10111 0 0 11/17 OCXSP Decrement stackpointer 0O.1 11 0 1 15
|
||
CNC Callonnocarry 101010 0 11/17 CMA Complement A 00 1 0 1 1 114
|
||
CZ Callonzero ,100 110011/17 STC Setcarry 0 0 1 10"11 4
|
||
CNZ Callonnozero 100010011/17 CMC Complement carry 001111114
|
||
CP Callonpositive 11 1 0 1 0 011/17 DAA DecimaladjustA 0010 011,14
|
||
CM Callonminus 11 111 0011/17 SHLD StoreH&Ldirect 0 0 1(}0 01016
|
||
CPE Callonparityeven 110110011/17 LHLD LoadH&Ldirect 0010101016
|
||
CPO Callonparityodd 1 1 0010 0 11/17 EI EnableInterrupts 111110 114
|
||
RET Return 1 0 0100110 01 Disableinterrupt 1 1 1 10 0 1 1 4
|
||
RC Returnoncarry 10110,005/11 N.OP No-operation 000000 004
|
||
RNC Returnonnocarry 10100 005/11
|
||
NOTES:. 1.DDDorSSS-OOOB-001 C-010D-011'E-100H-101 L-110Memory....:.111 A.
|
||
2.Twopossiblecycletimes,(5/11)indicateinstruction cyclesdependent oncondition flags.
|
||
5-19
|
||
|
||
===PAGE 82===
|
||
infel® SiliconGateMOS8080A-1
|
||
SINGLECHIP8-BITN-CHANNEL MICROPROCESSOR
|
||
•TTLDriveCapability
|
||
•1.3J.LsInstruction Cycle
|
||
•Powerful Problem Solving
|
||
Instruction Set
|
||
•SixGeneralPurposeRegisters
|
||
andanAccumulator
|
||
•SixteenBitProgram Counterfor
|
||
DirectlyAddressing upto64KBytes
|
||
ofMemory•SixteenBitStackPointerandStack
|
||
Manipulation Instructions forRapid
|
||
Switching oftheProgram Environment
|
||
•Decimal,Binary andDouble
|
||
Precision Arithmetic
|
||
•AbilitytoProvidePriorityVectored
|
||
Interrupts
|
||
•512DirectlyAddressed 1/0Ports
|
||
TheIntel®aOaOAisacomplete a-bitparallelcentralprocessing unit(CPU).Itisfabricated onasingleLSIchipusingIntel's
|
||
n-channel silicongateMOSprocess. Thisofferstheuserahighperformance solution tocontrolandprocessing applications.
|
||
TheaOaOAcontains six8-bitgeneralpurposeworking registers andanaccumulator. Thesixgeneralpurpose registers maybe
|
||
addressed individually orinpairsproviding bothsingleanddoubleprecision operators. Arithmetic andlogicalinstructions set
|
||
orresetfourtestableflags.Afifthflagprovides decimalarithmetic operation.
|
||
TheaOaOAhasanexternal stackfeaturewherein anyportionofmemory maybeusedasalastin/firstoutstacktostore/
|
||
retrievethecontents oftheaccumulator, flags,program counterandallofthesixgeneralpurpose registers. Thesixteenbit
|
||
stackpointercontrols theaddressing ofthisexternal stack.Thisstackgivesthe80aOAtheabilitytoeasilyhandlemultiple
|
||
levelpriorityinterrupts byrapidlystoringandrestoring processor status.Italsoprovides almostunlimited subroutine nesting.
|
||
Thismicroprocessor hasbeendesigned tosimplify systemsdesign.Separate 16-lineaddressanda-linebi-directional data
|
||
bussesareusedtofacilitate easyinterface tomemory andI/O.Signalstocontroltheinterface tomemory andI/Oarepro
|
||
videddirectly bytheaOaOA.Ultimate controloftheaddressanddatabussesresideswiththeHOLDsignal.Itprovides the
|
||
abilitytosuspend processor operation andforcetheaddressanddatabussesintoahighimpedance state.ThispermitsOR
|
||
tyingthesebusseswithothercontrolling devicesfor(DMA)directmemory accessormUlti-processor operation.
|
||
5-20
|
||
|
||
===PAGE 83===
|
||
SILICON GATEMOS8080A-1
|
||
ABSOLUTE MAXIMUM RATINGS·
|
||
Temperature UnderBias O°Cto+70°C
|
||
StorageTemperature -65°Cto+150°C
|
||
AllInputorOutputVoltages
|
||
WithRespecttoVaa -0.3Vto+20V
|
||
Vee,VOOandVssWithRespecttoVaa -0.3Vto+20V
|
||
PowerDissipation . . . . . . . . . . . ..1.5W*COMMENT: Stressesabovethoselistedunder'Absolute Maxi
|
||
mumRatings" maycausepermanent damagetothedevice.
|
||
Thisisastressratingonlyandfunctional operation ofthede
|
||
viceattheseoranyotherconditions abovethoseindicated in
|
||
theoperational sectionsofthisspecification is'notimplied.Ex
|
||
posuretoabsolute maximum ratingconditions forextended
|
||
periodsmayaffectdevicereliability.
|
||
D.C.CHARACTERISTICS
|
||
TA=O°Cto70°C,Voo=+12V±5%,Vce=+5V±5%,Vss=-5V±5%,Vss=OV,UnlessOtherwise Noted.
|
||
Symbol Parameter Min. Typ. Max. Unit TestCondition
|
||
VILe ClockInputLowVoltage Vss-1 Vss+0.8 V
|
||
VIHC ClockInputHighVoltage 9.0 Voo+1 V
|
||
VIL InputLowVoltage Vss-1 Vss+0.8 V
|
||
VIH InputHighVoltage 3.3 Vec+1 V
|
||
VOL OutputLowVoltage 0.45 V}'0L=1.9mAonalloutputs,
|
||
VOHOutputHighVoltage 3.7 V'OH=150J,.lA.
|
||
100(AV)Avg.PowerSupplyCurrent(Voo) 40 70mA
|
||
ICC(AV)Avg.PowerSupplyCurrent(Vce) 60 80mA}Operation
|
||
TCy=.32Jlsec
|
||
'ss(AV)Avg.PowerSupplyCurrent(Vss) .01 1mA
|
||
IlL InputLeakage ±10 pAVss~VIN~Vee
|
||
ICl ClockLeakage ±10 pAVss~VeLOeK ~Voo
|
||
IOL[2] DataBusLeakage inInputMode -100 JlA VSS~VIN ~Vss+0.8V
|
||
-2.0 mA
|
||
Vss+0.8V~VIN ~Vec
|
||
IFLAddressandDataBusLeakage +10pAVAOOR/OATA =Vec
|
||
DuringHOLD -100VAOOR/OATA =VSS+0.45V
|
||
+75 +25 +500.5----"'-----....L..- ....JoTYPICAL SUPPLY CURRENT VS.
|
||
TEMPERATURE, NORMALIZED.[3]
|
||
AMBIENT TEMPERATURE (OC)1.5r------r-----~---_
|
||
~zwa:a:
|
||
::>
|
||
(J1.01"-----=-~:------+-------4
|
||
>-'Q.
|
||
Q.
|
||
::>enSymbol Parameter Typ. Max. Unit TestCondition
|
||
Cf/> ClockCapacitance 1725 pffc=1MHz
|
||
CIN InputCapacitance 610pfUnmeasured Pins
|
||
COUTOutputCapacitance 10 20 pfReturned toVSS
|
||
NOTES:
|
||
1.TheRESETsignalmustbeactiveforaminimum of3clockcycles.
|
||
2.WhenOSINishighandVIN>VIHaninternalactivepullupwill
|
||
beswitchedontotheDataSus.
|
||
3.aIsupplyIb.TA=-0.45%/c.CAPACITANCE
|
||
TA=25°C Vee=VOO=Vss=OV,Vas=-5V
|
||
DATABUSCHARACTERISTIC
|
||
DURING DBIN
|
||
MAX
|
||
°o'-------------~
|
||
Vee
|
||
5-21
|
||
|
||
===PAGE 84===
|
||
SILICON GATEMOS8080A-1
|
||
A.c.CHARACTERISTICS CAUTlON: Whenoperating the8080A·latornearfullspeed,caremustbetakentoassureprecisetimingcompatibility between8080A·', 8224and8228.
|
||
TA=O°Cto70°C,Voo=+12V±5%,VCC=+5V±5%,VSS=-5V±5%,VSS=OV,UnlessOtherwise Noted
|
||
Symbol Parameter Min.Max.Unit TestCondition
|
||
tCy[3] ClockPeriod .322.0J.1sec
|
||
tr,tfClockRiseandFallTime 025nsec
|
||
t4»1 ¢1PulseWidth 50 nsec
|
||
t4»2 ~PulseWidth 145 nsec
|
||
t01 Delay cfJ1tocfJ2 0 nsec
|
||
t02 Delay¢2tocfJ1 60 nsec
|
||
t03 Delay¢,to¢2LeadingEdges 60 nsec
|
||
tOA[2]AddressOutputDelayFrom¢2 150nsec}Cl=50pftoo[2]DataOutputDelayFrom¢2 180nsec
|
||
toc[2] SignalOutputDelayFrom¢"orcfJ2(SYNC,WR.WAIT, HLOA) 110nsec}Cl=50pftOF[2]DBINDelayFrom¢2 25130nsec
|
||
tOI[1] DelayforInputBustoEnterInputMode tOFnsec
|
||
tOS1 DataSetupTimeDuring cfJ1andDBIN 10 nsec
|
||
TIMINGWAVEFORMS [14](Note:Timingmeasurements aremadeatthefollowing reference voltages: CLOCK111"=8.0V
|
||
110"=1.0V;INPUTS 111"=3.3V,1'0"=0.8V;OUTPUTS "1"=2.0V,"0"=O.8V.)
|
||
SYNC
|
||
DBIN
|
||
READY
|
||
WAIT
|
||
HOLD
|
||
HLDA
|
||
INT
|
||
INTE. tCY~I---.
|
||
~11- ---.
|
||
Fft~l
|
||
I f\ r~Jf\ }F\
|
||
~t~2~1
|
||
-~}~1~~~ -~ ..Jjl- .....,J-1-J~k-I ~ "1~
|
||
...t03"'! -.\t02~
|
||
--~.-=1.
|
||
i4--tOA-'\- ---1---~------------- --f
|
||
I tAW
|
||
i4---too~1 -...tOI1'- --ttoHI'-~tOO-"
|
||
~r -~.J+:.....H" DATAOUT .,._.JrPATA IN,--- ~-t- 1------10-----I
|
||
-...tOS1...- I-f--tow~
|
||
T -i-.....toS2.....
|
||
---.toc1.-. .-.tocl.-
|
||
-r t
|
||
~tOF:.I ...tOF
|
||
-----------~l
|
||
toc.-.-.\
|
||
L-,ItH-ijr--
|
||
--_...._------~- -r@t~~ I -tRSI- 'RS toe-'-{I
|
||
tH-..-T
|
||
I~I
|
||
toc---' _ tH-.11.-
|
||
!@IX
|
||
~r~:~
|
||
-L!@~
|
||
tiS1==~~
|
||
tH-......
|
||
5-22
|
||
|
||
===PAGE 85===
|
||
SILICON GATEMOS8080A-1
|
||
A.C.CHARACTERISTICS (Continued)
|
||
TA=O°Cto70°C,Voo=+12V±5%,Vee=+5V±5%,Vss=-5V±5%,Vss=OV,UnlessOtherwise Noted
|
||
Symbol Parameter Min.Max.Unit TestCondition
|
||
tOS2 DataSetupTimeto¢2DuringDBIN 120 nsec
|
||
tOH[1]DataHoldTimeFrom¢2DuringDBIN [1] nsec
|
||
tiE[2]INTEOutputDelayFrom¢2 200nsec CL=50pf
|
||
tRS READY SetupTimeDuring¢2 90 nsec
|
||
tHS HOLDSetupTimeto¢2 120 nsec
|
||
tiS INTSetupTimeDuring¢2(During <t>1inHaltMode) 100 nsec
|
||
tH HoldTimeFrom¢2(REAOY, INT,HOLD) 0 nsec
|
||
tFO DelaytoFloatDuringHold(AddressandOataSus) 120nsec
|
||
tAW[2]AddressStablePriortoWR........,
|
||
[5] nsec
|
||
tOW[2] OutputDataStablePriortoWR [6] nsec
|
||
two[2]OutputDataStableFromWR [7] nsec
|
||
tWA[2]AddressStableFromWR [7] nsec~CL=50pf:Address, Data
|
||
CL=50pf:WR,HLDA,DBIN
|
||
tHF[2] HLDAtoFloatDelay [8] nsec
|
||
tWF[2] WRtoFloatDelay [9] nsec
|
||
tAH[2]Address HoldTimeAfterDBINDuringHLDA -20 nsec-
|
||
NOTES:
|
||
1.DatainputshouldbeenabledwithOBINstatus.Nobusconflict canthenoccuranddataholdtimeisassured.
|
||
tOH::::50nsortOF,whichever isless.
|
||
2.LoadCircuit.
|
||
+5V
|
||
9
|
||
+1002.1K
|
||
+50
|
||
~CAPACITANCE (pf)
|
||
(CACTUAL -CSPEC)o -50.5-
|
||
>+10
|
||
~
|
||
...J
|
||
W
|
||
0
|
||
~0
|
||
::::>Q.
|
||
~
|
||
::::>-100
|
||
-13.tCY::::t03+tnt>2+t4>2+tf4>2+t02+tr4>1;>320ns.8080A
|
||
OUTPUT
|
||
TYPICAL!:J. OUTPUT DELAY VS.~CAPACITANCE
|
||
+20r-------.-----------r---- -----,A1S-AO~
|
||
twA
|
||
07-00I--
|
||
two
|
||
SYNC
|
||
oBIN
|
||
WR
|
||
toc
|
||
READY
|
||
WAIT
|
||
HOLDI-
|
||
HLoA
|
||
INT
|
||
INTE---.toc.--4.Thefollowing arerelevantwheninterfacing the8080AtodeviceshavingVIH::::3.3V:
|
||
a)Maximum outputrisetimefrom.8Vto3.3V=1OOns@CL=SPEC.
|
||
b)Outputdelaywhenmeasured to3.0V=SPEC+60ns@CL=SPEC.
|
||
c)IfCL:f.SPEC,add.6ns/pFifCL>CSPEC,subtract.3ns/pF(frommodified delay)ifCL<CSPEC.
|
||
5.tAW::::2tCY-t03-tnt>2-110nsec.
|
||
6.tOW::::tCY-t03-tr</>2-150nsec.
|
||
7.IfnotHLDA,tWO::::tWA::::t03+tr<P2+10ns.IfHLOA,tWO::::twA::::tWF.
|
||
8.tHF::::t03+tr<P2-50ns.
|
||
9.tWF=t03+tr4>2-10ns
|
||
10.DatainmustbestableforthisperiodduringDBIN·T3.BothtOS1andtOS2mustbesatisfied.
|
||
11.ReadysignalmustbestableforthisperiodduringT2orTW.(Mustbeexternally synchronized.)
|
||
12.HoldsignalmustbestableforthisperiodduringT2orTWwhenentering holdmode,andduringT3,T4,TS
|
||
andTWHwheninholdmode.(External synchronization isnotrequired.)
|
||
13.Interrupt signalmustbestableduringthisperiodofthelastclock cycle ofanyinstruction inordertobe
|
||
recognized onthefollowing instruction. (External synchronization isnotrequiredJ
|
||
14.Thistimingdiagramshowstimingrelationships only;itdoesnotrepresent anys~ificmachine cycle.
|
||
5-23
|
||
|
||
===PAGE 86===
|
||
infel® SiliconGateMOS8080A-2
|
||
SINGLE CHIPa-BITN-CHANNEL MICROPROCESSOR
|
||
•TTLDriveCapability
|
||
•1.5J.LsInstruction Cycle
|
||
•Powerful Problem Solving
|
||
Instruction Set
|
||
•SixGeneral Purpose Registers
|
||
andanAccumulator
|
||
•SixteenBitProgram Counter for
|
||
DirectlyAddressing upto64KBytes
|
||
ofMemory•SixteenBitStackPointerandStack
|
||
Manipulation Instructions forRapid
|
||
Switching of~heProgram Environment
|
||
•Decimal,Binary andDouble
|
||
Precision Arithmetic
|
||
•AbilitytoProvidePriorityVectored
|
||
Interrupts
|
||
•512DirectlyAddressed 1/0Ports
|
||
TheIntel®aOaOAisacomplete a-bitparallelcentralprocessing unit(CPU).Itisfabricated onasingleLSIchipusingIntel's
|
||
n-channel silicongateMOSprocess. Thisofferstheuserahighperformance solutiontocontrolandprocessing appli"cations.
|
||
TheaOaOAcontains sixa-bitgeneralpurposeworking registers andanaccumulator. Thesixgeneralpurpose registers maybe
|
||
addressed individually orinpairsproviding bothsingleanddoubleprecision operators. Arithmetic andlogicalinstructions set
|
||
orresetfourtestableflags.Afifthflagprovides decimalarithmetic operation.
|
||
TheaOaOAhasanexternal stackfeaturewherein anyportionofmemory maybeusedasalastin/firstoutstacktostore/
|
||
retrievethecontents oftheaccumulator, flags,program counterandallofthesixgeneralpurpose registers. Thesixteenbit
|
||
stackpointercontrols theaddressing ofthisexternal stack.ThisstackgivestheaOaOAtheabilitytoeasilyhandlemultiple
|
||
levelpriorityinterrupts byrapidlystoringandrestoring processor status.Italsoprovides almostunlimited subroutine nesting.
|
||
This microprocessor hasbeendesigned tosimplify systemsdesign.Separate 16-lineaddressanda-linebi-directional data
|
||
bussesareusedtofacilitate easyinterface tomemory andI/O.Signalstocontroltheinterface tomemory andI/Oarepro
|
||
videddirectlybytheaOaOA.Ultimate controloftheaddressanddatabussesresideswiththeHOLDsignal.Itprovides the
|
||
abilitytosuspend processor operation andforcetheaddressanddatabussesintoahighimpedance state.ThispermitsOR
|
||
tyingthesebusseswithothercontrolling devicesfor(DMA)directmemory accessormUlti-processor operation.
|
||
5-24
|
||
|
||
===PAGE 87===
|
||
SILICON GATEMOS8080A-2
|
||
ABSOLUTE MAXIMUM RATINGS·
|
||
Temperature UnderBias O°Cto+70°C
|
||
StorageTemperatu re... . . . . . . . . . . .._65°Cto+150°C
|
||
AllInputorOutputVoltages
|
||
WithRespecttoVas -0.3Vto+20V
|
||
Vee,VooandVssWithRespecttoVss -0.3Vto+20V
|
||
PowerDissipation . . . ...1.5W*COMMENT: Stressesabovethoselistedunder"Absolute Maxi
|
||
mumRatings" maycausepermanent damage tothedevice.
|
||
Thisisastressratingonlyandfunctional operation ofthede
|
||
viceattheseoranyotherconditions abovethoseindicated in
|
||
theoperational sectionsofthisspecification isnotimplied.Ex
|
||
posuretoabsolute maximum ratingconditions forextended
|
||
periodsmayaffectdevicereliability.
|
||
D.C.CHARACTERISTICS
|
||
TA=O°Cto70°C,VOO=+12V±5%,VCC=+5V±5%,Vas=-5V±5%,Vss=OV,UnlessOtherwise Noted.
|
||
Symbol Parameter Min. Typ. Max. Unit TestCondition
|
||
VILC ClockInputLowVoltage Vss-l Vss+0.8 V
|
||
V,HC ClockInputHighVoltage 9.0 Voo+l V
|
||
V,L InputLowVoltage Vss-l Vss+0.8 V
|
||
V,H InputHighVoltage 3.3 Vee+1 V
|
||
VOL OutputLowVoltage 0.45 V}IOL=1.9mAonalloutputs,
|
||
VOHOutputHighVoltage 3.7 VIOH=150tlA.
|
||
100(AV)Avg.PowerSupplyCurrent (Voo) 40 70mA
|
||
lee(AV)Avg.PowerSupplyCurrent(Vcc) 60 80mA}Operation
|
||
TCy=.38J,Lsec
|
||
'ss(AV)Avg.PowerSupplyCurrent(Vss) .01 1mA
|
||
IlL InputLeakage ±10 J1AVss~VIN~Vec
|
||
ICl ClockLeakage ±10 J1AVss~VeLocK ~Voo
|
||
lol[2] DataBusLeakage inInputMode -100 J1A VSS~VIN ~VsS+O.8V
|
||
-2.0 mA
|
||
Vss+O.8V~VIN ~Vee
|
||
IFlAddressandDataBusLeakage +10J1AVAOOR/OATA =Vec
|
||
DuringHOLD -100VAOOR/OATA =VSS+O.45V
|
||
CAPACITANCE
|
||
TA=25°C Vec=Voo=VSS=OV,VBS=-5V
|
||
Symbol Parameter Typ. Max. Unit TestCondition
|
||
Cq, ClockCapacitance 1725 pffc=1MHz
|
||
C,N InputCapacitance 610 pfUnmeasured Pins
|
||
COUT OutputCapacitance 10 20 pfReturned toVss
|
||
NOTES:
|
||
1.TheRESETsignalmustbeactiveforaminimum of3clockcycles.
|
||
2.WhenoBINishighandV,N>VIHaninternalactivepullupwill
|
||
beswitchedontotheDataBus.
|
||
3.AIsupply/ATA=-O.45%f C.TYPICAL SUPPLY CURRENT VS.
|
||
TEMPERATURE, NORMALIZED.[3]1.5,.....-----r-----or----_
|
||
to
|
||
Zwa::a:::>
|
||
(J1.0r------""""=-~---+__--~
|
||
>..J
|
||
Q"
|
||
Q"
|
||
:>
|
||
(I)
|
||
0.50-----+2.1-.5----+5"'-0---......J+
|
||
75
|
||
AMBIENT TEMPERATURE (OC)
|
||
DATABUSCHARACTERISTIC
|
||
DURING DBIN
|
||
MAX
|
||
5-25°o~--""""'-----_----3llo--
|
||
Vee
|
||
|
||
===PAGE 88===
|
||
SILICON GATEMOS8080A-2
|
||
A.C.CHARACTERISTICS
|
||
TA=O°Cto70°C,Vee=+12V±5%,VCC=+5V±5%,Vss=-5V±5%,Vss=OV,UnlessOtherwise Noted
|
||
Symbol Parameter Min.Max.Unit TestCondition
|
||
tCy[31 ClockPeriod .382.0/lsec
|
||
tr,tfClockRiseandFallTime 050nsec
|
||
t¢1 (j>1PulseWidth 60 nsec
|
||
!¢2 l/>2PulseWidth 175 nsec
|
||
t01 Delay(j>1to(j>2 0 nsec
|
||
t02 Delay<P2to<P1 70 nsec
|
||
t03 Delay~to(j>2LeadingEdges 70 nsec
|
||
tOA[2]AddressOutputDelayFrom(j>2 175nsec}CL=100pftoo[2]DataOutputDelayFrom(j>2 200nsec
|
||
toc[2]SignalOutputDelayFrom¢1,or(/>2(SYNC,WR,WAIT, HLOA) 120nsec}CL=50pf
|
||
tOF[2]DSINDelayFromlP2 25140nsec
|
||
tOI[1] DelayforInputBustoEnterInputMode tOFnsec
|
||
tOS1 DataSetupTimeDuringlP1andDBIN 20 nsec
|
||
TIMINGWAVEFORMS [14](Note:Timingmeasurements aremadeatthefollowing reference voltages: CLOCK"1"=8.0V
|
||
"0"=1.0V;INPUTS"1"=3.3V,"0"=0.8V;OUTPUTS "1"=2.0V,"0"=0.8V.)
|
||
'II tCY-I-.to,~
|
||
--.ift.,
|
||
~1 J f\ r~ }\ 71\
|
||
-4-t<t>2----'1
|
||
4~ }~~....-ll ~J- ~I- -
|
||
""<1>2 ~r-J ~ i ~H
|
||
...to3~1 --.1t02.-
|
||
---------------- ~
|
||
tAW--++---~·1
|
||
f4--tOO-'
|
||
) ~A!.A_O~T _,
|
||
iIIf--tow,---.-=t---..
|
||
-.toc1.- ~tocI-+-
|
||
-t-1P--------+~\1
|
||
OBIN /I-\- ------------------+----11 ......---+o-----++---+--+--++----t+"--t~tDF-.1SYNC--------- ......."""1--"i
|
||
A1S-Ao--------- ........--lr------
|
||
~tOA~
|
||
..-too-'I ~to!\.- ---ltoHI"'-
|
||
~ -~IJ.....-......---H--.~...-.x= 1-........ ~,...OATA IN@I
|
||
07.00---------oo+---....."rl- ....--------,...........J~-t-- ,.....
|
||
~tos11.-
|
||
~ ~tOS2-'
|
||
READY -X@t-;:r...
|
||
WAIT tH_--.__~_;__ ...lIl
|
||
toc--.1..- tH-.11.-
|
||
HOLD .-X@IX-----------------------------------------. ......tr~;....I~..,..I~-..........
|
||
HLOA-------------------------------------------,t"-f
|
||
_~LI~-"""""Ij,..
|
||
INT ~-----------------_-:-'Xr ~~tt,s!=-=
|
||
tH~...
|
||
INTE
|
||
5-26
|
||
|
||
===PAGE 89===
|
||
SILICON GATEMOS8080A-2
|
||
A.C.CHARACTERISTICS (Continued)
|
||
TA=O°Cto70°C,VOD=+12V±5%,Vee=+5V±5%,VBB=-5V±5%,Vss=OV,UnlessOtherwise Noted
|
||
Symbol Parameter Min.Max.Unit TestCondition
|
||
tOS2 DataSetupTimeto<P2DuringDBIN 130 nsec
|
||
toH[1]DataHoldTimeFrom</>2DuringDBIN [1] nsec
|
||
tiE[2]INTEOutputDelayFrom<P2 200nsec CL=50pf
|
||
tRS READYSetupTimeDuring<P2 90 nsec
|
||
tHS HOLDSetupTimetoep2 120 nsec
|
||
tiS INTSetupTimeDuring cfJ2(During <1>1inHaltMode) 100 nsec
|
||
tH HoldTimeFromep2(READY, INT,HOLD) 0 nsec
|
||
tFD DelaytoFloat During Hold(AddressandDataBus) 120nsec
|
||
tAW[2]AddressStablePriortoWR-[5] nsec
|
||
tow[2]OutputDataStablePriortoWR [6] nsec
|
||
tWD[2] OutputDataStableFromWR [7] nsec
|
||
tWA[2]AddressStableFromWR [7] nsecCL=100pf:Address, Data---CL=50pf:WR,HLDA,DBIN
|
||
tHF[2] HLDAtoFloatDelay [8] nsec
|
||
tWF[2] WRtoFloatDelay [9] nsec
|
||
tAH[2] AddressHoldTimeAfterDBINDuringHLDA -20 nsec-
|
||
+5V
|
||
TYPICAL ~OUTPUT DELAY VS.~CAPACITANCE
|
||
+20,....----.....-------,------y------.
|
||
+1002.1K
|
||
+50
|
||
~CAPACITANCE (pf)
|
||
(CACTUAL - CSPEC)o -50.=.
|
||
>+10«-Jw
|
||
0
|
||
t-O
|
||
:::>
|
||
Q..
|
||
t-
|
||
:::>-100
|
||
<13.tCY=t03+tr4>2+t4>2+tf4>2+t02+tr4>1~380ns.8080A
|
||
OUTPUTNOTES:
|
||
1.DatainputshouldbeenabledwithDBINstatus.Nobusconflictcanthenoccuranddataholdtimeisassured.
|
||
tOH=50nsortOF.whichever isless.
|
||
2.LoadCircuit.
|
||
t/),
|
||
A'S-AOto-
|
||
tWA
|
||
07-00,.-
|
||
two
|
||
SYNC
|
||
DBIN
|
||
WR
|
||
toc
|
||
READY
|
||
WAIT
|
||
HOLDI-
|
||
HLDA
|
||
INT
|
||
INTEI-...toc.-4.Thefollowing arerelevantwheninterfacing the8080AtodeviceshavingV,H=3.3V:
|
||
a)Maximum outputrisetimefrom.8Vto3.3V=100ns@CL=SPEC.
|
||
b)Outputdelaywhenmeasured to3.0V=SPEC+60ns @CL=SPEC.
|
||
c)IfCL#:SPEC,add.6ns/pFifCL>CSPEC,subtract.3ns/pF(frommodified delay)ifCL<CSPEC.
|
||
5.tAW=2tCY-t03-tr</>2-130nsec. .
|
||
6.tow=tCY-t03-tr4>2-170n5ec.
|
||
7.IfnotHLOA,two=twA=tD3+tr</>2+10n5.IfHLDA,two=twA=tWF.
|
||
8.tHF=t03+tr4>2-SOns.
|
||
9.twF=t03+trcf)2-10ns
|
||
10.DatainmustbestableforthisperiodduringDBIN°T3.BothtOS1andtOS2mustbesatisfied.
|
||
11.ReadysignalmustbestableforthisperiodduringT2orTW.(Mustbeexternally synchronized.)
|
||
12.HoldsignalmustbestableforthisperiodduringT2orTWwhenentering holdmode,andduringT3,T4,T5
|
||
andTWHwheninholdmode.(External synchronization isnotrequired.)
|
||
13.Interrupt signalmustbeuableduringthisperiodofthelastclockcycleofanyinstruction inordertobe
|
||
recognized onthefollowi,1g instruction. (External synchronization isnotrequired.)
|
||
14.Thistimingdiagramshowstimingrelationships only;itdoesnotrepresent anys~ificmachine cycle.
|
||
5-27
|
||
|
||
===PAGE 90===
|
||
|
||
|
||
===PAGE 91===
|
||
intel®.SiliconGateMOSM8080A
|
||
SINGLECHIP8-BITN-CHANNEL MICROPROCESSOR
|
||
•FullMilitaryTemperature Range
|
||
-55°Cto+125°C
|
||
•±10%PowerSupplyTolerance
|
||
• 2J-LsInstruction Cycle
|
||
•Powerful Problem Solving
|
||
Instruction Set
|
||
•SixGeneralPurpose Registers
|
||
andanAccumulator
|
||
•SixteenBitProgram Counterfor
|
||
DirectlyAddressing upto64KBytes
|
||
ofMemory•SixteenBitStackPointerandStack
|
||
Manipulation Instructions forRapid
|
||
Switching oftheProgram Environment
|
||
•Decimal,Binary andDouble
|
||
Precision Arithmetic
|
||
•AbilitytoProvidePriorityVectored
|
||
Interrupts
|
||
•512DirectlyAddressed I/OPorts
|
||
•TTLDriveCapability
|
||
TheIntel®MaOaOA isacomplete a-bitparallelcentralprocessing unit(CPU).Itisfabricated onasingleLSIchipusingIntel's
|
||
n-channel silicongateMaSprocess. Thisofferstheuserahighperformance solutiontocontrolandprocessing applications.
|
||
TheMaOaOA contains sixa-bitgeneralpurpose working registers andanaccumulator. Thesixgeneralpurpose registers maybe
|
||
addressed individually orinpairsproviding bothsingleanddoubleprecision operators. Arithmetic andlogicalinstructions set
|
||
orresetfourtestable flags.Afifthflagprovides decimalarithmetic operation.
|
||
TheMaOaOA hasanexternal stackfeaturewherein anyportionofmemory maybeusedasalastin/firstoutstacktostore/
|
||
retrievethecontents oftheaccumulator, flags,program counter andallofthesixgeneralpurpose registers. Thesixteenbit
|
||
stackpointercontrols theaddressing ofthisexternal stack.ThisstackgivestheMaOaOA theabilitytoeasilyhandlemultiple
|
||
levelpriorityinterrupts byrapidlystoringandrestoring processor status.Italsoprovides almostunlimited subroutine nesting.
|
||
Thismicroprocessor hasbeendesigned tosimplify systems design.Separate l6-lineaddressanda-linebi-directional data
|
||
bussesareusedtofacilitate easyinterface tomemory andI/O.Signalstocontroltheinterface tomemory andI/Oarepro
|
||
videddirectly bytheMaOaOA. Ultimate controloftheaddressanddatabussesresideswiththeHOLDsignal.Itprovides the
|
||
abilitytosuspend processor operation andforcetheaddressanddatabussesintoahighimpedance state.ThispermitsOR
|
||
tyingthesebusseswithothercontrolling devicesfor(DMA)directmemory accessormUlti-processor operation.
|
||
5-29
|
||
|
||
===PAGE 92===
|
||
SILICON GATEMOSM8080A
|
||
INSTRUCTION SET
|
||
Theaccumulator groupinstructions includearithmetic and
|
||
logicaloperators withdirect,indirect, andimmediate ad
|
||
dressingmodes.
|
||
Move,load,andstoreinstruction groupsprovidetheability
|
||
tomoveeither8or16bitsofdatabetween memory, the
|
||
sixworking registers andtheaccumulator usingdirect,in
|
||
direct,andimmediate addressing modes.
|
||
Theabilitytobranchtodifferent portions oftheprogram
|
||
isprovided withjump,jumpconditional, andcomputed
|
||
jumps.Alsotheabilitytocalltoandreturnfromsub
|
||
routines isprovided bothconditionally andunconditionally.
|
||
TheRESTART (orsinglebytecallinstruction) isusefulfor
|
||
interrupt vectoroperation.
|
||
Doubleprecision operators suchasstackmanipulation and
|
||
doubleaddinstructions extendboththearithmetic and
|
||
interrupt handling capability oftheMaOaOA. Theabilitytoincrement anddecrement memory, thesixgeneralregisters
|
||
andtheaccumulator isprovided aswellasextended incre
|
||
mentanddecrement instructions tooperateontheregister
|
||
pairsandstackpointer. Furthercapability isprovided by
|
||
theabilitytorotatetheaccumulator leftorrightthrough
|
||
oraroundthecarrybit.
|
||
Inputandoutputmaybeaccomplished usingmemory ad-.
|
||
dressesasI/Oportsorthedirectlyaddressed I/Oprovided
|
||
forintheMaOaOA instruction set.
|
||
Thefollowing specialinstruction groupcompletes the
|
||
Ma080A instruction set:theNOPinstruction, HALTtostop
|
||
processor execution andtheDAAinstructions providedeci
|
||
malarithmetic capability. STCallowsthecarryflagtobedi
|
||
rectlyset,andtheCMCinstruction allowsittobecomple
|
||
mented.CMAcomplements thecontents oftheaccumulator
|
||
andXCHGexchanges thecontents oftwo16-bitregister
|
||
pairsdirectly.
|
||
DataandInstruction Formats
|
||
DataintheM80aOA isstoredintheformof8-bitbinaryintegers. Alldatatransfers tothesystemdatabuswillbeinthe
|
||
sameformat.
|
||
ID7D6DsD4D3D2D1Dol
|
||
DATAWORD
|
||
Theprogram instructions maybeone,two,orthreebytesinlength. Multiple byteinstructions mustbestored
|
||
insuccessive wordsinprogram memory. Theinstruction formatsthendependontheparticularoperation
|
||
executed.
|
||
OneByteInstructions TYPICAL INSTRUCTIONS
|
||
I0706 05040302OLDOJ OPCOOE Registertoregist~r,memory refer-
|
||
ence,arithmetic orlogical,rotate,
|
||
return,push,pop,enableordisable
|
||
Interrupt instructions
|
||
TwoByteInstru·ctions
|
||
107D6D5D4D3D2D,DOIOPCODE
|
||
107D6D5D4D3D2D1DOIOPERAND Immediate modeorI/Oinstructions
|
||
ThreeByteInstructions
|
||
107D6Os0403D201DOIOPCODE Jump,callordirectloadandstore
|
||
107 DOILOWADDRESS OROPERAND 1instructions
|
||
D6Os0403O2D1
|
||
107D6Ds04D3D201DOIHIGHADDRESSOR OPERAND 2
|
||
FortheM80aOA alogic"1"isdefinedasahighlevelandalogic"0"isdefinedasalowlevel.
|
||
5-30
|
||
|
||
===PAGE 93===
|
||
SILICON GATEMOSM8080A
|
||
INSTRUCTION SET
|
||
Summary ofProcessor Instructions
|
||
Instruction Code(1) Clock(21 Instruction Code[n Clock(2)
|
||
Mnemonic Description 0706Os0403020,DoCycles Mnemonic Description 0706Os0403020100Cycles
|
||
MOVr1,r2Moveregistertoregister 01 0 0 0SSS5 RZ Returnonzero 110010 0 0 5/11
|
||
MOVM,rMoveregistertomemory 0111 0SSS7 RNZ Returnonnozero 1100 0 0 C05/11
|
||
MOVr,M Movememorytoregister 01 0 0 01 107 RP Returnonpositive 11 1 1 00 0 0 5/11
|
||
HlT Halt 011 1 01 107 RM Returnonminus 1 1 1 1 100 0 5/11
|
||
MVIr Moveimmediate register 0 0 00 01107 RPE Returnonparityeven 1 1 1 0 10 005/11
|
||
MVIM Moveimmediate memory 0 0 11011010 RPO Returnonparityodd 111 0 0 0005/11
|
||
INRrIncrement register 000001 0 0 5 RST Restart 1 1 A A A1 1 1 11
|
||
OCRrDecrement register 0000 01 015 IN Input 1101 101 1 10
|
||
INRMIncrement memory 0 0 1101 0010 OUT Output 1101001110
|
||
OCRMDecrement memory 0 0 1 1 01 0110 LXIBLoadImmediate register 0000 00 0110
|
||
ADOrAddregistertoA 100 0 0SSS4 PairB&C
|
||
ADCrAddregistertoAwithcarry 10 0 0 1SS S 4 LXI0Loadimmediate register 0 10
|
||
SUBrSubtractregisterfromA 10 0 1 0 S S S4 Pair0&E
|
||
SBBrSubtractregisterfromA 1 001 1SS S 4 LXIHLoadimmediate register 10
|
||
withborrow PairH&L
|
||
ANArAndregisterwithA 010 0 S S S 4 LXISP Loadimmediate stackpointer 0 0 10
|
||
XRArExclusive OrregisterwithA 01 0 1 S S S4 PUSHBPushregisterPairB&Con 00 11
|
||
ORArOrregisterwithA 01 1 0 SSS4 stack
|
||
CMPr CompareregisterwithA 01 1 1 SS S 4 PUSH0PushregisterPair0&Eon 11
|
||
ADDMAddmemorytoA 0 0 0 0 1107 stack
|
||
AOCMAddmemorytoAwithcarry 00011 107 PUSHHPushregisterPairH&Lon 11
|
||
SUBMSubtractmemoryfromA 0 0 101 107 stack
|
||
SBBMSubtractmemoryfromA 0 0 111107 PUSHPSWPushAandFlags 0 0 11
|
||
withborrow onstack
|
||
ANAM AndmemorywithA 010 0 POPBPopregisterpairB&Coff 0 10
|
||
XRAMExclusivearmemorywithA 0 1 0 0 stack
|
||
ORAMOrmemorywithA 01 1 0 POP0Popregisterpair0&Eoff 10
|
||
CMPM ComparememorywithA 01 1 0 stack
|
||
ADI Addimmediate toA 10 0 0 POPHPopregisterpairH&Loff 10
|
||
ACI Addimmediate toAwith 10 0 0 stack
|
||
carry POPPSWPopAandFlags 10
|
||
SUI Subtractimmediate fromA offstack
|
||
SBI Subtractimmediate fromA STA StoreAdirect 0 0013
|
||
withborrow LOA LoadAdirect 0 0013
|
||
ANI Andimmediate withA 0 0 XCHG Exchange 0&E,H&L 1 01 4
|
||
XRI Exclusive Orimmediate with 0 0 Registers
|
||
A XTHL Exchange topofstack,H&L111 0 001118
|
||
ORI Orimmediate withA 1 1 1 1 0 7 SPHL H&Ltostackpointer 111 1 10015
|
||
CPI Compareimmediate withA1 1 1 1 1 7 PCHL H&Ltoprogramcounter 111010 0 1 5
|
||
RLC RotateAleft 00 0 0 0 4 DADBAddB&CtoH&L 0000 10 0110
|
||
RRC RotateAright 0 0 0 0 1 4 DAD0Add0&EtoH&L 00 0 110 0 1 10
|
||
RAL RotateAleftthroughcarry 0 0 010 4 DADHAddH&LtoH&L 0010 10 0110RAR RotateArightthrough 00 0 1 1 4 DADSPAddstackpointertoH&l0 0 11 10 0110carrySTAXBStoreAindirect 000 0 00107JMP Jumpunconditional 0 0 0 01 1 10 STAX0StoreAindirect 00010 010 7JC Jumponcarry 01101010 LOAXBLoadAindirect 0000 1010 7JNC Jumponnocarry 010 0 1 010 LOAX0LoadAindirect 000110107JZ Jumponzero 00101010 INXBIncrement B&Cregisters 000 0 0 01 1 5JNZ Jumponnozero 00001010 INX0Increment 0&Eregisters 00 0 1 00 1 1 5JP Jumponpositive 1 1 001010 INXHIncrement H&Lregisters 00 1 000 1 1 5JM Jumponminus 11 101010 INXSPIncrement stackpointer 00 1 1 001 1 5JPE Jumponparityeven 10101010 OCXBDecrement B&C 0 0 0 0 1 0115JPO Jumponparityodd 10 0 0 1010 OCX0Decrement 0&E 0 0 0 1101 1 5CALL Callunconditional 0 0 110117 OCXHDecrement H&L 001010115CC Calloncarry 01 11 0011/17 OCXSPDecrement stackpointer 001110115CNC Callonnocarry 010 10011/17 CMA Complement A 0010 11114CZ Callonzero 0 0 1 1 0 0 11/17 STC Setcarry 001 1 01114CNZ Callonnozero 0 0 0 1 0011/17 CMC Complement carry 0011 11 114CP Callonpositive 110 10011/17 OAA DecimaladjustA 0 0 1 00 1 1 14CM Callonminus 1 1 1 1 0011/17 SHLD StoreH&ldirect 00 1 0 001016CPE Callonparityeven 101100llf17 LHlO LoadH&Ldirect 0 0 10 101016CPO Callonparityodd 100100l1f17 EI EnableInterrupts 1 1 1 1 10114RET Return 0 0 1 0 0110 01 Disableinterrupt 1 1 1100 1 1 4RC Returnoncarry 0110 005/11 NOP No-operation 000000 004RNC Returnonnocarry 0100005/11
|
||
NOTES: 1.DODorSSS-000B -001C -0100 -011E -100H -101L -110Memory -111A.
|
||
2.Twopossiblecycletimes,(5/11)indicate instruction cyclesdependent oncondition flags.
|
||
|
||
===PAGE 94===
|
||
SILICON GATEMOSM8080A
|
||
M8080A FUNCTIONAL PINDEFINITION
|
||
Thefollowing describes thefunction ofalloftheM8080A I/O
|
||
pins.Severalofthedescriptions refertointernal timingperiods.
|
||
A15-AO(output' three~state)
|
||
ADDRESS BUS;theaddressbusprovides theaddresstomemory
|
||
(upto64K8-bitwords)ordenotes theI/Odevicenumber forup
|
||
to256inputand256outputdevices. Aoistheleastsignificant
|
||
addressbit.
|
||
07-Do(input/output three-state)
|
||
DATABUS;thedatabusprovides bi-directional communication
|
||
between theCPU,memory, andI/Odevicesforinstructions and
|
||
datatransfers. Also,duringthefirstclockcycleofeachmachine
|
||
cycle,theM8080A outputs astatuswordonthedatabusthatde-
|
||
scribesthecurrent machine cycle.Doistheleastsignificant bit.
|
||
SYNC(output)
|
||
SYNCHRONIZING SIGNAL; theSYNCpinprovides asignalto
|
||
indicate thebeginning ofeachmachine cycle.
|
||
DBIN(output)
|
||
DATABUSIN;theDBINsignalindicates toexternal circuitsthat
|
||
thedatabusisintheinputmode.Thissignalshouldbeusedto
|
||
enablethegatingofdataontotheM8080A databusfrommemory
|
||
orI/O.
|
||
READY (input)
|
||
READY; theREADY signalindicates totheM8080A thatvalid
|
||
memory orinputdataisavailable ontheM8080A databus.This
|
||
signalisusedtosynchronize theCPUwithslowermemory orI/O
|
||
devices. Ifaftersending anaddressouttheM8080A doesnotre
|
||
ceiveaREADY input,theM8080A willenteraWAITstateforas
|
||
longastheREADY lineislow.READY canalsobeusedtosingle
|
||
steptheCPU.
|
||
WAIT(output)
|
||
WAIT;theWAITsignalacknowledges thattheCPUisinaWAIT
|
||
state.
|
||
WR(output)
|
||
WRITE; theWRsignalisusedformemory WRITEorI/Ooutput
|
||
control. ThedataonthedatabusisstablewhiletheWRsignalis
|
||
activelow(WR=0).
|
||
HOLD(input)
|
||
HOLD;theHOLDsignalrequests theCPUtoentertheHOLD
|
||
state.TheHOLDstateallowsanexternal devicetogaincontrol
|
||
oftheM8080A addressanddatabusassoonastheM8080A has
|
||
completed itsuseofthesebusesforthecurrentmachine cycle.It
|
||
isrecognized underthefollowing conditions:
|
||
•theCPUisintheHALTstate.
|
||
•theCPUisintheT2orTWstateandtheREADY signalisactive.
|
||
Asaresultofentering theHOLDstatetheCPUADDRESS BUS
|
||
(A15-Ao)andDATABUS(07-00)willbeintheirhighimpedance
|
||
state. TheCPUacknowledges itsstatewiththeHOLDAC
|
||
KNOWLEDGE (HLDA) pin.
|
||
HLDA(output)
|
||
HOLDACKNOWLEDGE; theHLDAsignalappears inresponse
|
||
totheHOLDsignalandindicates thatthedataandaddressbus1 40 All
|
||
2 39 A14
|
||
3 38 A13
|
||
4 37 A12
|
||
5 36oA1S
|
||
6 35oAg
|
||
7 34 As
|
||
8INTE~33oA7
|
||
9M8080A32 A6
|
||
10 31 As
|
||
11 30oA4
|
||
12 29 A3
|
||
13 28 +12V
|
||
14 27 A2
|
||
15 26 Al
|
||
16 25 Ao
|
||
17 24 WAIT
|
||
WR 18 23 READY
|
||
SYNC 19 22 ¢l
|
||
+5V 20 21 HLDA
|
||
PinConfiguration
|
||
willgotothehighimpedance state.TheHLOAsignalbegins at:
|
||
•T3forREADmemory orinput.
|
||
•TheClockPeriodfollowing T3forWRITEmemory orOUT
|
||
PUToperation.
|
||
Ineithercase,theHLOAsignalappearsaftertherisingedgeof(/)1
|
||
andhighimpedance occursaftertherisingedgeof(/)2.
|
||
INTE(output)
|
||
INTERRUPTENABLE;indicates thecontentoftheinternal inter
|
||
ruptenableflip/flop. Thisflip/flop maybesetorresetbytheEn
|
||
ableandDisable Interrupt instructions andinhibits interrupts
|
||
frombeingaccepted bytheCPUwhenitisreset.Itisauto
|
||
matically reset(disabling furtherinterrupts) attimeT1ofthein-
|
||
struction fetchcycle(M1)whenaninterrupt isaccepted andis
|
||
alsoresetbytheRESETsignal.
|
||
INT(input)
|
||
INTERRUPT REQUEST; theCPUrecognizes aninterrupt re
|
||
questonthislineattheendofthecurrent instruction orwhile
|
||
halted.IftheCPUisintheHOLDstateoriftheInterrupt Enable
|
||
flip/flop isresetitwillnothonortherequest.
|
||
RESET(input)[1]
|
||
RESET; whiletheRESET signalisactivated, thecontent ofthe
|
||
program counter iscleared. AfterRESET, theprogram willstart
|
||
atlocation 0inmemory. TheINTEandHLDAflip/flops arealso
|
||
reset.Notethattheflags,accumulator, stackpointer, andregisters
|
||
arenotcleared.
|
||
VssGround Reference
|
||
Vee+12Volts±10%.
|
||
Vee+5Volts±10%.
|
||
Vss-5Volts±10%.
|
||
¢1,¢22externally supplied clockphases.(nonTTLcompatible)
|
||
5-32
|
||
|
||
===PAGE 95===
|
||
SILICON GATEMOSM8080A
|
||
ABSOLUTE MAXIMUM RATINGS*
|
||
Temperature UnderBias -55°Cto+125°C
|
||
StorageTemperatu re... . . . . . . . . . . . . _65°Cto+150°C
|
||
AllInputorOutputVoltages
|
||
WithRespecttoVBB -0.3Vto+20V
|
||
Vcc,VooandVssWithRespecttoVBB -0.3Vto+20V
|
||
PowerDissipation . . . . . . . . . . . ..1.7W*COMMENT: Stressesabovethoselistedunder"Absolute Maxi
|
||
mumRatings" maycausepermanent damagetothedevice.
|
||
Thisisastressratingonlyandfunctional operation ofthede
|
||
viceattheseoranyotherconditions abovethoseindicated in
|
||
theoperational sectionsofthisspecification isnotimplied.Ex
|
||
posuretoabsolute maximum ratingconditions forextended
|
||
periodsmayaffectdevicereliability.
|
||
D.C.CHARACTERISTICS
|
||
TA=-55°Cto+125°C, VOD=+12V±10%,Vee=+5V±10%,VBB=-5V±10%,Vss=OV,UnlessOtherwise Noted.
|
||
Symbol Parameter Min. Typ. Max. Unit TestCondition
|
||
VILC ClockInputLowVoltage Vss-l Vss+0.8 V
|
||
VIHC ClockInputHighVoltage 8.5 Voo+1 V
|
||
VIL InputLowVoltage Vss-l Vss+0.8 V
|
||
VIH InputHighVoltage 3.0 Vcc+1 V
|
||
VOL OutputLowVoltage 0.45 V}IOL=1.9mAonalloutputs,
|
||
VOHOutputHighVoltage 3.7 VIOH=150J-lA.
|
||
IOD(AV) Avg.PowerSupplyCurrent(Voo) 50 80rnA
|
||
ICC(AV)Avg.PowerSupplyCurrent(Vec) 60100 mA}Operation
|
||
TCy=.48J.1.sec
|
||
IBB(AV) Avg.PowerSupplyCurrent(VBB) .01 1mA
|
||
IlL InputLeakage ±10 J1AVss~VIN~Vcc
|
||
ICL ClockLeakage ±10 J1AVss~VCLOCK ~VDD
|
||
IDL[2]DataBusLeakage inInputMode -100 J1A VSS~VIN~VSS+O.~V
|
||
-2.0 rnAVSS+0.8V ~VIN~VCC
|
||
IFLAddressandDataBusLeakage +10
|
||
J1AVADDR/DATA =VCC
|
||
DuringHOLD -100VADDR/DATA =Vss+O.45V
|
||
+125
|
||
AMBIENT TEMPERATURE rc)+50 -55TYPICAL SUPPLY CURRENT VS.
|
||
TEMPERATURE, NORMALIZEO.l3]1.5,.....------r-----------,
|
||
I
|
||
2
|
||
~1.0J---------:::::l~I------______I
|
||
a:
|
||
:::>u
|
||
>...J8:0.5t------J-------______I
|
||
:::>enSymbol Parameter Typ. Max. Unit TestCondition
|
||
C¢ ClockCapacitance 17 25 pffc=1MHz
|
||
CIN InputCapacitance 610 pfUnmeasured Pins
|
||
COUTOutputCapacitance 10 20 pfReturned toVss
|
||
NOTES:
|
||
1.TheRESETsignalmustbeactiveforaminimum of3clockcycles.
|
||
2.WhenDBINishighandVIN>VIHaninternalactivepullupwill
|
||
beswitchedontotheOataBus.
|
||
3.~Isupply/~TA=-0.45%/ C.CAPACITANCE
|
||
TA=25°C Vec=VOD=Vss=OV,VBB=-5V
|
||
DATABUSCHARACTERISTIC
|
||
DURING DBIN
|
||
MAX
|
||
°0"----------------------30--
|
||
Vee
|
||
|
||
===PAGE 96===
|
||
SILICON GATEMOSM8080A
|
||
A.C.CHARACTERISTICS (Continued)
|
||
TA=-55°Cto+125°C, VOO=+12V±10%,Vee=+5V±10%,VBB=-5V±10%,Vss=OV,UnlessOtherwise Noted.
|
||
Symbol Parameter Min.Max.Unit TestCondition
|
||
tOS2 DataSetupTimeto¢2DuringDBIN 130 nsee
|
||
tOH[1]DataHoldTimeFrom¢2DuringDBIN 50 nsee
|
||
tiE(2)INTEOutputDelayFrom¢2 200nsee CL=50pf
|
||
tRS READY SetupTimeDuring¢2 120 nsee
|
||
tHS HOLDSetupTimeto¢2 140 nsee
|
||
tiS INTSetupTimeDuring¢2(During 4>1inHaltMode) 120 nsee
|
||
tH HoldTimeFrom¢2(READY, INT,HOLD) 0 nsee
|
||
tFD DelaytoFloatDuringHold(AddressandDataBus) 130nsee
|
||
tAW[2]AddressStablePriortoWR-[5] nsee
|
||
tDW[2] OutputDataStablePriortoWR [6] nsee
|
||
tWD[2] OutputDataStableFromWR [7] nsee
|
||
tWA[2]AddressStableFromWR [7] nsee~CL=50pf
|
||
tHF[2] HLOAtoFloatDelay [8] nsee
|
||
tWF[2] WRtoFloatDelay [9] nsee
|
||
tAH[2]AddressHoldTimeAfterDBINDuringHLDA -20 nsee-
|
||
NOTES:
|
||
1.DatainputshouldbeenabledwithOBINstatus.Nobusconflictcanthenoccuranddataholdtimeisassured.
|
||
tOH=50nsortOF,whichever isless.
|
||
2.LoadCircuit.
|
||
+5V
|
||
8080A
|
||
OUTPUT
|
||
3.tey=t03+trq,2+tq,2+tfq,2+tD2+trq,l~480ns.
|
||
+100 +50
|
||
~CAPACITANCE(pf)
|
||
(CACTUAL -CSPEC)o -50oS
|
||
>+10«
|
||
..Jw
|
||
0
|
||
....0
|
||
:::J
|
||
Q.....
|
||
:::J-100
|
||
-1
|
||
-20
|
||
-100TYPICAL ~OUTPUT DELAY VS.~CAPACITANCE
|
||
+20r-----~---~---_---_..........
|
||
~--- .......----- .....---
|
||
DBINSYNC
|
||
READY
|
||
WAIT
|
||
HOLDfa-
|
||
HLDA
|
||
INT
|
||
INTE~toe'-4.Thefollowing arerelevantwheninterfacing theM8080A todeviceshavingVIH=3.3V:
|
||
a)Maximum outputr'isetimefrom.8Vto3.3V=lOOns@CL=SPEC.
|
||
b)Outputdelaywhenmeasured to3.0V=SPEC+60n5 @CL=SPEC.
|
||
dIfCL*SPEC,add.6ns/pFifCL>CSPEC,subtract .3n5/pF(frommodified delay)ifCL<CSPEC.
|
||
5.tAW=2tey-t03-trct>2-140nsec.
|
||
6.tow=tCY-t03-trep2-170nsec.
|
||
7.IfnotHLOA,two=tWA=t03+tr¢2+10ns.IfHLOA,two=tWA=tWF·
|
||
8.tHF=t03+trq,2-50ns.
|
||
9.tWF=tD3+tr<t>2-10ns
|
||
10.DatainmustbestableforthisperiodduringDBIN·T3.BothtOS1andtOS2mustbesatisfied.
|
||
11.Readysignalmustbestableforthisperio~duringT2orTW.(Mustbeexternally synchronized.)
|
||
12.HoldsignalmustbestableforthisperiodduringT2orTWwhenentering holdmode,andduringT3,T4,T5
|
||
andTWHwheninholdmode.(External synchronization isnotrequired.~
|
||
13.Interrupt signalmustbestableduringthisperiodofthelastclockcycleofanyinstruction inordertobe
|
||
recognized onthefollowing instruction. (External synchronization isnotrequired.)
|
||
14.Thistimingdiagram showstimingrelationships only;itdoesnotrepresent anyspecificmachine cycle.
|
||
5-34
|
||
|
||
===PAGE 97===
|
||
SILICONGATEMOSM8080A
|
||
A.C.CHARACTERISTICS
|
||
TA=-55°Cto+125°C, Voo=+12V±10%,Vee=+5V±10%,VBB=-5V±10%,Vss=OV,UnlessOtherwise Noted.
|
||
Symbol Parameter Min.Max.Unit TestCondition
|
||
tCy[3] ClockPeriod 0.482.0Jisec
|
||
tr,tfClockRiseandFallTime 050nsec
|
||
t(/>l eplPulseWidth 60 nsec
|
||
tep2 cI>2PulseWidth 220 nsec
|
||
t01 Delayeplto4>2 0 nsec
|
||
t02 Delay ~2to~1 80 nsec
|
||
t03 Delay ~1to~2LeadingEdges 80 nsec-tOA[2)AddressOutputDelayFrom ~2 200nsec
|
||
too[2]DataOutputDelayFrom ~2 220nsec
|
||
toc[2]SignalOutputDelayFrom ~1,or~2(SYNC,WR,WAIT,HLDA) 140nsec
|
||
tOF[2]DBINDelayFromep2 25150- CL=50pf
|
||
nsec-
|
||
tOI[l) DelayforInputBustoEnterInputMode tOFnsec
|
||
tOSl DataSetupTimeDuring ~1andDBIN 30 nsec
|
||
TIMINGWAVEFORMS [14](Note:Timingmeasurements aremadeatthefollowing reference voltages: CLOCK"1"=7.0V,
|
||
"0"=1.0V;INPUTS"1"=3.0V,"0"=0.8V;OUTPUTS "1"=2.0V,"0"=0.8V.)
|
||
SYNC
|
||
DBIN
|
||
READY
|
||
WAIT
|
||
HOLD
|
||
HLDA
|
||
INT
|
||
INTE.. ·tey-\--.
|
||
1011---.F\I01
|
||
I f\ r~t\ Jf\
|
||
...-to2-"1
|
||
....,~
|
||
7~~~~
|
||
I~~ r-..,
|
||
-J~.....~r....to3.....!--.1t02.--
|
||
.I--x .-=1~~ - -----~--- ~---------
|
||
...-tOA-'! -- ~tAW
|
||
.--too--'I -.to!1'- --ttoHI4--f.--tOO-' i
|
||
I...r_I) __+:=:J~~A I~~DATAOUT-------'osl1=-1~-----------f
|
||
..~tow~i!T-\- ..-tOS2-'i
|
||
-.toc14- --.tocl..- I
|
||
~ t I
|
||
~toF-.1 ....toF~1 !
|
||
~tI
|
||
-~~--------toc~I
|
||
L ,tHil'-
|
||
------------~@r-&~~I II --IRS""':' loe-II tRsl~
|
||
tH--..--1-li
|
||
toc-"'" _ tH-.;1·-
|
||
I@I~
|
||
--.r~;I~
|
||
-I~[I-
|
||
~~
|
||
tH~....
|
||
5-35
|
||
|
||
===PAGE 98===
|
||
|
||
|
||
===PAGE 99===
|
||
8702A
|
||
8704
|
||
8708ROMs
|
||
8302
|
||
8308
|
||
8316A
|
||
|
||
===PAGE 100===
|
||
|
||
|
||
===PAGE 101===
|
||
SiliconGateMOS8702A
|
||
2048BITERASABLE ANDELECTRICALLY
|
||
REPROGRAMMABLE READONLYMEMORY
|
||
•InputsandOutputsTTLCompatible
|
||
•Three-State Output-OR-Tie
|
||
Capability
|
||
•SimpleMemoryExpansion Chip
|
||
SelectInputLead•AccessTime-1.3 ~sec
|
||
Max.
|
||
•FastProgramming - 2Minutesfor
|
||
All2048Bits
|
||
•FullyDecoded, 256x 8Organization
|
||
•StaticMOS-NoClocksRequired
|
||
The8702Aisa256wordby8bitelectrically programmable ROMideallysuitedformicrocomputer system
|
||
development wherefastturn-around andpatternexperimentation areimportant. The8702Aundergoes
|
||
complete programming andfunctional testingoneachbitpositionpriortoshipment, thusinsuring100%
|
||
programmability.
|
||
The8702Aispackaged ina24pindual-inlinepackagewithatransparent quartzlid.Thetransparent quartz
|
||
lidallowstheusertoexposethechiptoultraviolet lighttoerasethebitpattern. Anewpatterncanthenbe
|
||
writtenintothedevice.Thisprocedure canberepeated asmanytimesasrequired.
|
||
Thecircuitryofthe8702Aisentirelystatic;noclocksarerequired.
|
||
Apin-for-pin metalmaskprogrammed ROM,theIntel8302,isidealforlargevolumeproduction runs ~f
|
||
systemsinitiallyusingthe8702A.
|
||
The8702Aisfabricated withsilicongatetechnology. Thislowthreshold technology allowsthedesignand
|
||
production ofhigherperformance MOScircuitsandprovides ahigherfunctional densityonamonolithic
|
||
chipthanconventional MOStechnologies.
|
||
PINCONFIGURATION BLOCKDIAGRAM
|
||
OUTPUT
|
||
BUFFERS
|
||
2048BIT
|
||
PROMMATRIX
|
||
(256X8)DATAOUT1DATAOUT8
|
||
PROGRAM ........A2Voo
|
||
A, Vee
|
||
Ao Vee
|
||
*DATAOUT1 A3
|
||
*DATAOUT2 A4
|
||
*DATAOUT3 As
|
||
*DATAOUT4 A6
|
||
*DATAOUT5 A7
|
||
*DATAOUT69 16VGG
|
||
*DATAOUT710 15Vee
|
||
*DATAOUT811(MSB) 14CS
|
||
Vee 12 13PROGRAM
|
||
*THISPINISTHEDATAINPUTLEADDURING PROGRAMMING.
|
||
PINNAMES
|
||
Ao-A7 ADDRESS INPUTS
|
||
CS CHIPSELECT INPUT
|
||
001-002 DATAOUTPUTS
|
||
5-37
|
||
|
||
===PAGE 102===
|
||
SILICON GATEMOS8702A
|
||
PINCONNECTIONS
|
||
Theexternal leadconnections tothe8702Adiffer,depending onwhether thedeviceisbeingprogrammed (1)orusedinread.
|
||
mode.(Seefollowing table.)
|
||
1213 1415 16 2223
|
||
MODE .(Vee) (Program) (CS)· (VBB)(VGG) (Vee)(Vee)
|
||
Read Vee Vee GND Vee VGG Vee Vee
|
||
Programming GND Program PulseGND Vee PulsedVGG(V,L4P)GNDGND
|
||
ABSOLUTE MAXIMUM RATINGS·
|
||
Ambient Temperature UnderBias OOCto+700C
|
||
StorageTemperature -65°Cto+1250C
|
||
Soldering Temperature ofLeads(10sec). . . . . ...+300oC
|
||
PowerDissipation 2Watts
|
||
ReadOperation: InputVoltages andSupply
|
||
Voltages withrespecttoVee +0.5Vto-20V
|
||
Program Operation: InputVoltages andSupply
|
||
Voltages withrespecttoVee -48V*COMMENT
|
||
Stresses abovethoselistedunder"Absolute Maximum Rat
|
||
ings"maycausepermanent damagetothedevice.Thisisa
|
||
stressratingonlyandfunctional operation ofthedeviceat
|
||
theseoratanyothercondition abovethoseindicated in
|
||
theoperational sectionsofthisspecification isnotimplied.
|
||
Exposure toAbsolute Maximum Ratingconditions forex
|
||
tendedperiodsmayaffectdevicereiiability.
|
||
READOPERATION
|
||
D.C.ANDOPERATING CHARACTERISTICS
|
||
. (2) .
|
||
TA=aocto70oC,Vee=+5V±5%, Voo=-9V±5%, VGG=-9V±5%, unlessotherwise noted.
|
||
SYMBOL TEST MIN.TypJ3)MAX.UNIT CONDITIONS
|
||
III Address andChipSelect 10 fJAVIN=O.OV
|
||
InputLoadCurrent
|
||
IlOOutputLeakage Current 10 JJA-VOUT=O.OV,CS= Vee-2
|
||
1000PowerSupplyCurrent 5 10mAVGG=Vee,CS=Vee-2
|
||
10l=O.OmA,TA=2Soc
|
||
1001PowerSupplyCurrent 35 SO mACS=Vcc-2 ""'"
|
||
10l=O.OmA, TA=2SoC
|
||
1002PowerSupplyCurrent 32 46 mACS=O.O
|
||
10l=O.OmA, TA=2SoC
|
||
>Continuous
|
||
1003PowerSupplyCurrent 38.5 60 mACS=Vec-2
|
||
10l=O.OmA , TA=OOCOperation
|
||
leF1OutputClampCurrent 8 14mAVOUT=-l.QV,TA=OOC
|
||
leF2OutputClampCurrent 13mAVOUT=-1.0V,TA=2SoC
|
||
~
|
||
IGGGateSupplyCurrent 10 fJA
|
||
V,l1InputLowVoltagefor-1.0 0.65 V
|
||
nLInterface
|
||
V1L2InputLowVoltageforVoo Vec-6V
|
||
MOSInterface
|
||
V1HAddress andChipSelect Vcc-2 Vee+0.3 V
|
||
InputHighVoltage
|
||
IOlOutputSinkCurrent 1.6 4 mAVOUT=0.45V
|
||
VOLOutputLowVoltage -.7 0.45 VIOl=1.6mA
|
||
VOHOutputHighVoltage 3.5 VIOH=-2001lA
|
||
Note1:Intheprogramming mode,thedatainputs1-8arepins4-11respectively. es=GNO.
|
||
Note2:VGGmaybeclockedtoreducepowerdissipation. Inthismodeaverage100increasesinproportion toVGGdutycycle.(Seep.5)
|
||
Note3:TypicalvaluesareatnominalvoltagesandTA=250C.
|
||
5-38
|
||
|
||
===PAGE 103===
|
||
SILICON GATEMOS8702A
|
||
A.C.CHARACTERISTICS
|
||
TA=00Cto+70°C,Vcc=+5V±5%,Voo=-9V±5%,VGG=-9V±5%unlessotherwise noted
|
||
SYMBOL TEST MINIMUM TYPICAL MAXIMUM UNIT
|
||
Freq. Repetition Rate 1 MHz
|
||
tOH Previousreaddatavalid 100 ns
|
||
tAcc Addresstooutputdelay 1.3 p.s
|
||
tovGGClockedVGGsetup[2] 1.0 JlS
|
||
tesChipselectdelay 400 ns
|
||
teo OutputdelayfromCS 900 ns
|
||
too Outputdeselect 400 ns
|
||
tOHC DataoutholdinclockedVGGmode(Note1) 5 JlS
|
||
Note1.TheoutputwillremainvalidfortOHeaslongasclocked VGGisatVee.Anaddress changemayoccurassoonastheoutputissensed
|
||
(clocked VGGmaystillbeatVee).Databecomes invalidfortheoldaddresswhenclocked VGGisreturned toVGG.
|
||
2.Forthisoptionpleasespecify8702AL
|
||
CAPACITANCE*
|
||
SYMBOL TEST MINIMUM TYPICAL MAXIMUM UNIT CONDITIONS
|
||
C1NInputCapacitance 8 15 pF'1N=Vee}All
|
||
COUTOutputCapacitance 10 15 pFCS=Vceunusedpins
|
||
CVGGVGGCapacitance 30 pFVOUT=VeeareatA.C.
|
||
(Clocked VGGMode)VGG=Vceground
|
||
~Thisparameter isperiodically sampled andisnot100%tested.
|
||
~~Ons
|
||
L·'·';I I
|
||
I\--
|
||
----:I
|
||
tOD~
|
||
~50nsI
|
||
NOTE2 -,,,,r---;;......---7DATA
|
||
OUTB)ClockedVGGOperation
|
||
'- CYCLE: TIME-1FREO ~
|
||
VIHXI,0"lo xl
|
||
ADDRESS ~ I
|
||
._90% • • V1LI------------..J I~---
|
||
I 1
|
||
Cs'VIH\1
|
||
11 :
|
||
I---~Ons_____'
|
||
I
|
||
V1L\1--------11----------
|
||
-II.-tDV:
|
||
Vcc\~: GGJ
|
||
CLOCKED"I/:
|
||
VGG
|
||
Vee;I: :(SEENOTE 11r---- tACC----i-I~.'OHC
|
||
I I
|
||
I I
|
||
II
|
||
DATA~~~: \ {'
|
||
:.-tACC---\ VOl~ • ..J
|
||
NOTE1:TheoutputwillremainvalidtortOHeaslongasclocked VGG
|
||
isatVee.Anaddress changemayoccurassoonastheoutput issensed
|
||
(clocked VGGmaystillbeatVee!.Databecomes invalidfortheold
|
||
address whenclocked VGGisreturned toVGG'
|
||
~OTE2:ItCSmakesatransition fromVILtoVIHwhileclocked VGG
|
||
ISatVGG.thendeselection ofoutput occursattooasshowninstatic
|
||
operation withconstant VGG.V
|
||
,Hv:DESELECTIDN OFDATAOUTPUT INDR·TlEOPERATION
|
||
ADDRESS.A
|
||
V1L1-----------------
|
||
I
|
||
I
|
||
CSV,H'\
|
||
V1LI
|
||
~~t
|
||
VCC,\': DVGG
|
||
CLOCKED :: /
|
||
VGG I
|
||
VGGI"tl------JI
|
||
I
|
||
IVOH7
|
||
DATA l
|
||
OUTI
|
||
V1H){~10%--XI
|
||
ADDRESS I
|
||
~90%
|
||
V1lI.....------------J, .......----
|
||
----Itcs~ I
|
||
_V1Hill t--toH--1
|
||
cs I I ':
|
||
V1l : I
|
||
I
|
||
I
|
||
I,CYCLE TIME I/FREO
|
||
V1H---f10%
|
||
cs
|
||
V1l
|
||
I
|
||
VOH---fe'I -too-
|
||
IVDATA I
|
||
OUT I
|
||
VOLI
|
||
-lteof-Conditions ofTest:
|
||
Inputpulseamplitudes: 0to4V;tR'tF::;50ns.
|
||
Outputloadis1TTLgate;measurements made
|
||
atoutputofTTLgate(tpD~15ns)
|
||
A)Constant VGGOperationSWITCHING CHARACTERISTICS
|
||
5-39
|
||
|
||
===PAGE 104===
|
||
SILICON GATEMOS8702A
|
||
TYPICAL CHARACTERISTICS
|
||
'00CURRENT VS.TEMPERATUREOUTPUT CURRENT VS.
|
||
VDOSUPPLY VOLTAGEOUTPUT CURRENT VS.
|
||
TEMPERATURE
|
||
I'\Vee=+5V-
|
||
r\voo=-9V
|
||
-r\\ Vaa=-9V
|
||
'\INPUTS" Vee-
|
||
I\.
|
||
\f'\OUTPUTS AREOPEN
|
||
I I I
|
||
I"'"I
|
||
~NS=V ee
|
||
I"I" I---~'l
|
||
CS=0.0V'-~
|
||
I--~
|
||
I_.-.~
|
||
AMBIENT TEMPERATURE (OCI39
|
||
38
|
||
37
|
||
36
|
||
35134
|
||
~33
|
||
~32
|
||
=>u31
|
||
o
|
||
_030
|
||
29
|
||
28
|
||
27
|
||
20406080100120VCC'"+5V
|
||
VGG'"-9V---b,......:::=I===:t __ F=l~--1
|
||
VOL
|
||
TA
|
||
~! -5-6-7-8
|
||
I- VooSUPPLY VOLTAGE (V)
|
||
~-3 I I
|
||
~ VCC=+SVa VGG'"-9V-I-~~iii'it---I-----j
|
||
~ VOH'"O.OV
|
||
=> TA'"25°C
|
||
~-3.5t--+-~ -+-_~M--+----i
|
||
I-
|
||
~l
|
||
=>o
|
||
%2-4L-_"""'--_ .........._............_.........._----'__L.-----'~!
|
||
I-
|
||
ffia:a:
|
||
=>u
|
||
~z
|
||
en
|
||
l-i:...
|
||
:;)
|
||
0
|
||
~
|
||
.P
|
||
~!
|
||
I-
|
||
ffia:a:
|
||
=>u.
|
||
wu-3a:
|
||
=>0en
|
||
l-i:...
|
||
=>0
|
||
%_0-4II,
|
||
~Vee"+5V
|
||
~~Voo:l-9V
|
||
Vaa:l-9V
|
||
"~VOL"+.45V-..-
|
||
cs=o.~t'-..................I I
|
||
Ido 0102030 5060708090IAjBIENT TEMPERATURE (oCI
|
||
IVee'+5VI
|
||
Voo=-9V I
|
||
I---I-Vaa=-9V
|
||
VOH=O.OV
|
||
~--~~I---I---~rr
|
||
OUTPUT SINKCURRENT
|
||
VS.OUTPUT VOLTAGE
|
||
!!IIIII -LiCLOCKED VGG.,-9VII'"-9V-i.-I Voo
|
||
[ ~1.--""~I cs'"V1H
|
||
T4'"25°C.--V~I
|
||
~".,.-iI-'I
|
||
~........................Ii f-~I!
|
||
II-V i
|
||
V~
|
||
I~r,I----: ! i
|
||
100 90 80 70 40 50 60
|
||
DUTYCYCLE 1%)30AVERAGE CURRENT VS.DUTY
|
||
CYCLEFORCLOCKED VGG
|
||
20 10oo +3+4 +1+245
|
||
~VCC'"+5V!12.0 40... VDD'"-9V
|
||
~ VGG'"-9V 100135a:10.0a: TA'"25°C ~=>!30u I
|
||
f--:ll:8.0 025 Z..FenCS'"O.OV w
|
||
-I-6.0C)20
|
||
~c(
|
||
ffi=>>150c(
|
||
10
|
||
'0005
|
||
OUTPUT VOLTAGE (VOLTS)-2-1 -3-4
|
||
ACCESS TIMEVS.
|
||
LOADCAPACITANCEACCESS TIMEVS.
|
||
TEMPERATURE
|
||
1400----.,..-.,.----.,..-~--r--r---r--r-__r____, 1400---.--..----.--..----r--r--,--r---r----,
|
||
1300~-I--~_l_-~_+_-f--_+___If----+-___i 1300~--+--+-__+_-t-__+_-t--t--+---+----t
|
||
1200~--+--f--__+_-f--_+_-f----+-__If----+---i 1200~-4--.j-~-.j_~-t---+--+----t-----1
|
||
800~-+~I---+-____4--+-
|
||
500I---I--~-l--~_+_-t--__+_-f---t-___i1100'----+--.j--+-+--~-+---t--+---+-----i
|
||
c:1000L---L-L-~~~~~r::+=r--+----1
|
||
1TTLLOAD::. 20pf
|
||
700I---t--+--+--t- Vee=+5V
|
||
600...--t--+---t--t- Vee=-9V
|
||
VGG=-9V
|
||
500~-+--+--+--~__+_-f---t--t---+----t1100 ~-4--.j-~-+---+--t---+--+----t-----1
|
||
c: _.....-~~.....-~
|
||
~1000~-;.-~=f--+---+--+---+---t---t----1
|
||
:E
|
||
~900~-+----f---t--+---t--+--_t_-t---t----t
|
||
CI.l
|
||
~u800~~-+---4--+--~-+---+--+---t-----t
|
||
U«1TTLLOAD-f
|
||
Vee=+5V
|
||
700~-4---11---+----+--+-- Voo=-9V-f-
|
||
6001---4----+--+---+--t- VGG=-9V--
|
||
TA=25°Cw
|
||
:E
|
||
~900I---I--~_l_-~_l_-~__+_-f--_t____i
|
||
~w
|
||
UUc(
|
||
00102030405060708090100
|
||
LOADCAPACITANCE (pF)102030405060708090
|
||
AMBIENT TEMPERATURE rc)
|
||
5·40
|
||
|
||
===PAGE 105===
|
||
SILICON GATEMOS8702A
|
||
PROGRAMMING OPERATION
|
||
D.C.ANDOPERATING CHARACTERISTICS FORPROGRAMMING OPERATION
|
||
TA=25°C,Vee=OV,Vss=+12V±10%,CS=OVunlessotherwise noted
|
||
SYMBOL TEST MIN. TYP. MAX. UNIT CONDITIONS
|
||
ILl1PAddressandDataInput 10 rnA VIN=-48V
|
||
LoadCurrent
|
||
'LI2P Program andVGG 10 rnA VIN=-48V
|
||
LoadCurrent
|
||
'ssVssSupplyLoadCurrent .05 rnA
|
||
IOOp(l) Peak100Supply 200 mAVoo=Vpro,7-48V
|
||
LoadCurrent VGG=-35
|
||
VIHP InputHighVoltage 0.3 V
|
||
VIL1PPulsedDataInput -46 -48 V
|
||
LowVoltage
|
||
V1L2PAddress InputLow -40 -48 V
|
||
Voltage
|
||
VIL3PPulsedInputLowVoo-46 -48 V
|
||
andProgram Voltage
|
||
VIL4PPulsedInputLow -35 -40 V
|
||
VGGVoltage
|
||
Note1:lOOpflowsonlyduringVOO,VGGontime.lOOpshouldnotbeallowedtoexceed300mAforgreaterthan 100~sec. Averagepower
|
||
supplycurrentlOOpistypically40mAat20%dutycycle.
|
||
A.C.CHARACTERISTICS FORPROGRAMMING OPERATION
|
||
TAMSIENT =25°C,Vee=OV,Vss=+12V±10%,CS=OVunlessotherwise noted
|
||
SYMBOL TEST MIN. TYP. MAX. UNIT CONDITIONS
|
||
DutyCycle(Voo, VGG) 20 %
|
||
t~pw Program PulseWidth 3 ms VGG=-35V,Voo=
|
||
Vprog=-48V
|
||
tow DataSetUpTime 25 IlS
|
||
tOH DataHoldTime 10 IlS
|
||
tvw Voo, VGGSetUp 100 IlS
|
||
tvo Voo, VGGHold 10 100 J.1S
|
||
tACW (2)AddressComplement 25 IlS
|
||
SetUp
|
||
tACH(2)AddressComplement 25 J.1S
|
||
Hold
|
||
tATW AddressTrueSetUp 10 J.1S
|
||
tATH AddressTrueHold 10 J.1S
|
||
Note2.All8addressbitsmustbeinthecomplement statewhenpulsedVeeandVGGmovetotheirnegativelevels.Theaddresses(0through
|
||
255)mustbeprogrammed asshowninthetimingdiagramforaminimumof32times.
|
||
5-41
|
||
|
||
===PAGE 106===
|
||
SILICON GATEMOS8702A
|
||
SWITCHING CHARACTERISTICS FORPROGRAMMING OPERATION
|
||
PROGRAM OPERATION
|
||
Conditions ofTest:
|
||
Inputpulseriseandfalltimes:s1J1sec
|
||
CS=OV
|
||
PROGRAM WAVEFORMS
|
||
BINARY ADDRESS
|
||
OFWORDTOBE
|
||
PROGRAMMED
|
||
I
|
||
I I I
|
||
I ~tvoi
|
||
I~f--tATW---.ltACHr--
|
||
IIItACW----.l', II
|
||
BINARY COMPLEMENT OF
|
||
ADDRESS OFWORD
|
||
TOBEPROGRAMMED
|
||
o------------~o
|
||
ADDRESS
|
||
-40to-48
|
||
-46to-48PULSED Voo
|
||
POWERSUPPLY
|
||
0------------""'"
|
||
PULSED VGG
|
||
POWERSUPPLY
|
||
-35to-40
|
||
o--------------~
|
||
PROGRAMMING
|
||
PULSE
|
||
-46to-48
|
||
o
|
||
DATAINPUT
|
||
(DEVICE
|
||
OUTPUT
|
||
LINES)
|
||
--46to-48I I
|
||
I I1-tATH-----"1
|
||
I
|
||
I
|
||
I I I
|
||
II I--'ltOHr-
|
||
I
|
||
DATASTABLE
|
||
TIME
|
||
PROGRAMMING OPERATION OFTHE8702A
|
||
ADDRESS
|
||
WhentheDataInputforThentheDataOutput WORD A7A6ASA4A3A2A1AO
|
||
theProgramModeis:duringtheReadModeis:
|
||
0 00 0 00 0 0 0
|
||
V,L,P=""-48V pulsed Logic1=VOH='P'ontape1 00 0 00 0 0 1
|
||
I IIIIIII I
|
||
I IIIIIIII
|
||
VIHP;:""OV Logic0=VOL='N'ontape255 11 1 1 11
|
||
AddressLogicLevelDuringReadMode: Logic0=VIL("".3V) Logic1=V,H(""3V)
|
||
AddressLogicLevelDuringProgramMode: Logic0=VIL2P(""-40V) Logic1=V,HP(--OV)
|
||
5-42
|
||
|
||
===PAGE 107===
|
||
SILICON GATEMOS8702A
|
||
PROGRAMMING INSTRUCTIONS
|
||
FORTHE8702A
|
||
I.Operation ofthe8702Ain
|
||
Program Mode
|
||
Initially,all2048bitsoftheROMarein
|
||
the"0"state(outputlow).Information
|
||
isintroduced byse\ectively program
|
||
ming"1"s(outputhigh)intheproper
|
||
bitlocations.
|
||
Wordaddressselection isdonebythe
|
||
samedecoding circuitry usedinthe
|
||
READmode(seetableonpage6for
|
||
logiclevels).All8addressbitsmustbe
|
||
inthebinarycomplement statewhen
|
||
pulsedVDDandVGGmovetotheirnega
|
||
tivelevels.Theaddresses mustbeheld
|
||
intheirbinarycomplement statefora
|
||
minimum of25p'secafterVDDandVGG
|
||
havemovedtotheirnegative levels.
|
||
Theaddresses mustthenmakethe
|
||
transition totheirtruestateaminimum
|
||
of10p'secbeforetheprogram pulse
|
||
isapplied.Theaddresses shouldbe
|
||
programmed inthesequenc~ 0through
|
||
255foraminimum of32times.The
|
||
eightoutputterminals areusedasdata
|
||
inputstodetermine theinformation
|
||
patternintheeightbitsofeachword.
|
||
Alowdatainputlevel(-48V)willpro
|
||
grama"1"andahighdatainputlevel
|
||
(ground) willleavea"0"(seetableon
|
||
page6).Alleightbitsofonewordare
|
||
programmed simultaneously bysetting
|
||
thedesiredbitinformation patternson
|
||
thedatainputterminals.
|
||
Duringtheprogramming, VGG,VDDand
|
||
theProgram Pulsearepulsedsignals.II.Programming ofthe8702AUsing
|
||
Intel®Microcomputers
|
||
Intelprovides lowcostprogram devel
|
||
opmentsystemswhichmaybeusedto
|
||
program itselectrically programmable
|
||
ROMs.Notethattheprogramming
|
||
specifications thatapplytothe8702A
|
||
areidentical tothoseforIntel's1702A.
|
||
A.Intellec®
|
||
TheIntellecseriesofprogram de
|
||
velopment systems, theIntellec
|
||
8/Mod8andIntellec8/Mod80,are
|
||
usedasprogram development tools
|
||
forthe8008and8080microproces
|
||
sorsrespectively. Assuch,theyare
|
||
equipped withaPROMprogrammer
|
||
cardandmaybeusedtoprogram
|
||
Intel'selectrically programmable
|
||
andultraviolet erasable ROMs.
|
||
AnASR-33teletypeterminalisused
|
||
astheinputdevice.Through useof
|
||
theInteHecsoftware systemmonitor,
|
||
programs tobeloadedintoPROM
|
||
maybetypedindirectlyorloaded
|
||
throughthepapertapereader.The
|
||
systemmonitorallowstheprogram
|
||
tobereviewed oralteredatwill
|
||
priortoactuallyprogramming the
|
||
PROM.Formorecomplete informa
|
||
tionontheseprogram development
|
||
systems, refertotheIntelMicro
|
||
computer CatalogortheIntellec
|
||
Specifications.
|
||
B.UsersoftheSIM8microcomputer
|
||
programming systemsmayalso
|
||
program the8702Ausingthe
|
||
MP7-03programmer cardandthe
|
||
appropriate controlROMs:
|
||
SIM8system-Control ROMs
|
||
A0860,A0861andA0863.
|
||
5-43III.8702AErasingProcedure
|
||
The8702Amaybeerasedbyexpo-
|
||
suretohighintensity short-wave ultra
|
||
violetlightatawavelength of2537A.
|
||
Therecommended integrated dose(Le.,
|
||
UVintensity xexposure time)is
|
||
6W-sec/cm2•Examples ofultraviolet
|
||
sourceswhichcan erase the8702A
|
||
in10to20minutesaretheModel
|
||
UVS-54andModelS-52short-wave
|
||
ultraviolet lampsmanufactured by
|
||
Ultra-Violet Products, Inc.(5114Walnut
|
||
GroveAvenue,SanGabriel,California).
|
||
Thelampsshouldbeusedwithout
|
||
short-wave filters,andthe8702Ato
|
||
beerasedshouldbeplacedaboutone
|
||
inchawayfromthelamptubes.
|
||
|
||
===PAGE 108===
|
||
·:,
|
||
|
||
===PAGE 109===
|
||
SiliconGateMOS8708/8704
|
||
8192/4096 BITERASABLE ANDELECTRICALLY
|
||
REPROGRAM MABLEREADONLYMEMORY
|
||
•87081024x8Organization
|
||
•8704512x8Organization
|
||
•FastProgramming -
|
||
Typ.100sec.ForAll8KBits
|
||
•LowPowerDuringProgramming
|
||
•AccessTime-450ns
|
||
•Standard PowerSupplies
|
||
+12V,±5V•Static-NoClocksRequired
|
||
•InputsandOutputsTTL
|
||
Compatible DuringBothRead
|
||
andProgram Modes
|
||
•Three-State Output- OR-Tie
|
||
Capability
|
||
TheIntel@8708/8704 arehighspeed8192/4096 biterasable andelectrically reprogrammable ROM's(EPROM) ideallysuited
|
||
wherefastturnaroundandpatternexperimentation areimportant requirements.
|
||
The8708/8704 arepackaged ina24pindual-in-line package withtransparent lid.Thetransparent lidallowstheusertoex
|
||
posethechiptoultraviolet lighttoerasethebitpattern. Anewpatterncanthenbewrittenintothedevices.
|
||
@Apinforpinmaskprogrammed ROM,theIntel8308,isavailable forlargevolumeproduction runsofsystems initially using
|
||
the8708.
|
||
The8708/8704 isfabricated withthetimeprovenN-channel silicongatetechnology.
|
||
PINCONFIGURATIONS BLOCKDIAGRAM
|
||
YGATINGOUTPUT BUFFERS
|
||
64X128
|
||
ROMARRAYDATAOUTPUT
|
||
0,Os
|
||
I
|
||
X
|
||
DECODERY
|
||
DECODERCHIPSELECT
|
||
LOGIC CS/WE-
|
||
AO·Ag
|
||
ADDRESS
|
||
INPUTSA7 24Vee
|
||
A62 23As
|
||
As3 22
|
||
A44 21Vea
|
||
A35 20CSIWE
|
||
87081
|
||
A26 8704 19Voo
|
||
A17 18PROGRAM
|
||
Ao8 17Os
|
||
019 1607
|
||
0210 1506
|
||
0311 14Os
|
||
Vss12 1304
|
||
*8704=Vss
|
||
8708=Ag
|
||
PINNAMES
|
||
Ao·Ag ADDRESS INPUTS
|
||
O,·Os DATAOUTPUTS
|
||
CSIWE CHIPSElECTIWRITE ENABLE INPUT
|
||
5-45
|
||
|
||
===PAGE 110===
|
||
SILICON GATEMOS8708/8704
|
||
Absolute Maximum Ratings~·
|
||
Temperature UnderBias ,. -25°Cto+85°C
|
||
StorageTemperature -~5°Cto+125°C
|
||
AllInputorOu'tputVoltageswithRespecttoVBB
|
||
(exceptProgram) . . . . . . . . . . . . . . . . . . . . . . . . . ..+15Vto-0.3V
|
||
ProgramInputtoVBB. . . . . . . . . . . . . . . . . . . . . . . . ..+35Vto-O.3V
|
||
SupplyVoltages VccandVsswithRespecttoVBB.. . . ...+15Vto-O.3V
|
||
VoowithRespecttoVBB. . . . . . . . . . . . . . . . . . . . . ..+20Vto-O.3V
|
||
PowerDissipation . . . . . . . . . . . . . . . . . . . . . ..1.5W*COMMENT
|
||
Stressesabovethoselistedunder"Absolute Maximum
|
||
Ratings" maycausepermanent damagetothedevice.
|
||
Thisisastressratingonlyandfunctional operation
|
||
ofthedeviceattheseoranyotherconditions above
|
||
thoseindicated intheoperational sectionsofthis
|
||
specification isnotimplied. Exposure toabsolute
|
||
maximum ratingconditions forextended periodsmay
|
||
affectdevicereliability·.
|
||
READOPERATION
|
||
D.C.andOperating Characteristics
|
||
TA=o°cto70°C,Vee=+5V±5%,Voo=+12V±5%,VeB=-5V±5%,VSS=ov,UnlessOtherwise Noted.
|
||
.Symbol Parameter Min.Typ.l1] Max.Unit Conditions
|
||
III AddressandChipSelectInputLoadCurrent 10JlAVIN=5.25V
|
||
Ilo OutputLeakageCurrent 10JlAVOUT=5.25V,CS/WE=5V
|
||
100 VooSupplyCurrent 50 65mAWorstCaseSupplyCurrents:
|
||
lee VeeSupplyCurrent 6 10mAAllInputsHigh
|
||
IBB VBeSupplyCurrent 30 45mACS/WE=5V;TA=O°C
|
||
Vil InputLowVoltage Vss 0.65 V
|
||
VIH InputHighVoltage 3.0 Vee+1 V
|
||
VOL OutputLowVoltage 0.45 VIOl=1.6mA
|
||
VOH1 OutputHighVoltage 3.7 VIOH=-100JlA
|
||
VOH2 OutputHighVoltage 2.4 VIOH=-1mA
|
||
Po PowerDissipation 800mWTA=70°C
|
||
NOTES: 1.TypicalvaluesareforTA=2Soeandnominalsupplyvoltages.
|
||
2.Theprogram input(Pin18)maybetiedtoVSSorVeeduringthereadmode.
|
||
5-46
|
||
|
||
===PAGE 111===
|
||
SILICON GATEMOS8708/8704
|
||
A.C.Characteristics
|
||
TA=O°Cto70°C,Vee=+SV±S%,Voo=+12V±S%,Vee=-SV±S%,Vss=OV,UnlessOtherwise Noted.
|
||
Symbol Parameter Min. Typ. Max. Unit
|
||
tAce AddresstoOutputDelay 2804S0 ns
|
||
teo ChipSelecttoOutputDelay 120 ns
|
||
tOF ChipDe-Select toOutputFloat 0 120 ns
|
||
tOH AddresstoOutputHold 0 ns
|
||
Capacitance£1] TA=2SoC,f = 1MHz
|
||
Symbol Parameter Typ.Max.UnitConditions
|
||
CIN InputCapacitance 46pFVIN=OV
|
||
COUT OutputCapacitance 812pFVOUT=QV
|
||
Note1.Thisparameter isperiodically sampled andnot100%tested.
|
||
A.C.TestConditions:
|
||
OutputLoad:1TTLgateandCL=100pF
|
||
InputRiseandFallTimes: ~20ns
|
||
TimingMeasurement Reference Levels:0.8Vand2.8Vforinputs;0.8Vand2.4Vforoutputs
|
||
InputPulseLevels:O.6SVto3.0V
|
||
Waveforms
|
||
ADDRESS----X--------------......J'IX,.,--------
|
||
C.S./WEI 1
|
||
I I~tOH-----'1
|
||
i~'--------------......."A iII.---teo---'1 I 1
|
||
~tDF---.1
|
||
14-11---- tACC _I 1
|
||
5-47
|
||
|
||
===PAGE 112===
|
||
SILICON GATEMOS8708/8704
|
||
PROGRAMMING OPERATION
|
||
Description
|
||
Initially, andaftereacherasure, allbitsofthe8708/8704 areinthe"1"state(Output High).Information isintroduced byselect
|
||
ivelyprogramming "0"intothedesiredbitlocations.
|
||
Thecircuitissetupforprogramming operation byraisingtheCS/WEinput(Pin 20) to+12V.Thewordaddress isselected inthe
|
||
samemanner asinthereadmode.Datatobeprogrammed arepresented, 8-bitsinparallel, tothedataoutputlines(01-08).
|
||
Logiclevelsforaddressanddatalinesandthesupplyvoltages arethesameasforthereadmode.Afteraddressanddatasetup
|
||
oneprogram pulse(Vp)peraddress isappliedtotheprogram input(Pin18).Onepassthrough alladdresses tobeprogrammed is
|
||
defined asaprogram loop.Thenumber ofloops(N)required isafunction oftheprogram pulsewidth(tpw)according to
|
||
N xtpw~100ms.
|
||
Forprogram verification, program loopsandreadloopsmaybealternated asshowninwaveform B.
|
||
Program Characteristics
|
||
TA=25°C,Vcc=+5V±5%,Voo=+12V±5%,Vss=-5V±5%,Vss=OV,CS/WE=+12V,UnlessOtherwise Noted.
|
||
Symbol Parameter Min. Typ. Max. Units
|
||
tAS AddressSetupTime 10 llS
|
||
tcss CS/WESetupTime 10 llS
|
||
tos DataSetupTime 10 llS
|
||
tAH Address HoldTime 1 llS
|
||
tCH CS/WEHoldTime .5 lls
|
||
tOH DataHoldTime 1 lls
|
||
tOF ChipDeselect toOutputFloatDelay 0 120 ns
|
||
tOPR Program ToReadDelay 10 llS
|
||
tpw Program PulseWidth .1 1.0 ms
|
||
tpR Program PulseRiseTime .5 2.0 llS
|
||
tpF Program PulseFallTime .5 2.0 llS
|
||
Ip Programming Current 10 20 rnA
|
||
Vp Program PulseAmplitude 25 27 V
|
||
NOTE:Intelsstandard productwarranty appliesonlytodevicesprogrammed tospecifications described herein.
|
||
ErasingProcedure
|
||
The8708/8704 maybeerasedbyexposuretohighintensity short-wave ultraviolet Iightatawavelength of2537A.Therecom
|
||
mended integrated dose.(Le.,UVintensity xexposure time)is10W-sec/cm 2.Examples ofultraviolet sourceswhichcanerasethe
|
||
8708/8704 in20to30minutes aretheModelUVS-54 andModelS-52short-wave ultraviolet lampsmanufactured byUltra-Violet
|
||
Products, Inc.(5114WalnutGroveAvenue, SanGabriel, California). Thelampsshouldbeusedwithout short-wave filters,andthe
|
||
8708/8704 tobeerasedshouldbeplacedaboutoneinchawayfromthelamptubes.
|
||
5-48
|
||
|
||
===PAGE 113===
|
||
SILICON GATEMOS8708/8704
|
||
Waveforms
|
||
(Logiclevelsandtimingreference levelssameasintheReadModeunlessnotedotherwise.)
|
||
A)Program Mode
|
||
CS/WE=+12V
|
||
~__AD_D_R_ESS_1_....c ~_--·-·-·----.lX'---A-D-D-RE-SS-1-0-23--~ADDRESS 0...---------------ONE PROGRAM LOOP---------------.!
|
||
I
|
||
26VADDRESS
|
||
DATA
|
||
°1·0SPROGRAM
|
||
PULSE
|
||
OV-------II
|
||
B)Read/Program/Read Transitions
|
||
ADDRESS~ PR~g~:M --'1
|
||
o
|
||
tess
|
||
26V
|
||
PROGRAM
|
||
PULSE
|
||
0--+-------"""1
|
||
DATA
|
||
°1·0SDATAOUT DATA
|
||
VALID FLOATDATAIN
|
||
VALIDDATAIN
|
||
VALIDDATAOUT
|
||
VALID
|
||
5-49
|
||
|
||
===PAGE 114===
|
||
SILICON GATEMOS8708/8704
|
||
TypicalCharacteristics (Nominal supplyvoltagesunlessotherwise noted):
|
||
OUTPUT SINKCURRENT
|
||
VS.OUTPUT VOLTAGERANGEOFSUPPLY CURRENTS
|
||
VS.TEMPERATURE
|
||
100 80 60ALLPOSSIBLE OPERATING
|
||
CONDITIONS:
|
||
Vee=5.25V
|
||
Voo=12.6V
|
||
Vaa=-5.25V
|
||
40 20pEEE]f!1EJEZPlEzz$m:=:2!:;·m··;:: }Icco'---__ ..I-__ ""'--- ...l........-_------'
|
||
o80.----..----,....---~--~--,
|
||
60
|
||
=i
|
||
.§
|
||
Cf.)...2wa::40a::
|
||
;:)
|
||
0
|
||
>..J
|
||
~
|
||
~
|
||
;:)
|
||
Cf.)
|
||
20
|
||
1.0 .8 .6---SPEC
|
||
.4TA=O°C
|
||
TA=25°C
|
||
TA=70°C~~---#----+_'_~-+-----i
|
||
.2Vee=4.75V
|
||
41----t----#-i~,r;--t----+__-__i681----+----t----t--~1t--~---::l~10r-----...----or----...----..,---,~
|
||
MAXIMUM JUNCTION TEMPERATURE
|
||
VS.AMBIENT TEMPERATURE
|
||
150r------_----..,..----,....------..
|
||
8JA=80°CIW
|
||
Vee=5.25V
|
||
Voo=12.6V
|
||
Vaa=-5.25V
|
||
1001----- 4~=----+------+----i
|
||
50t--------t-----+-----+____i500
|
||
400
|
||
300
|
||
E.u
|
||
tJ
|
||
...<t
|
||
200
|
||
100ACCESS TIMEVS.TEMPERATURE
|
||
II
|
||
1TTLLOAD+100pF
|
||
~
|
||
~~~
|
||
~~
|
||
80 60 40 20o
|
||
-20 6070 40 200'---------'----------1..----.1..------'o
|
||
ACCESS TIME
|
||
VS.LOADCAPACITANCE
|
||
I
|
||
TA=25°C
|
||
-
|
||
---------------~~
|
||
-----So
|
||
~200
|
||
...<t300400
|
||
100
|
||
oo 100 200 300 400 500
|
||
5-50
|
||
|
||
===PAGE 115===
|
||
SiliconGateMOS8302
|
||
2048BITMASKPROGRAMMABLE
|
||
READONLYMEMORY
|
||
•StaticMOS-NoClocksRequired
|
||
•SimpleMemoryExpansion -Chip
|
||
SelectInputLead
|
||
•24-PinDual-In-Line Hermetically
|
||
SealedCeramic Package•AccessTime-1 p'secMax.
|
||
•FullyDecoded, 256x 8Organization
|
||
•InputsandOutputsTTLCompatible
|
||
•Three-State Output-OR-Tie
|
||
Capability
|
||
TheIntel@8302 isafullydecoded 256wordby8bitmetalmaskROM.Itisidealforlargevolumeproduc
|
||
tionrunsofmicrocomputer systemsinitial.lyusingthe8702Aerasableandelectrically programmable ROM.
|
||
The8302hasthesamepinningasthe8702A.
|
||
The8302isentirelystatic-noclocksarerequired. Inputsandoutputsofthe8302areTTLcompatible.
|
||
Theoutputisthree-state forOR-tiecapability. Aseparatechipselectinputallowseasymemoryexpansion.
|
||
The8302ispackaged ina24pindual-in-Iine hermetically sealedceramicpackage.
|
||
The8302isfabricated withp-channel silicongatetechnology. Thislowthreshold allowsthedesignand
|
||
production ofhigherperformance MOScircuitsandprovides ahigherfunctional densityonamonolithic
|
||
chipthanconventional MOStechnologies.
|
||
PINCONFIGURATION BLOCKDIAGRAM
|
||
A2 VooDATAOUT1DATAOUT8
|
||
A12 23Vee
|
||
es-.OUTPUT
|
||
Ao3 22Vee BUFFERS
|
||
DATAOUT14(LSB) 21A3
|
||
DATAOUT25 20A4 2048BIT
|
||
ROMMATRIX
|
||
DATAOUT36 19As(256X8)8302
|
||
DATAOUT47 18As
|
||
DATAOUT58 17A]
|
||
DATAOUT69 16VGG
|
||
DATAOUT710 15N.C.
|
||
DATAOUT811(MSB) 14cs
|
||
Vee12 13N.C.
|
||
AoA1 A]
|
||
PINNAMES
|
||
AO'A7 ADDRESS INPUTS
|
||
CS CHIPSELECT INPUT
|
||
001·DOa DATAOUTPUTS
|
||
5-51
|
||
|
||
===PAGE 116===
|
||
SILICON GATEMOS8302
|
||
Absolute Maximum Ratings ~~
|
||
Ambient Temperature UnderBias oOcto+70oC
|
||
StorageTemperature -65°Cto+1250C
|
||
Soldering Temperature ofLeads(10sec). . . . . ...+300oC
|
||
PowerDissipation 2Watts
|
||
InputVoltages andSupply
|
||
VoltageswithrespecttoVcc+O.5Vto-20V*COMMENT
|
||
Stressesabovethoselistedunder IIAbsolute Maximum Rat
|
||
ings"maycausepermanent damagetothedevice.Thisisa
|
||
stressratingonlyandfunctional operation ofthedeviceat
|
||
theseoratanyothercondition abovethoseindicated in
|
||
theoperational sectionsofthisspecification isnotimplied.
|
||
Exposure toAbsolute Maximum Ratingconditions forex
|
||
tendedperiodsmayaffectdevicereliability.
|
||
READOPERATION
|
||
D.C.andOperating Characteristics
|
||
TA=DOCto70°C,Vee=+5V±5%, Voo=-9V±5%, V6~=-9V±5%, unlessotherwise noted.
|
||
SYMBOL TEST MIN.TypJ2)MAX.UNIT CONDITIONS
|
||
'llAddressandChipSelect 1JJAV,N=O.OV
|
||
InputLoadCurrent
|
||
'lOOutputLeakageCurrent 1J,JAVOUT=O.OV,CS= Vcc-2
|
||
'000PowerSupplyCurrent 510mAVGG=Vec,CS=Vcc-2
|
||
10l=O.OmA,TA=25°C
|
||
1001PowerSupplyCurrent 35 50mACS=Vee-2"""l
|
||
'Ol=O.OmA, TA=25°C
|
||
'002PowerSupplyCurrent 32 46mACS=O.O
|
||
'Ol=O.OmA, TA=25°C
|
||
>Continuous
|
||
'003PowerSupplyCurrent 38.5 60mACS=Vec-2
|
||
'Ol=O.OmA, TA=OOCOperation
|
||
'CF1OutputClampCurrent 8 14mAVOUT=-1.0V,TA=ooC
|
||
'CF2OutputClampCurrent 13mAVOUT=-1.0V,TA=25°C
|
||
4
|
||
'GGGateSupplyCurrent 1JJA
|
||
V1L1InputLowVoltagefor-1.0 0.65 V
|
||
TTLInterface
|
||
V1L2InputLowVoltagefor Voo Vce-6V
|
||
MOSInterface
|
||
V,HAddressandChipSelect Vee-2 Vee+0.3V
|
||
InputHighVoltage
|
||
'OlOutputSinkCurrent 1.6 4 mAVOUT=0.45V
|
||
'OHOutputSourceCurrent -2.0 mAVOUT=O.OV
|
||
VOLOutputLowVoltage -.70.45 V'Ol=1.6mA
|
||
VOHOutputHighVoltage 3.54.5 V'OH=-100fJA
|
||
Note1.VGGmaybeclockedtoreducepowerdissipation. Inthismodeaverage100increases inproportion toVGGdutycycle.
|
||
Note2.Typical valuesareatnominal voltages andTA=25°C.
|
||
5-52
|
||
|
||
===PAGE 117===
|
||
SILICON GATEMOS8302
|
||
A.C.Characteristics
|
||
TA=(1JCto+70°C,Vee=+5V±5%,Voo=-9V±5%,VGG=-9V±5%unlessotherwise noted
|
||
SYMBOL TEST MINIMUM TYPICAL MAXIMUM UNIT
|
||
Freq. Repetition Rate 1 MHz
|
||
tOH Previous readdatavalid 100 ns
|
||
tACC Addresstooutputdelay .700 1 JJ.s
|
||
tovGGClocked VGGsetup 1 JJ.s
|
||
tcsChipselectdelay 200 ns
|
||
tco OutputdelayfromCS 500 ns
|
||
too Outputdeselect 300 ns
|
||
tOHCDataoutholdinclocked VGGmode(Note1) 5 JJ.s
|
||
Note1.TheoutputwillremainvalidfortOHCaslongasclocked VGGisatVce.Anaddresschangemayoccurassoonastheoutputissensed
|
||
(clocked VGGmaystillbeatVee).Databecomes invalidfortheoldaddresswhenclocked VGGisreturned toVGG.
|
||
Capacitance* TA=25°C
|
||
SYMBOL TEST MINIMUM TYPICAL MAXIMUM UNIT CONDITIONS
|
||
C,N InputCapacitance 5 10 pF"1N=vee} All
|
||
COUTOutputCapacitance 5 10 pFCS=VCCunusedpins
|
||
CVGGVGGCapacitance 30 pFVOUT=VCCareatA.C.
|
||
(Clocked VGGMode)VGG=VCCground
|
||
*Thisparameter isperiodically sampled andisnot100%tested.
|
||
A)Constant VGGOperationSwitching Characteristics
|
||
DATAOUT
|
||
INVALIDDATAOUT
|
||
INVALIDVOH-----~
|
||
DATA
|
||
OUT
|
||
V
|
||
,H-v.DESELECTlDN OFDATAOUTPUT INOR·TlEOPERATION
|
||
ADDRESS.fi.
|
||
V1L1-----------------
|
||
: NOTE2 ._ ~~~Ons
|
||
csV,H~ ,',r---~----l ...·......i---
|
||
'-"L I ,I I
|
||
~"-to too--,I~
|
||
vcc,,::VGGL'::
|
||
CLOCKEDI: III II
|
||
VGGI II
|
||
VGG1-+1-----....", I I
|
||
I ...--~50ns---1 II I II
|
||
V {I:
|
||
DATAO~HTi-'ACC~ .
|
||
VOL ......----------1VOL---------r--ISr----------
|
||
NOTE 1:TheoutputwillremainvalidfortOHeaslongasclocked VGG
|
||
isatVee.Anaddress changemayoccurassoonastheoutput issensed
|
||
(clocked VGGmaystillbeatVee).Databecomes invalidfortheold
|
||
address whenclocked VGGisreturned toVGG'
|
||
NOTE2:IfCSmakesatransition fromVILtoVIHwhileclocked VGG
|
||
isatVGG,thendeselection ofoutput occursattooasshowninstatic
|
||
operation withconstant VGG'B)Clocked VGGOperation~ CYCLE TIME ~IFREO---....l
|
||
ADDRE~~H~::>C
|
||
V1L I I
|
||
I I
|
||
I
|
||
VIH,,: I I
|
||
CS '\ ~~ons---{
|
||
V1LI I
|
||
_I~tDV :.
|
||
Vee,; : GG /:..--------..\
|
||
CLOCKED'\I / ;
|
||
VGG
|
||
VGGI'::(SEENOTE1)~---
|
||
.-.- 'ACC~--I~tOHC
|
||
I I
|
||
I I
|
||
I I
|
||
DATAOUT
|
||
INVALID....1·----tAcc-----·~1
|
||
V1H---f10%
|
||
CS
|
||
V1L
|
||
1
|
||
"o~---f()1 -too~
|
||
IUDATA I
|
||
OUT I
|
||
VOLI I
|
||
---ltco.---CYCLE TIME'I/FREO-
|
||
V,----------_IHV10% V
|
||
ADDRESSfi 90% A
|
||
V1L1 I~----
|
||
--I'cs~ I
|
||
_ V1Hn' t--toH--lcs I II:
|
||
V1L : :
|
||
I I
|
||
g~~~H--4!~--~N-~-TA-AL-~-DU-T--~\r;-
|
||
VOL t---+--
|
||
DESELECTION OFDATAOUTPUT INOR·TlEOPERATION
|
||
AD:~:Y:: X"----VIL'~Conditions ofTest:
|
||
Inputpulse.amplitudes: 0to4V;tR,tF~50ns
|
||
Outputloadis1TTLgate;measurements made
|
||
at.outputofTTLgate(tpD::515ns)
|
||
5-53
|
||
|
||
===PAGE 118===
|
||
SILICON GATEMOS8302
|
||
TypicalCharacteristics
|
||
100CURRENT VS.TEMPERATUREACCESS TIMEVS.
|
||
LOADCAPACITANCEOUTPUT SINKCURRENT
|
||
VS.OUTPUT VOLTAGE
|
||
I
|
||
\vee=+5V-
|
||
~voo=-9V-\\ vGG=-9V
|
||
"INPUTS:: Vee-
|
||
~
|
||
\I"OUTPUTS AREOPEN
|
||
III'\~Il'NSIIV ee
|
||
."'""l
|
||
CS=0.0V'
|
||
I
|
||
I
|
||
+1+2+3+4CiI---+---+--.! 12.0
|
||
~zaut----+---+-- ~10.0
|
||
::)
|
||
CJ
|
||
~8.0
|
||
en
|
||
t----+---+-- ~6.0~--+-~T---+-----te:;)
|
||
t----+---+-- 0
|
||
-4-3-2-1'-
|
||
1TTLLOAD t--
|
||
Vcc=+5VI----
|
||
VOO=-9V
|
||
VGG::-9VI--
|
||
TA::I250Cr----
|
||
I II900
|
||
800
|
||
700
|
||
!600
|
||
w
|
||
~500
|
||
~
|
||
~400auuu3004(
|
||
200
|
||
100
|
||
oo102030405060708090100
|
||
LOADCAPACITANCE (pF)
|
||
80100120 604020o39
|
||
38
|
||
37
|
||
36
|
||
35i34
|
||
~33zau
|
||
II:32II:
|
||
ju31
|
||
0_030
|
||
29
|
||
28
|
||
27
|
||
AMBIENT TEMPERATURE (OC) OUTPUT VOLTAGE (VOLTSI
|
||
ACCESS TIMEVS.
|
||
TEMPERATUREOUTPUT CURRENT VS.
|
||
VOOSUPPLY VOLTAGEOUTPUT CURRENT VS.
|
||
TEMPERATURE
|
||
II I
|
||
~vee·+5V
|
||
~~voo•-9V
|
||
vGG•-9V
|
||
~~VOL·+.45V-I--
|
||
cs..o.~~r--......I
|
||
0102030k5060 708090IAiBIENT TEMPERATURE t"CI
|
||
Vee"+5V
|
||
Voo•-9V--VGG--9V
|
||
VOH"O.OV
|
||
~
|
||
~I--~~rr----;{
|
||
.!
|
||
~zaua:a:
|
||
::)u
|
||
~z
|
||
en
|
||
~::)
|
||
~
|
||
~:J0
|
||
j
|
||
_0
|
||
Ci0
|
||
!
|
||
~zw
|
||
II:a:
|
||
::)
|
||
U
|
||
au
|
||
CJ-3a:::)
|
||
S
|
||
~::)
|
||
~
|
||
~:J0
|
||
x_0-4I I
|
||
Vcc::+5V
|
||
"""VGG=-9V ""'""
|
||
VOL::+.45V/
|
||
_ TA=.250C
|
||
--Specified
|
||
Operating Range_r--_I I
|
||
n(I,
|
||
-5-6-7-8-9-10
|
||
VDOSUPPLYVOLTAGE (V)
|
||
i-- II
|
||
VCC::I+5V
|
||
VGG::-9V
|
||
VOH::IO.OV
|
||
TA'"25°C
|
||
,,~;{
|
||
!
|
||
~z-3w
|
||
II:
|
||
II:
|
||
:;)
|
||
U
|
||
w
|
||
U
|
||
II::J0-3.5en
|
||
I-:J
|
||
~I-:Jo
|
||
%.9-4102030405060708090
|
||
AMBIENTTEMPERATURE (OC)~
|
||
I---
|
||
1TTLLOAD~20pf-
|
||
VccII+5V-
|
||
VDO..-9V
|
||
VGG=-9V-
|
||
I I900
|
||
800
|
||
700
|
||
.:600
|
||
w
|
||
~500
|
||
~
|
||
~400wuu3004(
|
||
200
|
||
100
|
||
AVERAGE CURRENT VS.DUTY
|
||
CYCLEFORCLOCKED VGG
|
||
45
|
||
40
|
||
100135
|
||
C30.!
|
||
026_0
|
||
au
|
||
CJ204(a:w15>4(
|
||
10
|
||
10005IIIII
|
||
CLOCKED VGG::-9V
|
||
VDD..-9V
|
||
~----CS::V1H ~
|
||
TA..25°C~~----~~.---
|
||
~~
|
||
~
|
||
--~~~
|
||
~~
|
||
---
|
||
oo 10 20 30 40 50 60
|
||
DUTYCYCLE (%)70 80 90 100
|
||
5-54
|
||
|
||
===PAGE 119===
|
||
SiliconGateMOS8308
|
||
8192BITSTATICMOSREADONLYMEMORY
|
||
Organization --1024Wordsx 8Bits
|
||
•FastAccess-450ns
|
||
•DirectlyCompatible with8080CPU
|
||
atMaximl)m Processor Speed
|
||
•TwoChipSelectInputsforEasy
|
||
Memory Expansion
|
||
•DirectlyTTLCompatible -AllInputs
|
||
andOutputs•ThreeStateOutput-OR-Ti~
|
||
Capability
|
||
•·FullyDecoded
|
||
•Standard PowerSupplies
|
||
+12VDC,±5VDC
|
||
TheIntel®8308isan8,192bitstaticMOSmaskprog~ammable ReadOnlyMemory organized as1024wordsby~-bi~s.This
|
||
ROMisdesigned for8080microcomputer systemapplications wherehighperformance, largebitstorage, andsimpleinter
|
||
facingareimportant designobjectives. TheinputsandoutputsarefullyTTLcompatible.
|
||
Apinforpincompatible electrically programmed erasable ROM,theIntel®8708,isavailable forsystemdevelopment and
|
||
smallquantity production use.
|
||
TwoChipSelectsareprovided -CS1whichisnegative true,andCS2/CS2 whichmaybeprogrammed eithernegative or
|
||
positivetrueatthemasklevel.
|
||
The8308readonlymemory isfabricated withN-channel silicongatetechnology. Thistechnology provides thedesigner with
|
||
highperformance, easy-to-use MOScircuits.
|
||
PINCONFIGURATION BLOCKDIAGRAM
|
||
DATAOUT1DATAOUT8
|
||
A7 Vee
|
||
A6 AsCS1--'OUTPUT
|
||
A5 AgCS2/CS2.-...BUFFERS
|
||
A4 Va8
|
||
A3 CSl 811)2BIT
|
||
ROMMATRIX
|
||
A2 \bo (1024X8)
|
||
A, CS2/CS2
|
||
Ao Os
|
||
0, 07
|
||
02 06
|
||
03 05
|
||
Vss 04
|
||
AoA, Ag
|
||
PINNAMES
|
||
AO-Ag ADDRESSINPUTS
|
||
o,-Os DATAOUTPUTS
|
||
CS,.CS2 CHIPSELECT INPUTS
|
||
5-55
|
||
|
||
===PAGE 120===
|
||
SILICON GATEMOS8308
|
||
Absolute Maximum Ratings*
|
||
Ambient Temperature UnderBias -25°Cto+85°C
|
||
StorageTemperature -65°·Cto-i-150°C
|
||
VoltageOnAnyPinWithRespect
|
||
ToVaa. . . . . . . . . . . . . . . . . -0..3Vto20V
|
||
PowerDissipation 1.0Watt*COMMENT
|
||
Stressesabovethoselistedunder"Absolute Maximum Ratings" may
|
||
causepermanent damagetothedevice.Thisisastressratingonly
|
||
andfunctional operation ofthedeviceattheseoranyothercondi
|
||
tionsabovethoseindicated in'theoperational sections ofthisspeci
|
||
fication isnotimplied. Exposure toabsolute maximum ratingcondi
|
||
tionsforextended periodsmayaffectdevicereliability.
|
||
D.C.andOperating Characteristics
|
||
TA=O°Cto+70°C,VCC=5V±5%;Voo=12V±5%,Vas=-5V±5%,Vss=OVUnlessOtherwise Specified.
|
||
Limits
|
||
Symbol Parameter
|
||
TypJ1]Unit TestConditions
|
||
Min. Max.
|
||
ILl InputLoadCurrent 10 J.l.A VIN=0to5.25V-(AllInputPinsExceptCS,)
|
||
ILCL InputLoadCurrentonCS, 1.6 rnA VIN=0.45V
|
||
ILPC InputPeakLoadCurrentonCS, 4 rnA VIN=0.8Vto3.3V
|
||
ILKC InputLeakageCurrentonCS, 10 J.l.A VIN=3.3Vto5.25V
|
||
ILO OutputLeakageCurrent 10 J.l.A ChipDeselected
|
||
VIL Input"Low"Voltage Vss-1 0.8V V
|
||
VIH Input"High"Voltage 3.3 Vcc+1.0 V
|
||
VOL Output"Low"Voltage 0.45 VIOL=2rnA
|
||
VOH' Output"High"Voltage 2.4 VIOH=-4rnA
|
||
VOH2 Output"High"Voltage 3.7 VIOH=-1rnA
|
||
Icc Power ~upplVCurrentVcc .8 2 rnA
|
||
100 PowerSupplyCurrentVoo 32 60 rnA
|
||
Iss PowerSupplyCurrentVss 10~A 1 rnA
|
||
Po PowerDissipation 775 rnW
|
||
NOTE1:TypicalvaluesforTA=25°Candnominal supplyvoltage
|
||
D.C.OUTPUT CHARACTERISTICS D.C.OUTPUT CHARACTERISTICS
|
||
2.42.62.83.03.23.43.63.84 0.2
|
||
VOHVOLTS'lil~,III
|
||
t=Oto70°C,
|
||
AI I 1',
|
||
'I',II
|
||
TYPICAL
|
||
"",'lIlI
|
||
/~~
|
||
SPEf~
|
||
~Ill..
|
||
-........~,....."
|
||
((4-1-3
|
||
-2-8-9-10
|
||
-7
|
||
1-6
|
||
~-5
|
||
-4~A:::6to76°C,
|
||
~
|
||
/
|
||
~
|
||
~I,
|
||
TYPICAL J
|
||
'('~
|
||
/~~
|
||
/
|
||
~J ~V
|
||
~
|
||
~V~ .........
|
||
'"I~SPEC
|
||
~VIoo.1.2.3 .4 .5.6.7 .8 .9 1.0
|
||
VOLVOLTS28
|
||
379
|
||
6
|
||
15
|
||
.1J4
|
||
5-56
|
||
|
||
===PAGE 121===
|
||
SILICON GATEMOS8308- -
|
||
A.C.Characteristics
|
||
TA=oo.cto'+70~C, VCC=+5V±5%;VO_D=+12V±5%,VBB=-5V_±5%,VSS_=OV,UnlessOtherwise Specif.i~d.
|
||
Limits[2]
|
||
Symbol Parameter Unit
|
||
Min. Typ. Max.
|
||
tACC AddresstoOutputDelayTime 200-450 ns
|
||
tC01 ChipSelect1toOutput Dela.y~ime 85160 ns
|
||
teo2 ChipSelect2toO~tputDelayTime 125220 ns
|
||
ChipDeselecttoOutputDatafloat Ti~_e_ 125220.-
|
||
tOF ns
|
||
NOTE2:Refertoconditions~ ofTestforA.C.Characteristics. ~dd50nanoseconds (worstcase)tospecified valuesat
|
||
VOH=3.7V@IOH=-1mA,CL=100pF.
|
||
CONDITIONS OFTESTFOR
|
||
A.C.CHARACTERISTICSCAP~CI_!ANCE TA_= __~5°C,f=1MHz!VBB=-5V,VOO,.
|
||
Vccandallot~erpinsti~~~oVss.
|
||
OutputLoad 1TTLGate,andCLOAO=100pF
|
||
InputPulseLevels. . . . . . . . . . . . . . . ...65Vto3.3V
|
||
InputPulseRiseandFallTimes 20nsec
|
||
TimingMeasurement Reference Level
|
||
........ ·....·..·..2.4VVIH,VOH;0.8VVIL,VOLLimits
|
||
Symbol Test
|
||
Typ. Max.
|
||
CIN InputCapacitance 6pF
|
||
CoUT Output C~pacitance 12pF
|
||
4-------- tACC--------~I
|
||
----------~
|
||
ADDRESS
|
||
.Ao-Ag--------------------- --------------
|
||
1..----t Co1----·1
|
||
~----------------1....-------te02------ ...1---------------,
|
||
5-57
|
||
|
||
===PAGE 122===
|
||
SILICON GATEMOS8308
|
||
TypicalCharacteristics (Nominal supplyvoltagesunless.otherwise noted.)
|
||
100VS.TE""PERATURE
|
||
(NORMALIZED)AOUTPUT CAPACITANCE
|
||
VS.AOUTPUT DELAY
|
||
+100 +50o -50-40L..-__ ...I..-__ ...Io....-__ .......I.-__ --'
|
||
-100+40r-----~--_r__--~---,
|
||
~CAPACITANCE (pF)_+20t----+-----+----~<------fuW(I)
|
||
..5-
|
||
~.J
|
||
~0t---:---+-------:::._--""'"'"f--
|
||
t::J
|
||
~t::Jo
|
||
<1-20~--+_--_+__----+---__t
|
||
102030405060 70 8090
|
||
AMBIENT TEMPERATURE TA(OC)~~
|
||
~"-~~
|
||
~
|
||
::::;~.7.8.9
|
||
.61.1
|
||
1.01.21.4
|
||
CS1INPUT
|
||
CHARACTERISTICSTACCVS.TEMPERATURE
|
||
.(NORIVIALIZ~O)
|
||
~~
|
||
~
|
||
~~
|
||
---~
|
||
.-:::i:::::=o
|
||
o102030405060708090
|
||
AMBIENT TEMPERATURE TA(OC).6.7.8.91.4
|
||
1.11.21.3
|
||
1.0
|
||
1.0 1.5 2.0 2.5 3.0
|
||
V1N(VOLTS).5)/1
|
||
~/\
|
||
/\
|
||
\...oo.51.02.5
|
||
2.02.5
|
||
~
|
||
.§1.5
|
||
-~
|
||
5-58
|
||
|
||
===PAGE 123===
|
||
MCS™
|
||
CUSTOM ROM
|
||
ORDERFORM8308
|
||
ROM
|
||
APp _S# _
|
||
STO _CUSTOMER _
|
||
P.O.NUMBER . _
|
||
OATE _
|
||
ForInteluseonly
|
||
PPpp---------
|
||
zz, _
|
||
00 _
|
||
OATE . _
|
||
Allcustom8308ROMordersmustbesubmitted onthisform.Programming information shouldbesentintheformofcomputer
|
||
punched cardsorpunched papertapepertheformatsdesignated onthisorderform.Additional formsareavailable fromIntel.
|
||
MARKING
|
||
®Themarking asshownattherightmust contain theIntellogo,the
|
||
producttype(P8308), the4-digitIntelpatternnumber(PPPP),adate
|
||
code(XXXX), andthe2-digitchipnumber (DO).Anoptional customer
|
||
identification numbermaybesubstituted forthechipnumber(ZZ).
|
||
Optional Customer Number(maximum 9characters orspaces).
|
||
CUSTOMER NUMBER _
|
||
MASKOPTION SPECIFICATIONS•8308Ixxxx
|
||
DATECODEPPPP
|
||
zzINTELPATTERN NUMBER
|
||
CHIPNUMBER OR
|
||
CUSTOMER NUMBER
|
||
A.CHIPNUMBER (CHIPSELECT
|
||
OPTION)
|
||
Mustbespecified 0or1.
|
||
Thechipnumber willbecodedin
|
||
termsofpositive logicwherealogic
|
||
"1"ishighlevelinput.
|
||
ChipSelectTruthTable
|
||
Chip
|
||
Number CS1 CS2 Selected
|
||
0 0 0 Yes
|
||
1 0 1 Yes
|
||
0 10 No
|
||
1 1 1 No
|
||
ChipNumberB.ROMTruthTableFormat
|
||
Programming information shouldbe
|
||
sentintheformofcomputer punched
|
||
cardsorpunched papertape.Ineither
|
||
case,aprintout ofthetruthtable
|
||
shouldbeaccompanied withtheorder.
|
||
Thefollowing generalformatisapplic
|
||
abletotheprogramming information
|
||
senttoIntel:
|
||
•Datafieldsshouldbeorderedbegin
|
||
ningwiththeleastsignificant address
|
||
(0000)andendingwiththemostsig.
|
||
nificantaddress(1023).
|
||
• Adatafieldshouldstartwiththe
|
||
mostsignificant bitandendwiththe
|
||
leastsignificant bit.
|
||
5-59•ThedatafieldshouldconsistofP's
|
||
andN's.A Pistoindicateahighlevel
|
||
output(mostpositive) andanN alow
|
||
leveloutput(mostnegative). Interms
|
||
ofpositive logic,a Pisdefined asa
|
||
logic"1"andanNisdefinedasaiogic
|
||
"0".Iftheprogramming information
|
||
issentonapunched papertape,then
|
||
astartcharacter, B,andanendcharac
|
||
ter,F,mustbeusedinthedatafield.
|
||
Seeparagraph 2.
|
||
1.Punched CardFormat
|
||
AnSO-column Hollerith card(prefer
|
||
ablyinterpreted) punched byanIBM
|
||
026or029keypunch shouldbesub
|
||
mitted.Thefirst'cardwillbeatitle
|
||
card;theformatisasfollows:
|
||
|
||
===PAGE 124===
|
||
a.TitleCardMCS™CUSTOM ROMORPER_FOR.M_8308
|
||
NO.OFOUTPUTS
|
||
TITLECARD 4or8
|
||
DESIGNATION CUSTOMER'S INTELP/Nl '1 CUSTOMER'S DIVISION OR1DECIMAL NUMBER
|
||
~INDICATING THECOMPANY NAME LOCATION CUSTOMER:S PIN I' i~ TRUTHTABLENUMBER
|
||
~"/~ G.:"-'·i-i·iNl('·~ CORP ::.,.o#1'i:: ,-:~AI?~ \.!iLI~ h?14:' (h',
|
||
IIIIII I I I I I II II I
|
||
IIIIIII I I I I I
|
||
~~~~~!~,~~~~~~~~~~I~!~~~~~~~~~ ~~~~~~~~!~~~~~!~~~~~~~ ~~~~~~~~~~~~I~~~~'~~!~ ~~I~~~~,~,,!
|
||
1I1111111 i11111111111111 11111111111111111111111111111111111111111111111111111111
|
||
2222211221121122212122222'21222122 il21112 2222222222 22222222212221222222 2121l2121?
|
||
I)IIJ3)))31)11))lll))I))))))))))3l)))I))Illl))1)IJ3))))) ))))I))]]))II)])))))) 1))
|
||
4U44uuU4u44u44U44u4u4UUUU4U4444UU444UU4UUIU444u41U444~~44
|
||
~!~SS5SSSI~IS~5SISSS5SSSSS5S~SSSS555ISS55SS~SSSS5SSSSSSSSSs'SSSIS5SS5S5SISIS)SSSS
|
||
666666&666&66661666666166666666666666666666666 &6661666666666 6~&&6666666666666666
|
||
I I "IIITI I I I I,,"I111I1IIII1111I I I I I I11I111I1I I11T111111111 I1I11111' I'11111111 j1I
|
||
888888188888 88888888888888888888888 8888888888888888888888 8~ea68GH&U88811188adBP
|
||
99HH919 g.~99ql9919999919999999999999999999199 J991999gq99999 ~'J'r,q91399q9n9q~qqq
|
||
'...... III••),. 'I'l'.J•,.,.:.:: .LO':\:.:'••••,1Q)1J:'J'.J\" J~J:I)1,,,••,:.,.: l.•••'",••.'\:.1",,••',f•••'. ...~.fl'!'..••• •.'.l~"'l
|
||
b.fQr_a1024wQrdX8-bitorganiza
|
||
tiononly,cards2andthefollowing
|
||
cardsshouldbepunched asshown.
|
||
MSB
|
||
DECIMAL WORD (OUTPUT 8l LSB DECIMAL NUMBER
|
||
ADDRESS BEGINNING (OUTPUT 1) INDICATING THE
|
||
EACHCARD 8DATAF.IELDS TRUTHTABLENUMBER
|
||
~r------+--t---.L.------_ rJ,
|
||
11111111 1I11II1I 1111I1I1 11111111 11111111 11111111 11111111 11111111
|
||
1111100000000000000000000000000 U0000000000000000000000000000000000000000000 u0011
|
||
•11'II"",'"'·\'I·:III'~:·:.:.: •.I:\:::tI~10111lIJ ..nlll:III"'U'/fI""''':lIh':III:II~III6I'I.lt"'II;lhHIIU·I'I'·; ,·.·j·.·I·.·· ",n
|
||
1I1111I1I1I1111111111111111I111111111111I111111111111111111I1111111111111111111I
|
||
222221111111 2121222212212,1121112222222222222222?Z2122222112'1222~222222;222i?~;2
|
||
3]JJ]))J))1) ) ) )JJJ)) ) )] ] ] JJJj ) ) ]J)J)))) ] ) ] )JJJlJJlJ)]13JJ))))J)] JJJJJ]13J1) 1)JJJ
|
||
U4C.:u.UU:44..H4.4c::~.tt.:.· 14C.::444~4H444:4H44:4UH:4H: ~4~:~::::4~::
|
||
~~S~~S~IS11111 ~SsSSIII ~s)S1111.);.ijIIi)Isssill;i;)1111IiiSSII)sIII ~i)II~;II))))
|
||
HHHHH6666b6666&6Et(iHbE~bt06Ii6&60t666t~b0~~0~6606~0ii£i:DO00~~c~~::~0tbEt0~0~
|
||
1111111: 11:::::1111;':;I;II: ~1:II;111111111111//11111111 i11111111: i11/1;......;I:I
|
||
868S8868Pfltg86G8888a888aci8888886~888888688666886&e8~~~Eae~li:~:i~o:~i,'~~:ii~i=:
|
||
9h~"O;"•qQqH~~~"9qg9q0;~~It"goCqqH999q99n9Q5~.;;'...•, •;• , ,
|
||
I:.,. •;.• .'..,.••• I~:I~:fc,...Column
|
||
1
|
||
2-5
|
||
6~30
|
||
31-34
|
||
35-54
|
||
55-57
|
||
58-66
|
||
67
|
||
68-75
|
||
76-78
|
||
79-80
|
||
Column
|
||
1-5
|
||
6
|
||
7-14
|
||
15
|
||
16-23
|
||
;33
|
||
34-41
|
||
42
|
||
43-50
|
||
51
|
||
52-59
|
||
60
|
||
61-68
|
||
69
|
||
70-77
|
||
78
|
||
79-80Data
|
||
Punch·aT
|
||
Blank
|
||
Customer Company Name
|
||
Blank
|
||
Customer's Company Divisionorlocation
|
||
Blank
|
||
Customer PartNumber
|
||
Blank
|
||
PunchtheIntel4-digitbasicpartnumber
|
||
andin( )thenumberofoutputbits,
|
||
e.g.,·8308(8).
|
||
Blank' .
|
||
Puncha2-digitdecimalnumbertoiden
|
||
tifythetruthtablenumber (mask
|
||
programmed chipselectnumber).
|
||
Data'
|
||
Punchthe5-digitdecimalequivalent of
|
||
thebinarycodedlocation whichbe
|
||
ginseachcard.Theaddress isright
|
||
justified, Le.,00000,00008,00016,
|
||
etc.
|
||
Blank
|
||
DataField
|
||
Blank
|
||
DataField
|
||
Blank
|
||
DataField
|
||
Blank
|
||
DataField
|
||
Blank
|
||
DataField
|
||
Blank
|
||
DataField
|
||
Blank
|
||
DataField
|
||
Blank
|
||
Punchsame2-digitdecimalnumber asin
|
||
titlecard.
|
||
2.PaperTapeFormat
|
||
1"widepapertapeusing7-or8-bit
|
||
ASCIIcode,suchasamodel33ASR
|
||
teletype produces, orthe11/16"wide
|
||
papertapeusinga5-bitBaudotcode,
|
||
suchasaTelexproduces.
|
||
Theformat requirements areasfol
|
||
lows:
|
||
a.Allwordfieldsaretobepunched in
|
||
consecutive order,startingwithword
|
||
field0(alladdresses low).There mu~t
|
||
beexactly 1024wordfieldsforthe
|
||
1024X 8ROMorganization.
|
||
b.Eachwordfieldmustbeginwith
|
||
thestartcharacter Bandendwiththe
|
||
stopcharacter F.Theremustbeex
|
||
actly8datacharacters between theB
|
||
andF.NOOTHER CHARACTERS, SUCH
|
||
ASRUBOUTS, AREALLOWED ANY
|
||
WHERE INAWORDFIELD.Ifinpre
|
||
paringatapeanerror i~made,theen
|
||
tirewordfield,including theBandF,
|
||
mustberubbedout.Withintheword
|
||
field,a Presultsinahighleveloutput
|
||
andanNresultsinalowleveloutput.
|
||
c.Preceding thefirstwordfieldand
|
||
following thelastwordfield,there
|
||
mustbealeader/trailer lengthofat
|
||
least25characters. Thisshouldconsist
|
||
ofruboutornullpunches (letterkey
|
||
forTelextapes).
|
||
d.Between wordfields,comments not
|
||
containing B'sorF'smaybeinserted.
|
||
Carriage returnandlinefeedcharacters
|
||
shouldbeinserted asa"comment")justbeforeeachwordfield(oratleast
|
||
between everyfourwordfields).When
|
||
thesecarriage returns,etc.,areinserted,
|
||
thetapemaybeeasilylistedonthe
|
||
teletype forpurposes oferrorcheck
|
||
ing.Thecustomer mayalsofindit
|
||
helpfultoinsertthewordnumber (as
|
||
acomment) atleasteveryfourword
|
||
fields.
|
||
e.Includedinthetapebeforethe
|
||
leadershouldbethecustomer's com
|
||
pleteTelexorTWXnumber and,if
|
||
morethanonepattern isbeingtrans
|
||
mitted,theROMpatternnumber.
|
||
f.MSBandLSBarethemostandleast
|
||
significant bitofthedeviceoutputs.
|
||
Refertothedatasheetforthepin
|
||
numbers.
|
||
DataField StartCharacter~ StopCharacterI, , I I
|
||
Leader:RuboutKeyforTWXandLetter BP P P N N N N N F B N N N N N NP P F
|
||
KeyforTelex(atleast25frames). I 'I I
|
||
Word'Field 0 WordiField 1
|
||
5-60MSB LSB,+
|
||
BNPNPPPNNFIi'
|
||
WordField1023Trailer:RuboulKeyforTWXandLeuer
|
||
KeyforTelex(alleasl25frames),
|
||
|
||
===PAGE 125===
|
||
intel® SiliconGateMOSROM8316A
|
||
16,384BITSTATICMOSREADONLYMEMORY
|
||
Organization-2048 Wordsx 8Bits
|
||
-- .
|
||
AccessTime-SSO nsmax
|
||
•Single+5VoltsPowerSupplyVoltage
|
||
•DirectlyTTLCompatible -AllInputs
|
||
andOutputs
|
||
•LowPowerDissipation of31.4/LW/Bit
|
||
Maximum
|
||
•ThreeProgrammable ChipSelect
|
||
InputsforEasyMemoryExpansion•Three-State Output-OR-Tie
|
||
Capability
|
||
•FullyDecoded -OnChipAddress
|
||
Decode
|
||
•InputsProtected -AllInputsHave
|
||
Protection AgainstStaticCharge
|
||
®
|
||
TheIntel8316Aisa16,384-bit staticMOSreadonlymemory organized as2048wordsby8bits.ThisROMis
|
||
designed formicrocomputer memory applications wherehighperformance, largebitstorage,andsimpleinter
|
||
facingareimportant designobjectives.
|
||
TheinputsandoutputsarefullyTTLcompatible. Thisdeviceoperates withasingle+5Vpowersupply.The
|
||
threechipselectinputsareprogrammable. Anycombination ofactivehighorlowlevelchipselectinputscanbe
|
||
definedandthedesiredchipselectcodeisfixedduringthemasking process.Thesethreeprogrammable chip
|
||
selectinputs,aswellasOR-tiecompatibility ontheoutputs, facilitate easymemory expansion.
|
||
The8316Areadonlymemory isfabricated withN-channel silicongatetechnology. Thistechnology provides the
|
||
designerwithhighperformance, easy-to-use MOScircuits. Onlyasingle+5Vpowersupplyisneededandall
|
||
devicesaredirectlyTTLcompatible.
|
||
PINCONFIGURATION BLOCKDIAGRAM
|
||
0,02 0304as0607Os
|
||
A,o
|
||
Ag
|
||
As
|
||
(/)
|
||
CHIPA7a:w
|
||
I.L SELECT
|
||
I.LPROG.A6:J
|
||
CD
|
||
~
|
||
As:J
|
||
0...
|
||
~
|
||
A4(/)
|
||
(/)w"""-CS,a:
|
||
A30 16,384BIT0« CELLMATRIX CHIP
|
||
A2SELECT"'--CS2 INPUT
|
||
A1 BUFFERS
|
||
Ao "-cs3
|
||
PINNAMES
|
||
AO·A,oADDRESS INPUTS
|
||
01.08OATAOUTPUTS
|
||
CS1·CS3PROGRAMMABLE CHIPSELECT INPUTS
|
||
5-61
|
||
|
||
===PAGE 126===
|
||
SI~ICON GATEMOSROM8316A
|
||
ABSOLUTE MAXIMUM RATINGS·
|
||
Ambient Temperature UnderBias O°Cto70°C
|
||
StorageTemperature -65°Cto+150°C
|
||
VoltageOnAnyPinWithRespect
|
||
ToGround. . . . . . . . . . . . . . . . . . . . ..-0.5Vto+7V
|
||
PowerDissipation ~. .1.0Watt
|
||
D.C.ANDOPERATING CHARACTERISTICS.
|
||
TA=O°Cto+70°C,Vee=5V±5%unlessotherwise specified*COMMENT: Stresses abovethoseIistedunder"Absolute Maximum
|
||
Ratings" maycausepermanent damagetothedevice.Thisisastress
|
||
ratingonlyandfunctional operation ofthedeviceattheseorany
|
||
otherconditions abovethoseindicated intheoperational sectionsof
|
||
thisspecification isnotimplied. Exposure toabsolute maximum rating
|
||
conditions forextended periodsmayaffectdevicereliability.
|
||
LIMITS
|
||
SYMBOL PARAMETERMIN.TYP.(1) MAX.UNIT TESTCONDITIONS
|
||
ILl InputLoadCurrent 10IlA VIN=0to5.25V
|
||
(AllInputPins)
|
||
ILOH OutputLeakageCurrent 10 IlA CS=2.2V,VOUT=4.0V
|
||
ILOL OutputLeakageCurrent -20 IlA CS=2.2V,VOUT=0.45V
|
||
ICC PowerSupplyCurrent 40 98 mA Allinputs5.25VDataOutOpen
|
||
VIL Input"Low"Voltage -0.5 '0.8 V
|
||
VIH Input"High"Voltage 2.0 VCC+1.OVV
|
||
VOL Output"Low"Voltage 0.45 V IOl=2.0mA
|
||
VOH Output"High"Voltage 2.2 V I0H=-100,uA
|
||
(1)TypicalvaluesforTA=25°eandnominal supplyvoltage.
|
||
A.C.CHARACTERISTICS
|
||
TA=O°Cto+70°C,Vee=+5V±5%unlessotherwise specified
|
||
LIMITS
|
||
SYMBOL PARAMETERMIN. Typ.(1) MAX.UNIT
|
||
tA AddresstoOutputDelayTime 400 850 nS
|
||
teo ChipSelecttoOutputEnableDelayTime 300 nS
|
||
tOF ChipDeselecttoOutputDataFloatDelayTime 0 300 nS
|
||
CONDITIONS OFTESTFOR
|
||
A.C.CHARACTERISTICS
|
||
OutputLoad...1TTLGate,andCLOAD=100pF
|
||
InputPulseLevels. . . . . . . . . . . . . . . 0.8to2.0V
|
||
InputPulseRiseandFallTimes.(10%to90%)20nS
|
||
TimingMeasurement Reference Level
|
||
Input 1.5V
|
||
Output 0.45Vto2.2VCAPACITANCE(2) TA=25°C,f=1MHz
|
||
LIMITS
|
||
SYMBOL TESTTYP. MAX.
|
||
CIN 'AllPinsExceptPinUnder 4pF 10pF
|
||
TestTiedtoACGround
|
||
COUT AllPinsExceptPinUnder 8pF 15pF
|
||
TestTiedtoACGround
|
||
(2)Thisparameter isperiodically sampled andisnot1000A»tested.
|
||
5-62
|
||
|
||
===PAGE 127===
|
||
SILICON GATEMOSROM831.6A
|
||
WAVEFORMS
|
||
ADDRESS
|
||
PROGRAMMABLE
|
||
CHIPSELECTStOF
|
||
5-63OU~TVALID1111.
|
||
|
||
===PAGE 128===
|
||
S.ILICO.N GATEMOSROM8316A
|
||
TYPICAL D.C.CHARACTERISTICS
|
||
ACCESS TIMEVS.AMBIENT
|
||
TEMPERATURE V,NLIMITSVS.TEMPERATURE
|
||
506070 1020TYPICAL1.8r----,r----r--.,r---r---.,r---r--_
|
||
1.6t----1t-----t----1t---t---I----f------f
|
||
VCC:;;:5.0V1.2t---t---l--t---t--------"t---t-------4
|
||
1.01ooo.---'1-----1_---'I--_"--_"--_.&...._--1
|
||
oent-l
|
||
~1.4t---t------t--t---t---t---t----f
|
||
z
|
||
->
|
||
80 60 20200t-----t---.:..-+-----+------t400r-----:=--...-==----t------t------I600....-~--+----t-----+---~800r----;----t----:::::;~--t---__I900.------,..---,------.-------.
|
||
OUTPUT SINKCURRENT VS.
|
||
OUTPUT VOLTAGEOUTPUT SOURCE CURRENT VS.
|
||
OUTPUT VOLTAGE
|
||
330
|
||
25
|
||
20
|
||
<'E15
|
||
-l
|
||
9
|
||
10
|
||
ov~I--
|
||
./
|
||
/V TYPICAL
|
||
V/
|
||
jVTA=25°C
|
||
VCCMIN
|
||
I/-30
|
||
-25
|
||
-20
|
||
<'E-15
|
||
~
|
||
9
|
||
-10
|
||
-5\
|
||
\
|
||
~
|
||
\TYPICAL
|
||
~
|
||
\TA=25°C
|
||
I\..VCC MIN
|
||
~
|
||
~
|
||
VOL(VOLTS) VOH(VOLTS)
|
||
ACCESS T"MEVS.LOAD
|
||
CAPACITANCESTATIC 'CCVS.AMBIENT TEMPERATURE
|
||
WORSTCASE
|
||
80 60 20O~-------I---------80I-----+---~!-----+------I
|
||
6Oi------+----t-----t-------t100------- .........~---------.
|
||
500 400WORSTCASE
|
||
200 300
|
||
CLOAO(pfd)100 oTYPICAL600I------+-----+----+----+-----t800I-----+----+----t----t-----t
|
||
4OO1-----fl-=:;;.----+----t----t-----t
|
||
200I-----+----I------t----t-----t1000---....--~--...,.--~~-......,
|
||
5-64
|
||
|
||
===PAGE 129===
|
||
MCS™
|
||
CUSTOM ROM
|
||
ORDERFORM8316A
|
||
ROM
|
||
CUSTOMER,------------------
|
||
P.O.NUMBER ----.;. _
|
||
OATE _
|
||
APp _S# ----:.
|
||
STO _ForInteluseonly
|
||
pppp--------
|
||
zz, _
|
||
00 _
|
||
OATE _
|
||
Allcustom8316AROMordersmustbesubmitted onthisform.Programming information shouldbesentintheformofcomputer
|
||
punched cardsorpunched papertapepertheformatsdesignated onthisorderform.Additional formsareavailable fromIntel.
|
||
INTELPATTERN NUMBER
|
||
.CHI"P"NUMBER OR
|
||
CUSTOMER NUMBERzz
|
||
DATE.CODE•8316AIxxxxMARKING
|
||
Themarking asshownattherightmustcontaintheIntel@logo, the
|
||
producttype(P8316A), the4-digitIntelpatternnumber(PPPP),adate
|
||
code(XXXX), andthe2-digitchipnumber(DD).Anoptionalcustomer
|
||
identification numbermaybesubstituted forthechipnumber(ZZ).
|
||
Optional Customer Number(maximum 9characters orspaces).
|
||
CUSTOMER"NUMBER _
|
||
MASKOPTION SPECIFICATIONS
|
||
A.CHIPNUMBER (Mustbe
|
||
specified-any numberfrom0through
|
||
7-00).
|
||
Thechipnumberwillbecodedin
|
||
termsofpositive logicwherealogic
|
||
II1"isahighlevelinput.
|
||
Chip
|
||
Number CS3 CS2 CS1
|
||
o 0 0 0
|
||
1 0a 1
|
||
2a 1a
|
||
3 0 1 1
|
||
4100
|
||
5101
|
||
6 1 . 1 a
|
||
7111B.ROMTruthTableFormat
|
||
Programming information shouldbe
|
||
sentintheformofcomputer punched
|
||
cardsorpunched papertape.Ineither
|
||
case,aprintout ofthetruthtable
|
||
shouldbeaccompanied withtheorder.
|
||
Thefollowing generalformatisapplic
|
||
abletotheprogramming information
|
||
senttoIntel:
|
||
•Datafields·should beorderedbegin
|
||
ningwiththeleastsignificant address
|
||
(0000)andendingwiththemostsig
|
||
nificantaddress(2047).
|
||
• Adatafieldshouldstartwiththe
|
||
mostsignificant bitandendwiththe
|
||
leastsignificant bit.•ThedatafieldshouldconsistofP's
|
||
andN's.A Pistoindicateahighlevel
|
||
output(mostpositive) andanN alow
|
||
leveloutput(mostnegative). Interms
|
||
ofpositive logic,a"Pisdefined.asa
|
||
logic111"andanNisdefined asalogic
|
||
110".Iftheprogramming information
|
||
issentonapunched papertape, the~
|
||
astartcharacter, B,andanendcharac
|
||
ter,F,mustbeusedinthedatafield.
|
||
1.Punched CardFormat
|
||
AnSO-column Hollerith card(prefer
|
||
ablyinterpreted) punched byanJ8M
|
||
026or029keypunch shouldbesub
|
||
mitted.Thefirstcardwillbeatitle
|
||
card;theformatisasfollows:
|
||
5-65
|
||
|
||
===PAGE 130===
|
||
a.TitleCard NO.OFOUTPUTS
|
||
TITLECARD 4or8
|
||
CUSTOMER'S1DESIGNATION CUSTOMER'S INTELPIN DECIMAL NUMBER1DIVISION ORI
|
||
COM~ANY NAME LOCATION CUSTOMER'S PINI INDICATING THEI' ,----....1..-------,,1 r--L-,~ TRUTHTABLENUMBER
|
||
r--;,~·'I·~l.~I:.~·LL[!":':_~.~·r"!:-,""·~.;~'~l~r.·)~· ~CO~~R~P--:.--!;:'~,"~:i':!":,ri~~~l;L""':'t4":":"ll.~. "':'C~:\L""':!I~.~....:-~l2~J~4:;.\ -.l-...:.:.(h~~·.~~{J~O
|
||
IIIIII I I I I I II II I
|
||
IIIIIII • I I I I
|
||
~~~~~!~!~,~I~I~,~!,~~~~~!~~~~~~~~~~~ ~~~!~~I~~~ ~~,~~~~~~~~ e~~~~e~~~~~~I~I~~~~~,!~ ~,~,~~\~~'~~!
|
||
Itlllllll!II!!!!!!II!IIIIIII!!llllllllllllllllllllllll11111111111111111111111\!1
|
||
2222222222222222222122222'222222222122222222222222222 22222221222222222'22222222227
|
||
1111))11311111111111 3111311111313313313311333313133333333333 I333333II33331333333
|
||
4U444U44444444444444444'"444444~UU4444444444444444~44444441444444441444444444
|
||
SSSSSSSSS~SISSSSISSSSSSSS~SSSSSS55SSIS55SSSSSS5S5555S5SS5S5S551S5SSS55S151SS5555
|
||
.66666666666666616666661666666666666& 66&6&&6&66&&6&1666&66&666L666666666666666666
|
||
,",11111'11'" 1111r1111111'" 1III1111111111111111111111111,," 11U111"111"1"
|
||
8883881888888888888888888888888888888888888888888888888 8888e8888888888811188888@
|
||
9999~99199 ~999199199 999199999999999999999991993991 9999999999 ~~~999999999~99q999q':II"'".0"': '''''I''·I'':t:'I:''/lr.l.;'"alOlll1I1!11\.1I1111101l1:'IUhIP·'''~·,,1\;'/10':." ..··,...··,:·:·:·,,,,.,.0':":;'.', "··t··.•
|
||
.'''I~'1
|
||
b.Fora2048wordX8-bitorganiza
|
||
tiononly,cards2'andthefollowing
|
||
cardsshouldbepunched asshown.
|
||
MSB
|
||
DECIMAL WORD (OUTPUT 8) LSB DECIMAL NUMBER
|
||
~~~:~~R~EGINNINGI I08U::~: ~IELDS ~~~;~~I:;L~~EUMBER
|
||
,L, I I· .I rl,
|
||
.':.":;.'!.'F'f1J-'rthr1rdt F'f'F'F'WthF' F'F'ftrtrtftH' f'f'F'rtttf'F'f1 F'Htf·ttff·f-'f-' t1Ufcttl'tF'F'f-' f1f1F'f-'t1tHif' f-'ttr'1f-'f'Wtf-' I,Ili'"
|
||
I1I11I11 11111111 11111111 11111111 11111111 11111111 IlIlIill 11111111
|
||
1111100000000000000000000000000000000000000000000000 00000000000 00000000000 000011I~:;i;;;i'i'i'['I";'I''II';';'I'~:I~:',;1:,17:; ~~~IIIiii~il;~~~;II"tl;l·tlr-r';';'~l ¥;l~'t~I[~'II~'i;at"j'II~i:lt",'~::,~: ~'~.~lj"11:\':Il~
|
||
22221221211n2212222222222222122 ZZ222222222222222222222222222222222222222Z22222Z
|
||
333JJ33333131333333J3333331JJJJlJ3J33333333333333333'33333333333333JJ333JJJ333JJJ
|
||
U44UUU4U4UU44444~~,ul••C,(I••• ~~4444444444~444444444444.4 44~4:4H4444~~.
|
||
~ss5~55I~11111 ~~55511155iS1111)):.)jIIS)155S1115:.:.:.11111 :.,i5SIIsSIII5~51155115)S5
|
||
,H6&t~66'£&6666666666Ettbi:b~lib~1161i6ii6ii£6&66£L0~~iiii66ii6C6iiEiiiiiiii0~0iitii500i:&EE0L6ii
|
||
,"111III1;::?iI111i:;I;III:1111/111111111 II1111111 /111/111111111 //111;ill;11;: 1
|
||
868888888 PEt8888888888888 Ii888888&a888888888 &8888&&e88~aEaa~858&388~6Eet560teeic.-
|
||
""~9~~~~s~q~~.q.~~~~)~.~1.9~~.~.~.~~~9Q0~~~~!~~9,~~~~,~.~~~~.~~.i~,1~tt:.;.:••;1'1'~.1.:~~. ,.~••• '~~".~~Column
|
||
1
|
||
2-5
|
||
6-30
|
||
31-34
|
||
35-54
|
||
55-57
|
||
58-66
|
||
67
|
||
68-75
|
||
76-78
|
||
79-80
|
||
Column
|
||
1-5
|
||
6
|
||
7-14
|
||
15
|
||
16-23
|
||
33
|
||
34-41
|
||
42
|
||
43-50
|
||
51
|
||
52-59
|
||
60
|
||
61-68
|
||
69
|
||
70-77
|
||
78
|
||
79-80Data
|
||
PunchaT
|
||
Blank
|
||
Customer Company Name
|
||
Blank
|
||
Customer's Company Divisionorlocation
|
||
Blank
|
||
Customer PartNumber
|
||
Blank
|
||
PunchtheIntel4-digitbasicpartnumber
|
||
andin( )thenumberofoutputbits,
|
||
e.g.,8316A(8).
|
||
Blank
|
||
Puncha2-digitdecimalnumbertoiden
|
||
tifythetruthtablenumber (mask
|
||
programmed chipselectnumber).
|
||
Data
|
||
Punchthe5-digitdecimal equivalent of
|
||
thebinarycodedlocation whichbe
|
||
ginseachcard.Theaddress isright
|
||
justified, Le.,00000,00008,00016,
|
||
etc.
|
||
Blank
|
||
DataField
|
||
Blank
|
||
DataField
|
||
Blank
|
||
DataField
|
||
Blank
|
||
DataField
|
||
Blank
|
||
DataField
|
||
Blank
|
||
DataField
|
||
Blank
|
||
DataField
|
||
Blank
|
||
Punchsame2-digitdecimalnumber asin
|
||
titlecard.
|
||
2.PaperTapeFormat
|
||
1"widepapertapeusing7-or8-bit
|
||
ASCIIcode,such·asamodel33ASR
|
||
teletype produces, orthe11/16"wide
|
||
papertapeusinga5-bitBaudotcode,
|
||
suchasaTelexproduces.
|
||
Theformatrequirements are'asfol
|
||
lows:
|
||
a.Allwordfieldsaretobepunched in
|
||
consecutive order,startingwithword
|
||
field0(alladdresses low).Theremust
|
||
beexactly2048wordfieldsforthe
|
||
2048X8ROMorganization.
|
||
b.Eachwordfieldmustbeginwith
|
||
thestartcharacter Bandendwiththe
|
||
stopcharacter F.Theremustbeex
|
||
actly8datacharacters between theB
|
||
andF.NOOTHER CHARACTERS, SUCH
|
||
ASRUBOUTS, AREALLOWED ANY
|
||
WHERE INAWORDFIELD.Ifinpre
|
||
paringatapeanerrorismade,theen
|
||
tirewordfield,including theBandF,
|
||
mustberubbedout.Withintheword
|
||
field,a Presultsinahighleveloutput
|
||
andanNresultsinalowleveloutput.
|
||
c.Preceding thefirstwordfieldand
|
||
following thelastwordfield,there
|
||
mustbealeader/trai lerlengthofat
|
||
least25characters. Thisshouldconsist
|
||
ofruboutornullpunches -(Jetterkey
|
||
forTelextapes).
|
||
d.Between wordfields,comments not
|
||
containing B'sorF'smaybeinserted.
|
||
Carriagereturnandlinefeedcharacters
|
||
shouldbeinserted asa"comment")justbeforeeachwordfield(oratleast
|
||
between everyfourwordfields).When
|
||
thesecarriagereturns,etc.,areinserted,
|
||
thetapemaybeeasilylistedonthe
|
||
teletype forpurposes oferrorcheck
|
||
ing.Thecustomer mayalsofindit
|
||
helpfultoinsertthewordnumber(as
|
||
acomment) atleasteveryfourword
|
||
fields.
|
||
e.Included inthetapebeforethe
|
||
leadershouldbethecustomer's com
|
||
pleteTelexorTWXnumber and,if
|
||
morethanonepattern isbeingtrans
|
||
mitted,theROMpatternnumber.
|
||
f.MSBandLSBarethemostandleast
|
||
significant bitofthedeviceoutputs.
|
||
Refertothedatasheetforthepin
|
||
numbers.
|
||
DataField LSB
|
||
WordFi~'d2048StartCharacter ~_ StapCharacter--1, , I I
|
||
Leader:RuboutKeyforTWXandLetter BPPP N N N N N F BN N N NN NPP F
|
||
KeyforTelex(atleast25frames). I 1L..' ---r- ----J
|
||
Ward'Field 0 WardlField 1
|
||
5-66MSB
|
||
t tBNPNPPPNNF
|
||
ITrailer:RubautKeyfarTWXandLet~~r
|
||
KeyforTelex{atleast.25framesL
|
||
|
||
===PAGE 131===
|
||
8101-2
|
||
8111-28102-2
|
||
8102A-4
|
||
81078-4RAMs
|
||
5101
|
||
8210
|
||
8222
|
||
|
||
===PAGE 132===
|
||
|
||
|
||
===PAGE 133===
|
||
SiliconGateMOS8101-2
|
||
1024BIT(256x4)STATICMOSRAM
|
||
WITHSEPARATE 1/0
|
||
•256x 4Organization toMeetNeeds
|
||
forSmallSystemMemories
|
||
•AccessTime-850nsecMax.
|
||
•Single+5VSupplyVoltage
|
||
•DirectlyTTLCompatible -AllInputs
|
||
andOutput
|
||
•StaticMOS-NoClocksor
|
||
Refreshing Required
|
||
•SimpleMemoryExpansion -Chip
|
||
EnableInput•InputsProtected -AllInputsHave
|
||
Protection AgainstStaticCharge
|
||
•LowCostPackaging -22PinPlastic
|
||
Dual-In-Line Configuration
|
||
•LowPower-Typically 150mW
|
||
•Three-State Output-OR-Tie
|
||
Capability
|
||
•OutputDisableProvided forEaseof
|
||
UseinCommon DataBusSystems
|
||
®TheIntel8101-2isa256wordby4bitstaticrandomaccessmemoryelementusingnormally offN-channel
|
||
MOSdevicesintegrated onamonolithic array.ItusesfullyDCstable(static)circuitry andtherefore requires
|
||
noclocksorrefreshing tooperate. Thedataisreadoutnondestructively andhasthesamepolarity asthe
|
||
inputdata.
|
||
The8101-2isdesignedformemoryapplications wherehighperformance, lowcost,largebitstorage,andsim
|
||
pleinterfacing areimportant designobjectives.
|
||
ItisdirectlyTTLcompatible inallrespects: inputs,outputs, andasingle+5Vsupply.Twochip-enables
|
||
alloweasyselection ofanindividual packagewhenoutputsareOR-tied. Anoutputdisableisprovided sothat
|
||
datainputsandoutputscanbetiedforcommon I/Osystems. Outputdisableisthenusedtoeliminate any
|
||
bidirectional logic.
|
||
®TheIntel8101-2isfabricated withN-channel silicongatetechnology. Thistechnology allowsthedesignand_
|
||
production ofhighperformance, easy-to-use MOScircuitsandprovides ahigherfunctional densityonamon
|
||
olithicchipthaneitherconventional MOStechnology orP-channel silicongatetechnology.
|
||
Intel'ssilicongatetechnology alsoprovides excellent protection againstcontamination. Thispermitstheuse
|
||
oflowcostsiliconepackaging.
|
||
@
|
||
---0Vee
|
||
~GND
|
||
o=PINNUMBERSCELLARRAY
|
||
32ROWS
|
||
32COLUMNSROW
|
||
SELECTAOBLOCKDIAGRAM
|
||
m~-.~
|
||
CE2~---I
|
||
00::>--4 >o-~R/W
|
||
DIN DATAINPUT 00 OUTPUT DISABLE
|
||
Ao-A., ADDRESS INPUTS DOUTDATAOUTPUT
|
||
RIW READIWRITE INPUT Vee POWER(+5V)
|
||
m,CE2 CHIPENABLE-PINCONFIGURATION LOGICSYMBOL
|
||
A322 VeeAo 01,
|
||
A221 A4 A, DO,
|
||
A, 20 RIWA2012
|
||
AoA3 0024 19 CElA4013
|
||
As 5 1800 As 003
|
||
8101-2 A68101-2 014 A6 6 17 CE2
|
||
A7 0°4
|
||
A7160°4
|
||
GNo 8 15 014 00
|
||
01, 9 140°3
|
||
DO, 10 13 013
|
||
01211 120°2
|
||
RIWCE2CEl
|
||
PINNAMES
|
||
5-67
|
||
|
||
===PAGE 134===
|
||
SILICON GATEMOS8101-2
|
||
Absolute Maximum Ratings*
|
||
Ambient Temperature UnderBias.. . ...O°Cto70°C
|
||
StorageTemperatu re... . . . . . . . . -650Cto+1500C
|
||
VoltageOnAnyPin
|
||
WithRespecttoGround. . . . . . ...-0.5Vto+7V
|
||
PowerDissipation . . . . . . . . . . . ..1Watt*COMMENT:
|
||
Stressesabovethoselistedunder''Absolute Maximum
|
||
Rating"maycausepermanent damage tothedevice.This
|
||
isastressratingonlyandfunctional operation ofthede
|
||
viceattheseoratanyothercondition abovethoseindi
|
||
catedintheoperational sectionsofthisspecification is
|
||
notimplied. Exposure toabsolute maximum ratingcon
|
||
ditionsforextended periodsmayaffectdevicereliability.
|
||
D.C.andOperating Charact~ristics
|
||
TA=o°cto70°C,Vee=5V±5%unlessotherwise specified.
|
||
V,N=0to5.25V
|
||
V,N=5.25V,10=OmA
|
||
TA=25°CCE=2.2V,VOUT=0.45VCE=2.2V,VOUT=4.0VTestConditions Symbol Parameter Min.Typ.[1] Max. Unit
|
||
ILl InputCurrent 10pA
|
||
ILOH 110LeakageCurrent[2] 15pA-
|
||
ILOL1/0LeakageCurrent[2] -50 J1A
|
||
lecl PowerSupplyCurrent 30 60rnA
|
||
~I~~;--l-p~~-;s~;~~c~;~;~~ 70mAVIN=5.25V.10=OmA--1- TA=O°C
|
||
~~:~;-_: ~_!~~~-~~~-==--------~
|
||
VOLIOutput"Low"Voltage +0.45VIOL =2.0mA
|
||
~E~~:=~utP~-t-·7~igh-~;\/oltage-~------ -------i2-+---=~== __~=-V____10H=-150p.A
|
||
NOTE: 1.TypicalvaluesareforTA=25()eandnominal supplyvoltage.
|
||
2.InputandOutputtiedtogether.
|
||
OUTPUT SOURCE CURRENT VS.
|
||
OUTPUT VOLTAGEOUTPUT SINKCURRENT VS.
|
||
OUTPUT VOLTAGE
|
||
: AMBIENT TEMPERATURE I
|
||
~.~O"l:l----l-----.-i-.-t-.-.--
|
||
:-f25CI I t'I
|
||
~l~t-+-- ---T~--
|
||
! !I!I
|
||
~-10.._.-I.-+----+----.I!
|
||
~ ,:I
|
||
_0 --,- -r.'I
|
||
-_.Vu4.75V
|
||
OUTPUT "HI(iH" TYPICAL
|
||
t.---"-'-~---+------""!I--t--- +---;
|
||
I o L-.-----'-_.....L.-----lo....-~_"O"- _
|
||
1
|
||
VOHIVOLlS) VOL(VOLTS)
|
||
5-68
|
||
|
||
===PAGE 135===
|
||
SILICON GATEMOS8101-2
|
||
A.C.Characteristics
|
||
READCYCLE TA=o°cto70°C,Vee=5V±5~/~,unlessotherwise specified.
|
||
Symbol Parameter=IMin. Typ. Max. Unit TestConditions
|
||
--~--_._---
|
||
tReyReadCycle ~ns----- .---.--
|
||
tA AccessTime 850 ns ____ ._.__u.___________~--- ~._----~._---
|
||
teo ChipEnableToOutput6~._~~(Seebelow)--_._-_ .._----
|
||
too OutputDisableToOutputr 550 ns._-----. -'--------_._----- ~-
|
||
200~--~~-1 tOF[1]DataOutputtoHighZState 0
|
||
--
|
||
tOHPrevious DataReadValidI0nsiafterchangeofAddress
|
||
WRITECYCLE
|
||
Symbol Parameter IMin. Typ. Max. Unit TestConditions
|
||
tweY WriteCyclei850 ns
|
||
tAW WriteDelay,
|
||
150 ns
|
||
tew ChipEnableToWrite-T750 ns
|
||
(Seebelow)
|
||
tDW DataSetup1500 ns--tOH DataHold 100 ns
|
||
WritePulse---_..._---- --j-------- t------- ,...--'
|
||
twp !630 ns
|
||
tWR WriteRecovery:50Insi,_---L-
|
||
A.C.CONDITIONS OFTEST Capacitance TA=25°C,f=1MHz
|
||
InputPulseLevels: +0.65Voltto2.2Volt
|
||
InputPulseRiseandFallTimes: 20nsec
|
||
1TTLGateandCL~.:100pFTimingMeasurement Reference Level:
|
||
OutputLoad:1.5Volt-
|
||
Symbol TestLimits(pF)
|
||
!Typ.Max.
|
||
CIN InputCapacitance48
|
||
~-(AllInputPins)VIN=OV
|
||
CoUT Output Capacitance VOUT=OV812
|
||
Waveforms
|
||
READCYCLE WRITECYCLE l2]
|
||
ADDRESS==:>c
|
||
CE2-......-....Il- tco--.I
|
||
CE2 /
|
||
-----"
|
||
DATA
|
||
IN'\'00~. /'OH
|
||
I'-- -..J
|
||
tA•tOF11;.'
|
||
DATA--1---- - - --y IJATAOUT
|
||
OUT__j ..A V_A_L_ID _ODJ
|
||
•tDf'j.- -.--.,tOH/.-·-=x ~_~_~:_L_I~ -_.__...:,t
|
||
tow ---.-.tAW;.....-- tw~
|
||
RW '\ ~p-J...R!
|
||
. I
|
||
NOTES: 1.tDFiswithrespecttothetrailingedgeofCE1,CE2,orOD,whichever occursfirst.
|
||
2.Duringthewritecycle,00isalogical1forcommon 1/0and"don'tcare"forsepJ~ate I/Ooperation.
|
||
3.00shouldbetiedlowforseparate I/Ooperation.00
|
||
(COMMON lID)131
|
||
5-69
|
||
|
||
===PAGE 136===
|
||
|
||
|
||
===PAGE 137===
|
||
SiliconGateMOS8111-2
|
||
1024BIT(256x4)STATICMOSRAM
|
||
WITHCOMMON I/OANDOUTPUT DISABLE
|
||
•Organization 256Wordsby4Bits
|
||
•AccessTime-850nsecMax.
|
||
•Common DataInputandOutput
|
||
•Single+5VSupplyVoltage
|
||
•DirectlyTTLCompatible -AllInputs
|
||
andOutput
|
||
•StaticMOS-NoClocksor
|
||
Refreshing Required
|
||
•SimpleMemoryExpansion -Chip
|
||
EnableInput•FullyDecoded -OnChipAddress
|
||
Decode
|
||
•InputsProtected -AllInputsHave
|
||
Protection AgainstStaticCharge
|
||
•LowCostPackaging -18PinPlastic
|
||
Dual-In-Line Configuration
|
||
•LowPower-Typically 150mW
|
||
•Three-State Output-OR-Tie
|
||
Capability
|
||
TheIntel®8111-2 isa256wordby4bitstaticrandomaccessmemoryelementusingnormally offN-channel
|
||
MOSdevicesintegrated onamonolithic array.ItusesfullyDCstable(static)circuitry andtherefore requires
|
||
noclocksorrefreshing tooperate. Thedataisreadoutnondestructively andhasthesamepolarity asthe
|
||
inputdata.Common input/output pinsareprovided.
|
||
The8111-2isdesigned formemoryapplications insmallsystemswherehighperformance, lowcost,largebit
|
||
storage,andsimpleinterfacing areimportant designobjectives.
|
||
ItisdirectlyTTLcompatible inallrespects: inputs,outputs, andasingle+5Vsupply.Separate chipenable
|
||
(CElleadsalloweasyselection ofanindividual packagewhenoutputsareOR-tied.
|
||
TheIntel®8111-2 isfabricated withN-channel silicongatetechnology. Thistechnology allowsthedesignand
|
||
production ofhighperformance, easy-to-use MOScircuitsandprovides ahigherfunctional densityonamon
|
||
olithicchipthaneitherconventional MOStechnology orP-channel silicongatetechnology.
|
||
Intel'ssilicongatetechnology alsoprovides excellent protection againstcontamination. Thispermitstheuse
|
||
oflowcostsiliconepackaging.
|
||
LOGICSYMBOL BLOCKDIAGRAM
|
||
o'PINNUMBERS@
|
||
-------0Vee
|
||
~GNO
|
||
MEMORY ARRAY
|
||
32ROWS
|
||
32COLUMNSROW
|
||
SELECTAO
|
||
A, I/O,
|
||
AzI/Oz
|
||
A31/03
|
||
A41/04
|
||
As8111-2
|
||
AO-A7 ADDRESS INPUTS
|
||
00 OUTPUT DISABLE
|
||
RIW READIWR ITEINPUT
|
||
CE, CHIPENABLE 1
|
||
CE2 CHIPENABLE 2
|
||
1/0,-1/04DATAINPUT/OUTPUTPINCONFIGURATION
|
||
A3 18Vee
|
||
A2 17A4
|
||
A, 16R/W
|
||
Ao4 15tEl
|
||
As58111-2 141/04
|
||
A66 131/03
|
||
A7 121/02
|
||
GNO 11I/O,
|
||
00 9 10CE2
|
||
PINNAMES
|
||
5-71
|
||
|
||
===PAGE 138===
|
||
SILICON GATEMOS8111-2
|
||
Absolute Maximum Ratings*
|
||
Ambient Temperature UnderBias.. . ...O°Cto70°C
|
||
StorageTemperature -65°Cto+150°C
|
||
VoltageOnAnyPin
|
||
WithRespecttoGround . . . . . . ...-0.5Vto+7V
|
||
PowerDissipation 1Watt*COMMENT:
|
||
Stressesabovethoselistedunder''Absolute Maximum
|
||
Rating"maycausepermanent damagetothedevice.This
|
||
isastressratingonlyandfunctional operation ofthede
|
||
viceattheseoratanyothercondition abovethoseindi
|
||
catedintheoperational sectionsofthisspecification is
|
||
notimplied. Exposure toabsolutemaximum ratingcon
|
||
ditionsforextended periodsmayaffectdevicereliability.
|
||
D.C.andOperating Characteristics
|
||
TA=O°Cto70°C,VCC=5V±5%,unlessotherwise specified.
|
||
Symbol Parameter Min.Typ.r1]Max. Unit TestConditions
|
||
III InputLoadCurrent 10 J.1AVIN=0to5.25V
|
||
IlOHI/OLeakageCurrent 15 J.1ACE=2.2V,VI/O=4.0V
|
||
IlOl I/OLeakageCurrent -50 J1ACE=2.2V,VI/a=0.45V
|
||
ICC1 PowerSupplyCurrent 30 60mA VIN=5.25V
|
||
11/0=OmA,TA=25°C
|
||
ICC2 PowerSupplyCurrent 70mAVIN=5.25V
|
||
11/0=OmA,TA=O°C
|
||
VIL InputLowVoltage -0.5 +0.65 V
|
||
VIH InputHighVoltage 2.2 Vcc V
|
||
Val OutputLowVoltage 0.45 V10l=2.0mA
|
||
VOH OutputHighVoltage 2.2 V10H=-150J.1A
|
||
NOTES: 1.TypicalvaluesareforTA=25°Candnominal supplyvoltage.
|
||
OUTPUT SOURCE CURRENT VS.
|
||
OUTPUT VOLTAGEOUTPUT SINKCURRENT VS.
|
||
OUTPUT VOLTAGE
|
||
1.5 1.0
|
||
VOL(VOLTS)0.515..--+---+--+-~~--+-------t
|
||
..Joi10~--4---+--'~-~-+--+------4
|
||
!
|
||
VOH(VOLTS)oL----L-_..L-.-..L.---.;;;~__.._. __.-.
|
||
1-5.-.----+--~-AMBIENT TEMPERATURE
|
||
-15~~-==--~ O°C-t----+---I----+--;
|
||
25°C
|
||
70°C
|
||
i-10~----4-..-+---+--t----t--+----1
|
||
!
|
||
~
|
||
.2
|
||
5-72
|
||
|
||
===PAGE 139===
|
||
SILICON GATEMOS8111-2
|
||
A.C.Characteristics
|
||
READCYCLE TA=o°cto70°C,Vee=5V±5%,unlessotherwise specified.
|
||
Symbol Parameter Min. Typ. Max. Unit TestConditions
|
||
tRCY ReadCycle 850 ns
|
||
tA AccessTime 850 ns
|
||
tco ChipEnableToOutput 650 ns (Seebelow)
|
||
too OutputDisableToOutput 550 ns
|
||
tOF[1]DataOutputtoHighZState 0 200 ns
|
||
tOHPreviousDataReadValid0 nsafterchangeofAddress
|
||
WRITECYCLE
|
||
Symbol Parameter Min. Typ. Max. Unit TestConditions
|
||
twCY WriteCycle 850 ns
|
||
tAW WriteDelay 150 ns
|
||
tcw ChipEnableToWrite 750 ns(Seebelow)
|
||
tow DataSetup 500 ns
|
||
tOH DataHold 100 ns
|
||
twP WritePulse 630 ns
|
||
tWR WriteRecovery 50 ns
|
||
A.C.CONDITIONS OFTEST Capacitance TA=25°C,f=1MHz
|
||
InputPulseLevels: +0.65Voltto2.2Volt
|
||
InputPulseRiseandFallTimes: 20nsec
|
||
1TTLGateandCL=100pFTimingMeasurement Reference Level:
|
||
OutputLoad:1.5VoltSymbol TestLimits(pF)
|
||
Typ.Max.
|
||
CIN InputCapacitance48(AllInputPins)VIN=OV
|
||
GoUT OutputCapacitance VOUT=OV1015
|
||
Waveforms
|
||
READCYCLE WRITECYCLE
|
||
DATAIN
|
||
STABLE----twey------ ..I
|
||
I~tOH
|
||
~tOF----.I....--tow---._........._""I..---tew--- ..I
|
||
OUTPUT
|
||
DISABLE
|
||
DATAI/OCHIP
|
||
ENABLESADDRESS
|
||
DATAOUT
|
||
VALIDOUTPUT
|
||
DISABLE1..-------tReY-----~
|
||
CHIP -.........-""1"-- teo
|
||
ENABLES
|
||
tCE1,CE2)ADDRESS
|
||
DATAI/O
|
||
1~-tAW--.I""-----" I_---+ "'"f4---lwp ------..............- tWR~
|
||
READ/
|
||
WRITE
|
||
NOTE:1.tOFiswithrespecttothetrailingedgeofeEl,CE2,or00,whichever occursfirst.
|
||
5-73
|
||
|
||
===PAGE 140===
|
||
|
||
|
||
===PAGE 141===
|
||
SiliconGateMOS8102-2
|
||
•SimpleMemoryExpansion -Chip
|
||
EnableInput
|
||
•FullyDecoded -OnChipAddress
|
||
Decode
|
||
•InputsProtected -AllInputsHave
|
||
Protection AgainstStaticCharge
|
||
•LowCostPackaging-16PinPlastic
|
||
Dual-In-Line Configuration1024BITFULLYDECODED STATIC MOS
|
||
RANDOM ACCESS MEMORY
|
||
•AccessTime-850nsMax.
|
||
•Single+5VoltsSupplyVoltage
|
||
•DirectlyTTLCompatible -AllInputs
|
||
andOutput
|
||
•StaticMOS-NoClocksor
|
||
Refreshing Required
|
||
•LowPower-Typically 150mW
|
||
•Three-State Output-OR-Tie
|
||
Capability
|
||
TheIntel@8102-2 isa1024wordbyonebitstaticrandom accessmemory elementusingnormally off
|
||
N-channel MOSdevicesintegrated onamonolithic array.ItusesfullyDCstable(static)circuitry and
|
||
therefore requires noclocksorrefreshing tooperate. Thedataisreadoutnondestructively andhasthe
|
||
samepolarity astheinputdata.
|
||
The8102-2 isdesigned formicrocomputer memory applications wherehighperformance, lowcost,large
|
||
bitstorage,andsimpleinterfacing areimportant designobjectives.
|
||
ItisdirectlyTTLcompatible inallrespects: inputs,output,andasingle+5voltsupply.Aseparate chip
|
||
enable(CE)leadallowseasyselectionofanindividual packagewhenoutputsareOR-tied.
|
||
TheIntel®8102-2 isfabricated withN-channel silicongatetechnology. Thistechnology allowsthedesign
|
||
andproduction ofhighperformance, easy-to-use MOScircuitsandprovides ahigherfunctional densityon
|
||
amonolithic chipthaneitherconventional MOStechnology orP-channel silicongatetechnology.
|
||
Intel'ssilicongatetechnology alsoprovides excellent protection againstcontamrnation. Thispermitsthe
|
||
useoflowcostsiliconepackaging.
|
||
BLOCKDIAGRAM PINCONFIGURATION LOGICSYMBOL
|
||
A6 16A7
|
||
As 2 15AsAo
|
||
A,
|
||
RIW 3 14Ag A2 DIN
|
||
AJ
|
||
A,4 13CE A48102-2 As8102-2
|
||
A25 12DATAOUTA6
|
||
AJ6 11DATAINA7
|
||
As DOUT
|
||
A47 10VeeAg
|
||
Ao 8 9GNDCER/W
|
||
PINNAMES
|
||
DIN DATAINPUT CECHIPENABLE
|
||
Ao-AgADDRESS INPUTS DOUTOATAOUTPUT
|
||
RIW READIWRITE INPUT VeePOWER(+5V)R/W
|
||
DATA
|
||
IN
|
||
0=PINNUMBERS
|
||
5-75CELL
|
||
ARRAY
|
||
32ROWS
|
||
32COLUMNS
|
||
COLUMN I/OCIRCUITSDATA
|
||
OUT
|
||
|
||
===PAGE 142===
|
||
SILICON GATEMOS8102-2
|
||
ABSOLUTE MAXIMUM RATINGS·
|
||
Ambient Temperature UnderBias
|
||
StorageTemperature
|
||
VoltageOnAnyPin
|
||
WithRespectToGround
|
||
PowerDissipation-O.5Vto+7V
|
||
. 1Watt*COMMENT:
|
||
Stressesabovethoselistedunder"Absolute Maxi
|
||
mumRating"maycausepermanent damagetothe
|
||
device.Thisisastressratingonlyandfunctional
|
||
operation ofthedeviceattheseoratanyoth~r
|
||
condition abovethoseindicated intheoperational
|
||
sectionsofthisspecification isnotimplied.Expo
|
||
suretoabsolute maximum ratingconditions for
|
||
extended periodsmayaffectdevicereliability.
|
||
D.C.ANDOPERATING CHARACTERISTICS
|
||
TA=OOCto+70°C,Vee=5V±5%unlessotherwise specified
|
||
LIMITS
|
||
SYMBOL PARAMETER~-- --UNIT TESTCONDITIONS
|
||
MIN. TYP.(1) MAX.-- ,
|
||
III INPUTLOADCURRENT 10 p.A VIN=0to5.25V
|
||
(ALLINPUTPINS)
|
||
ILOHOUTPUT LEAKAGE CURRENT 10 IJA CE=2.2V,VOUT=4.0V
|
||
IlOLOUTPUT LEAKAGE CURRENT -100 IJA CE=2.2V,VOUT=O.45V
|
||
'CC1POWERSUPPLY CURRENT 30 60ImA ALLINPUTS=5.25V
|
||
, DATAOUTOPEN
|
||
i IiTA=25°C
|
||
ICC2 POWERSUPPLYCURREN:=] 70
|
||
ImA ALLINPUTS=5.25V
|
||
DATAOUTOPEN
|
||
I TA=OOCi
|
||
VilINPUT"LOW"VOLTAGE -0.5 +0.65IV
|
||
V1HINPUT"HIGH"VOLTAGE 2.2 VeeiV
|
||
VOLOUTPUT "LOW"VOL-rAGE +0.45 !V'Ol=1.9mAI
|
||
VOHOUTPUT "HIGH"VOLTAGE 2.2I !IV 'OH=-100IJA
|
||
I
|
||
(1)TypicalvaluesareforTA=25°Candnominal supplyvoltage.
|
||
TYPICAL D.C.CHARACTERISTICS
|
||
POWERSUPPLVCURRENT VS.
|
||
AMBIENT TEMPERATUREPOWERSUPPLY CURRENT VS.
|
||
SUPPLY VOLTAGE
|
||
6 5 41050 4- - +-- .·l--,-+----+---1
|
||
AMBI~NT TEMPERAl URE~25°C\
|
||
40--~+_.---+----.~!-_+____f
|
||
~ I I I
|
||
E
|
||
t?30
|
||
<ta:w>20-_..t
|
||
<t
|
||
uu___o~.--.-iII
|
||
I I .V=525V
|
||
--+--T~'-- cc -
|
||
~4~! II :
|
||
-'~--i---±_I I._n,Y: I,..-.._
|
||
SPEC.iii
|
||
'-"--POINTS 1-
|
||
30
|
||
10~__ --t.- --..I-__ -----"
|
||
o1020304050607020---+.-., -+-..----+-80
|
||
70
|
||
~60
|
||
!
|
||
w500
|
||
<{
|
||
a:w>40
|
||
<{u_u
|
||
AMBIENT TEMPERATURE (OCI Vcr;(VOLTS)
|
||
5-76
|
||
|
||
===PAGE 143===
|
||
SILICON GATEMOS8102-2
|
||
A.C.CHARACTERISTICS TA=ooeto70oe,Vee=5V±5%unlessotherwise specified
|
||
SYMBOL
|
||
READCYCLEPARAMETERLIMITS--·---r----mT----
|
||
_.~~_~..._...l}YP._... ..L_~?<~._._UNIT
|
||
os
|
||
nsnsns
|
||
ns--t R-e------r-R--EA~D-C-Y--C-L-E--·------- --_..--------- 85o-·-···T -._-"--r.-_._.---"---'-
|
||
~~~~~~~---~--------~-_ .._-----~--~-- -_._----~._------ ~-----~
|
||
tAACCESS TIME I500i850-----~ _.-_.-.....-.---~-.- ----- -_.--.--.~-------.-----.--. ...--_..-------1-----------t···---_._.-
|
||
teo CHIPENABLE TOOUTPUT TIME : I500 _______ ~------_--- .---+ .._--l-. ~---
|
||
tOH1PREVIOUS READDATAVALIDWITHRESPECT 50I
|
||
TOADDRESS :----------4--------- ------·l- _.-_..--..-------~----.
|
||
PREVIOUS READDATAVALIDWITHRESPECT aI 1
|
||
TOCHIPENABLE i :_____"__ --J- _
|
||
WRITECYCLE
|
||
ns--~-C----~W-R-I-T-E-C-Y-C-L-E----------------T--8-~-r--~-~- !M
|
||
------.----+----.----- ...--.-.----- ....--.------------------- ..-- .__....__1_-- -.....+.-..-.-t-------
|
||
tAW ADDRESS TOWRITESETUPTIME I200' : !ns.----- ------+i ..--.----+-.-.-----.-- ..---~---.-----~---
|
||
~_tw_p +_W-R-IT-E-P-U-L-S-E-W-IDTH I~~L_. .+-...-n_--li---ns_-
|
||
tWR WRITERECOVERYTIME --t50: ! Ins
|
||
-----------1t-------------------------+------~~:------- ..~ i
|
||
__::_: -+--~_:_~_:_:_~_T_L~_P ~~EEt~~~-.±--=~=~L~==--+---~-:-
|
||
tcw CHIPENABLE TOWRITESETUPTIME I750! ;
|
||
(1)TypicalvaluesareforTA=250Candnominal supplyvoltage.
|
||
CAPACITANCE TA=25°C,f=1MHz
|
||
A.C.CONDITIONS OFTEST
|
||
InputPulseLevels: +0.65Voltto2.2Volt
|
||
InputPulseRiseandFallTimes: 20nsec
|
||
TimingMeasurement Reference Level: 1.5Volt
|
||
OutputLoad: 1TTLGateandCL=100pF._------_._-----
|
||
SYMBOL TESTLIMITS(pF)
|
||
TYP.MAX.---------_.- -_.--.._------
|
||
CININPUTCAPACITANCE35(ALLINPUTPINS)ViN::OV
|
||
COUTOUTPUT CAPACITANCE710VOUT=OV
|
||
WAVEFORMS
|
||
READCYCLE WRITECYCLE
|
||
DATASTABLE~----tow----~~~~----twP------...I..-----tew~----~It4-------twc---------I~
|
||
DATA DATACAN
|
||
INCHANGECHIP
|
||
ENABLE
|
||
READ/
|
||
WRITEteoADDRESSt4-------tRC-----~
|
||
~----tA-----""CHIP
|
||
ENABLE
|
||
DATA
|
||
OUT
|
||
5-77
|
||
|
||
===PAGE 144===
|
||
SILICON GATEMOS8102·2
|
||
TYPICAL D.C.CHARACTERISTICS
|
||
INPUTCURRENT VS.
|
||
INPUTVOLTAGE
|
||
-7.5-1OUTPUT SINKCURRENT VS.
|
||
bUTPUT VOLTAGE
|
||
1.5 1.0
|
||
VOL(VOLTS)0.5
|
||
VIN(VOLTS)EFFECTIVE INPUT
|
||
CHARACTERISTIC
|
||
I
|
||
Vee g5.0V
|
||
~~~b~.JVILMAX. (VIHMIN.
|
||
VIN(VOLTS)+1+2 +3 +4 +5+6Vee~5.0V
|
||
r TYPICAL+5
|
||
-5+2.5
|
||
OUTPUT SOURCE CURRENT VS.
|
||
OUTPUT VOLTAGEOUTPUT CURRENT VS.OUTPUT
|
||
VOLTAGE WITHCHIPDISABLEDRELATIONSHIP BETWEEN OUTPUT
|
||
SINKCURRENT, NUMBER OFOR-TIES,
|
||
ANDOUTPUT VOLTAGE
|
||
20
|
||
1216vcclg4.75~
|
||
/V[7
|
||
7
|
||
/
|
||
1.5
|
||
.40.45 .50 .55.60.65 .70 .75
|
||
VOL(VOLTS)4.3
|
||
3.9
|
||
3.5
|
||
ct3.1.g
|
||
~.22.7
|
||
2.3
|
||
1.9
|
||
VOUT(VOLTSt+1+2 +3 +4+5+6TYPICAL
|
||
CE g2.2Vr"T-+5
|
||
-20-1-15ct-5.g
|
||
~--10
|
||
VOH(VOLTS)AMBIENT TEMPERATURE
|
||
oac-+--+-~_---+-_-I
|
||
25°C
|
||
70°C
|
||
0----'_---10._--1-----:::......1.-_...10.0-_...1.----'
|
||
1-15
|
||
ct-10t-----.~__+---+--+---+--_+_---I
|
||
!
|
||
X.!'
|
||
TYPICAL A.C.CHARACTERISTICS
|
||
ACCESSTIMEYS.
|
||
LOADCAPACITANCEACCESS TIMEYS.
|
||
AMBIENT TEMPERATURE
|
||
1400
|
||
1200
|
||
1000
|
||
!800
|
||
c
|
||
~600
|
||
400IT
|
||
TAII25°C
|
||
VeeII4.75V_
|
||
1TTLLOAD
|
||
SPEC.POINT
|
||
4
|
||
------~
|
||
------~~l.1400
|
||
1200
|
||
1000
|
||
~800
|
||
<[
|
||
~600
|
||
400II
|
||
VeeII4.75V
|
||
1TTLLOAD_
|
||
Cl"lOOpF
|
||
SPEC.POINT•
|
||
l.....--."",..,-
|
||
.-.........~-----l-tP\CAl.
|
||
200 200
|
||
0050100150200 250 300350 0010203040506070
|
||
LOADCAPACITANCE (pFI AMBIENT TEMPERATURE (OCI
|
||
5-78
|
||
|
||
===PAGE 145===
|
||
SiliconGateMOS8102A-4
|
||
1024BITFULLYDECODED STATICMOS
|
||
RANDOM ACCESS MEMORY
|
||
•AccessTime-450nsMax.
|
||
•Single+5VoltsSupplyVoltage
|
||
•DirectlyTTLCompatible -AllInputs
|
||
andOutput
|
||
•StaticMOS-NoClocksor
|
||
Refreshing Required
|
||
•LowPower-Typically 150mW
|
||
•Three-State Output-OR-Tie
|
||
Capability•SimpleMemoryExpansion -Chip
|
||
EnableInput
|
||
•FullyDecoded -OnChipAddress
|
||
Decode
|
||
•InputsProtected -AllInputsHave
|
||
Protection AgainstStaticCharge
|
||
•LowCostPackaging -16PinPlastic
|
||
Dual-In-Line Configuration
|
||
TheIntel®S102A-4 isa1024wordbyonebitstaticrandomaccessmemory elementusingnormally off
|
||
N-channel MOSdevicesintegrated onamonolithic array.ItusesfullyDCstable(static)circuitry andthere
|
||
forerequires noclocksorrefreshing tooperate.Thedataisreadoutnondestructively andhasthesame
|
||
polarity astheinputdata.
|
||
The8102A-4 isdesigned formicrocomputer memory applications wherehighperformance, lowcost,large
|
||
bitstorage,andsimpleinterfacing areimportant designobjectives.
|
||
ItisdirectlyTTLcompatible inallrespects: inputs,output,andasingle+5voltsupply.Aseparatechip
|
||
enable(CE)leadallowseasyselection ofanindividual packagewhenoutputsareOR-tied.
|
||
®
|
||
TheIntel8102A-4isfabricated withN-channel silicongatetechnology. Thistechnology allowsthedesignand
|
||
production ofhighperformance, easy-to-use MOScircuitsandprovidesahigherfunctional densityonamon
|
||
olithicchipthaneitherconventional MOStechnology orP-channel silicongatetechnology.
|
||
Intel'ssilicongatetechnology alsoprovides excellent protection againstcontamination. Thispermitstheuse
|
||
oflowcostsiliconepackaging.
|
||
DATA
|
||
OUTCELL
|
||
ARRAY
|
||
32ROWS
|
||
32COLUMNS
|
||
COLUMN 110CIRCUITSBLOCKDIAGRAM
|
||
R/W
|
||
0=PINNUMBERSDATA
|
||
IN
|
||
DIN DATAINPUT CECHIPENABLE
|
||
Af}"Ag ADDRESS INPUTS DOUTOATAOUTPUT
|
||
R/W READIWRITE INPUT VeePOWER(+5V)PINCONFIGURATION LOGICSYMBOL
|
||
A6 16A7
|
||
As 2 15AsAo
|
||
A1
|
||
RIW 3 14 Ag A2 DIN
|
||
A3
|
||
A14 13CE A4
|
||
8102A-4 As8102A-4
|
||
A25 12DATAOUTAs
|
||
A36 11DATAINA7
|
||
As DOUT
|
||
A47 10VeeAg
|
||
Ao 8 9GNDCE R/W
|
||
PINNAMES
|
||
5-79
|
||
|
||
===PAGE 146===
|
||
SILICON GATEMOS8102A-4
|
||
ABSOLUTE MAXIMUM RATINGS·
|
||
Ambient Temperature UnderBias
|
||
StorageTemperature
|
||
VoltageOnAnyPin
|
||
WithRespectToGround
|
||
PowerDissipation-O.5Vto+7V
|
||
1Watt*COMMENT:
|
||
Stressesabovethoselistedunder"Absolute Maxi
|
||
mumRating"maycausepermanent damagetothe
|
||
device.Thisisastressratingonlyandfunctional
|
||
operation ofthedeviceattheseoratanyother
|
||
condition abovethoseindicated intheoperational
|
||
sectionsofthisspecification isnotimplied.Expo
|
||
suretoabsolute maximum ratingconditions for
|
||
extended periodsmayaffectdevicereliability.
|
||
D.C.ANDOPERATING CHARACTERISTICS
|
||
TA=O°Cto+70oe,Vcc=5V±5%unlessotherwise specified
|
||
LIMITS
|
||
SYMBOL PARAMETER
|
||
TYP.c1)UNIT TESTCONDITIONS
|
||
MIN. MAX.
|
||
ILl INPUTLOADCURRENT 10 J,J.A VIN= 0to5.25V
|
||
(ALLINPUTPINS)
|
||
ILOHOUTPUT LEAKAGE CURRENT 5 J,J.A CE=2.0V,vOUT=2.4to
|
||
ILOLOUTPUT LEAKAGE CURRENT -10 J,J.A CE=2.0V,vOUT=0.4V
|
||
ICC1POWERSUPPLY CURRENT 30 60 rnA ALLINPUTS=5.25V
|
||
DATAOUTOPEN
|
||
TA=25°C
|
||
ICC2POWERSUPPLY CURRENT 70 rnA ALLINPUTS=5.25V
|
||
OATAOUTOPEN
|
||
TA=DoC
|
||
VILINPUT"LOW"VOLTAGE -0.5 0.8 V
|
||
VIHINPUT"HIGH" VOLTAGE 2.0 Vcc V
|
||
VOLOUTPUT "LOW"VOLTAGE 0.4 V IOl=2.1mA
|
||
VOHOUTPUT "HIGH" VOLTAGE 2.4V IOH=-100J,J.A
|
||
(1).TypicalvaluesareforTA=250Candnominal supplyvoltage.
|
||
TYPICAL D.C.CHARACTERISTICS
|
||
POWERSUPPLY CURRENT VS.
|
||
AMBIENT TEMPERATURE
|
||
80__ -......,.....-~---r---r--.,.----,
|
||
70-----+---+----+---~
|
||
60«
|
||
..s
|
||
w50e"«a:w
|
||
40>«u_u
|
||
30
|
||
2060
|
||
50
|
||
40«
|
||
..s
|
||
w30e"«a:w20>«
|
||
u
|
||
~
|
||
10
|
||
0POWERSUPPLY CURRENT VS.
|
||
SUPPLY VOLTAGE
|
||
III I
|
||
AMBIENT TEMPERATURE =25°C
|
||
I
|
||
'............""
|
||
o(-.(v~~
|
||
V/
|
||
10'--__ ~____"_"""'O-'_..Ioo._--I.. __
|
||
o10203040506070
|
||
AMBIENT TEMPERATURE (OC)
|
||
5-803 4 5
|
||
Vee(VOLTS)6
|
||
|
||
===PAGE 147===
|
||
SILICON GATEMOS8102A-4
|
||
A.C.Characteristics TA=O°Cto70°C,Vee=5V±5%unlessotherwise specified
|
||
Limits
|
||
Symbol ParameterTypJ1]UnitMin. Max.
|
||
READCYCLE
|
||
tRC ReadCycle 450 ns
|
||
tA AccessTime 450 ns
|
||
tco ChipEnabletoOutputTime 230 ns
|
||
tOHl Previous ReadDataValidwithRespecttoAddress 40 ns
|
||
tOH2 Previous ReadDataValidwithRespecttoChipEnable 0 ns
|
||
WRITECYCLE
|
||
twc WriteCycle 450 ns
|
||
tAW AddresstoWriteSetupTime 20 ns
|
||
twP WritePulseWidth 300 ns
|
||
tWA WriteRecovery Time 0 ns
|
||
tow DataSetupTime 300 ns
|
||
tOH DataHoldTime 0 ns
|
||
tcw ChipEnabletoWriteSetupTime 300 ns
|
||
NOTE: 1.TypicalvaluesareforTA=25°Candnominal supplyvoltage.
|
||
Capacitancel21TA=25°C,f=1MHz
|
||
A.C.CONDITIONS OFTEST
|
||
InputPulseLevels: 0.8Voltto2.0Volt
|
||
InputRiseandFallTimes: 10nsec
|
||
TimingMeasurement Inputs: 1.5Volts
|
||
Reference Levels Output: 0.8and2.0Volts
|
||
OutputLoad: 1TTLGate!andCL=100pFSYMBOL TESTLIMITS(pF)
|
||
Typ.,[1] MAX.
|
||
C1NINPUTCAPACITANCE35(ALLINPUTPINS)V1N=:OV
|
||
COUTOUTPUT CAPACITANCE710VOUT=OV
|
||
NOTE: 2.Thisparameter isperiodically sampled
|
||
andisnot100%tested.
|
||
Waveforms
|
||
READCYCLE WRITECYCLE
|
||
tRC twe
|
||
ADDRESS CD
|
||
teo
|
||
CHIP CHIP'ew
|
||
ENABLE ENABLE
|
||
tA twP
|
||
DATA READI
|
||
OUT WRITE
|
||
CD1.5VOLTStow
|
||
®2.0VOLTS
|
||
fj)0.8VOLTSDATA DATA CANDATASTABLEINCHANGE
|
||
5-81
|
||
|
||
===PAGE 148===
|
||
SILICON GATEMOS8102A-4
|
||
TypicalD.C.andA.C.Characteristics
|
||
POWERSUPPLY CURRENT VS.
|
||
AMBIENT TEMPERATUREPOWERSUPPLY CURRENT VS.
|
||
SUPPLY VOLTAGE
|
||
15o10203040506070
|
||
TA(OC) Vee(VOLTS)If-- TA"'25°C-V./
|
||
/~PICAL/r
|
||
/
|
||
I35
|
||
5
|
||
110152530
|
||
ct
|
||
!20II
|
||
VeeMAX.-
|
||
............-..............~TYPICALr---___
|
||
........-
|
||
204045
|
||
35
|
||
i
|
||
~30
|
||
25
|
||
OUTPUT SOURCE CURRENT VS.
|
||
OUTPUT VOLTAGEOUTPUT SINKCURRENT VS.
|
||
OUTPUT VOLTAGE
|
||
-30
|
||
-25
|
||
-20
|
||
ct!-15
|
||
%
|
||
~
|
||
-10
|
||
-5"\..
|
||
\TYPICAL
|
||
~TA;:25°C
|
||
VeeMIN.
|
||
'~
|
||
'""'"30
|
||
25
|
||
20
|
||
15
|
||
10~,......,.....1-
|
||
VTYPICAL
|
||
/j'
|
||
/TA=25'C
|
||
JVeeMIN.
|
||
I
|
||
VOH(VOLTS) VOL(VOLTS)
|
||
1.6...----+--_+_-"".lTA..700C
|
||
CYCLETIME=350ns
|
||
~
|
||
0.951.00ACCESS TIMEVS.Vee
|
||
NORMALIZED TOVee=5.0V
|
||
1.05
|
||
1.2...----+--_+_-+---+----+--t----tVINLIMITSVS.TEMPERATURE
|
||
1.8
|
||
~....
|
||
~1.4...----+--_+_-+--+----+--t----t
|
||
Z>-
|
||
Vee"5.0V
|
||
1.00102030405060 70
|
||
TA(OC)4.0 4.5 5.0
|
||
Vee(VOLTS)5.5 6.0
|
||
ACCESS TIMEVS.
|
||
AMBIENT TEMPERATUREACCESS TIMEVS.
|
||
LOAD·CAPACITANCE
|
||
VeeMIN.
|
||
1TTLLOAD
|
||
c;."100pF350,...----,----,----r---r----'T"""'-.....,
|
||
TA"25°C
|
||
VeeMIN.
|
||
1TTLLOAD
|
||
250t-----+--TY .......P-ICA-L-+----+----I:=........,~--1250t-----t------i -=T---+---+--~
|
||
TYPICAL
|
||
c..-:.
|
||
150t-----+--+----+--+-----+--t----t 150t------I----t--+---t----t---i
|
||
OUTPUT REFERENCE LEVELS: VOH'"2.0V
|
||
VOLaO.8V
|
||
5OL.-----J...._..L-----L._.....L----L_ .........---'o102030405060 70
|
||
TA(OC)OUTPUT REFERENCE LEVEL" ,.5V
|
||
5O~---I._---I._---.l.---'-----""'"o100 200300 400500 600
|
||
CL(pF)
|
||
5-82
|
||
|
||
===PAGE 149===
|
||
SiliconGateMOS81078·4
|
||
FULLYDECODED RANDOM ACCESS
|
||
4096BITDYNAMIC MEMORY
|
||
*AccessTime··270nsmax.*Read,WriteCycleTimes--470 nsmax.
|
||
*RefreshPeriod--2ms
|
||
•LowCostPerBit •AddressRegisters
|
||
•LowStandby Power Incorporated ontheChip
|
||
•EasySystemInterface •SimpleMemoryExpansion-
|
||
•OnlyOneHighVoltage ChipSelectInputLead
|
||
InputSignal-ChipEnable •FullyDecoded -OnChip
|
||
•TTLCompatible --AllAddress, AddressDecode
|
||
Data,WriteEnable, •OutputisThreeStateand
|
||
ChipSelectInputs TTLCompatible
|
||
•Read-Modify-Write Cycle •IndustryStandard 22-Pin
|
||
Time_.590ns Configuration
|
||
TheIntel81078isa4096wordby1bitdynamic n-channel MOSRAM.Itwasdesigned formemory applications where
|
||
verylowcostandlargebitstorageareimportant designobjectives. The81078usesdynamic circuitry whichreducesthe
|
||
standby powerdissipation.
|
||
Reading information fromthememory isnon-destructive. Refreshing ismosteasilyaccomplished byperforming oneread
|
||
cycleoneachofthe64rowaddresses. Eachrowaddressmustberefreshed everytwomilliseconds. Thememory isre
|
||
freshedwhether ChipSelectisalogiconeoralogiczero.
|
||
The81078isfabricated withn-channel silicongatetechnology. Thistechnology allowsthedesignandproduction of
|
||
highperformance, easytouseMOScircuitsandprovides ahigherfunctional densityonamonolithic chipthanother
|
||
MOStechnologies. The81078usesasingletransistor celltoachievehighspeedandlowcost.Itisareplacement for
|
||
the81078.
|
||
Ao-A" ADDRESS INPUTS* VBBPOWER(-5V)
|
||
CE CHIPENABLE Vee POWER(+5V)
|
||
CS CHIPSELECT VOOPOWER(+12V)
|
||
DIN DATAINPUT VssGROUND
|
||
DOUTDATAOUTPUT WE WRITEENABLE
|
||
NC NOTCONNECTEDPINCONFIGURATION
|
||
81078
|
||
Vee Vss
|
||
Ag As
|
||
A,o A]
|
||
A" ~
|
||
CS Vee
|
||
o.N CE
|
||
DouT NC
|
||
Ao As
|
||
A, A.1
|
||
A2 A3
|
||
Vee WE
|
||
PINNAMES
|
||
*RefreshAddressAo-As'LOGICSYMBOL
|
||
81078
|
||
Ao
|
||
A,
|
||
A2DIN
|
||
AJ
|
||
A4
|
||
As
|
||
A6
|
||
A]DOUT
|
||
As
|
||
Ag
|
||
A,o
|
||
A"
|
||
CS CE WE
|
||
5-83BLOCKDIAGRAM
|
||
AO0----. .......0"be
|
||
A,0----.MEMORY~Vee
|
||
ROWDECODE 64A2andBUFFERARRAY ~Vss
|
||
AJ0----.REGISTER .......0"BB
|
||
A464x64
|
||
~0----.
|
||
f64
|
||
TIMINGCOLUMNCE0----. CONTROLAMPLIFIERSGENERATOR
|
||
64
|
||
DIN0----.
|
||
WE0----. I/O
|
||
CS0----.
|
||
|
||
===PAGE 150===
|
||
SILICON GATEMOS81078·4
|
||
Absolute Maximum Ratings*
|
||
Temperature UnderBias oocto70°C
|
||
StorageTemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..-65°Cto+1500C
|
||
AllInputorOutputVoltageswithRespecttothemostNegativeSupplyVoltage, Vee. . . . . . . . . . . . . . . . ..+25Vto-O.3V
|
||
SupplyVoltages Vee,Vcc,andVsswithRespecttoVee.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..+20Vto-O.3V
|
||
PowerDissipation 1.25W
|
||
*COMMENT:
|
||
Stressesabovethoselistedunder''Absolute Maximum Ratings" maycausepermanent damagetothedevice.Thisisastressrating
|
||
onlyandfunctional operation ofthedeviceattheseoranyotherconditions abovethoseindicated intheoperational sectionsof
|
||
thisspecification isnotimplied.Exposure toabsolutemaximum ratingconditions forextended periodsmayaffectdevicereliability.
|
||
D.C.andOperating Characteristics
|
||
TA=0°Cto70°C,Voo=+12V±5%,Vcc=+5V±5%,Vss[1]=-5V±5%,Vss=OV,unlessotherwise noted.
|
||
LimitsSymbol ParameterTyp.[2]UnitConditionsMin. Max.
|
||
IIIInputLoadCurrent.01 10 JJAVIN=VILMINtoV,HMAX(allinputsexceptCE)
|
||
Ilc InputLoadCurrent .01 10 JJAV,N=V,LMINtoV,HMAX
|
||
Illol OutputLeakageCurrent .01 10 JJACE=VILCorCS=V,H
|
||
forhighimpedance state Vo=OVto5.25V
|
||
1001VooSupplyCurrent110 200 JJACE=-1Vto+.6VduringCEoff[3]
|
||
'002VooSupplyCurrent80 100 mACE=V,HC,TA=25°CduringCEon
|
||
100AV1AverageVooCurrent 55 80 mACycletime=470ns, }
|
||
tCE=300ns TA=250C
|
||
IOOAV2 AverageVooCurrent 27 40 rnACycletime=1000ns,
|
||
tCE=300ns
|
||
ICC1[4]VecSupplyCurrent -
|
||
duringCEoff.01 10 JJACE=V'LCorCS=V,H
|
||
Iss VeBSupplyCurrent 5 100 JJA
|
||
Vil InputLowVoltage -1.0 0.6 VtT=20ns-SeeFigure4
|
||
VIH InputHighVoltage 2.4 VCC+l V
|
||
VllC CEInputLowVoltage -1.0 +1.0 V
|
||
VIHC CEInputHighVoltage Voo-l Voo+1 V
|
||
Val OutputLowVoltage 0.0 0.45 VIOl=2.0mA
|
||
VOHOutputHighVoltage 2.4 Vec V'OH=-2.0mA
|
||
NOTES:
|
||
1.Theonlyrequirement forthesequence 'ofapplying voltagetothedeviceisthatVOO,VCC,andVSSshouldneverbe.3Vmore
|
||
negative thanVSS.
|
||
2.TypicalvaluesareforTA=25°Candnominalpowersupplyvoltages.
|
||
3.TheIDOandICCcurrentsflowtoVSS'TheIBecurrentisthesumofallleakagecurrents.
|
||
4.DuringCEonVCCsupplycurrentisdependent onoutputloading,VCCisconnected tooutputbufferonly.
|
||
5-84
|
||
|
||
===PAGE 151===
|
||
SILICON GATEMOS81078·4
|
||
ADDRESS CANCHANGE0
|
||
14-----------t ce(300)----------~
|
||
\'JH--...--~-+------------------------_t-;-.....,r_----.,...--tAC(O)- .......-~
|
||
V,HC----+-----+-I..-oI!""!!----------------------- .....
|
||
CE
|
||
tcO(2S0)---------.1 .._----..-- t:(~~
|
||
OoUT.....IMP~6~NCE 1-_....iI... V_A_L_ID_-_-_-:.::=~~ ~:~~~:~
|
||
VoL- --II.~----------------- tACc(270) .1 tCF(O) :ADDRESS
|
||
AND~
|
||
\'ILReadandRefreshCycle [1)(Numbers inparentheses areforminimum cycletiminginns)
|
||
~-------------- tCy(470)----------------------~
|
||
------. -----..1
|
||
..-----tw'1S0)----ADDRESS CANCHANGECD
|
||
-tce(300)_._--- ._----_._--~------ tCy(470)---------
|
||
ADDRESSSTABLE
|
||
..---- tAH(SO)-----.
|
||
14-------- tcw(1S0)-----4-----~
|
||
DtNCANCHANGE®
|
||
®
|
||
DINV1H------~-----------~CE
|
||
o
|
||
V'LC---- .....-..11
|
||
WECANCHANGEV1HC--------i- ~~~---------------------- .....®
|
||
\'JH------+----------~V1L------t--------------I-- ...----....-----~~------_t_---
|
||
\'JL------t-----------~\'JH
|
||
ADDRESS
|
||
ANDCS
|
||
\'JLWriteCycle
|
||
'bH------- -----~
|
||
DOUT'-IMP~~~~CE -.~_....... --I11111111'.--- U_N_D_E_FI_N_E_D__......_IM_P~_ri~~_CE __'
|
||
VOL--- - ---,.-
|
||
teF(O)
|
||
NOTES: 1.ForRefreshcyclerowandcolumnaddresses mustbestablebeforetACandremainstableforentiretAHperiod.
|
||
2.VILMAXisthereference levelformeasuring timingoftheaddresses, CS,WE,andDIN.
|
||
3.VIHMINisthereference levelformeasuring timingoftheaddresses, CS,WE,andDIN.
|
||
4.VSS+2.0Visthereference levelformeasuring timingofCEo
|
||
5.VOO-2Visthereference levelformeasuring timingofCEo
|
||
6.VSS+2.0Visthereference levelformeasuring thetimingof00UT.
|
||
7.DuringCEhightypically O.5mAwillbedrawnfromanyaddresspinwhichisswitched fromlowtohigh.
|
||
5-85
|
||
|
||
===PAGE 152===
|
||
SILICON GATEMOS81078·4
|
||
A.C.Characteristics TA=oOcto700C,Voo=12V±5%,VCC=5V±10%,Vaa=-5V±5%,
|
||
READ,WRITE,ANDREADMODIFY /WRITECYCLEvss=OV,unlessotherwise noted.
|
||
Symbol Parameter Min. Max. Unit Conditions
|
||
tREF TimeBetween Refresh 2ms
|
||
tAC Address toCESetUpTime 0 ns tACismeasured fromendofaddresstransition
|
||
tAH Address HoldTime 100 ns
|
||
tcc CEOffTime 130 ns
|
||
tT CETransition Time 10 40 ns
|
||
tCF CEOfftoOutput 0 ns
|
||
HighImpedance-State
|
||
READCYCLE
|
||
Symbol Parameter Min. Max. Unit Conditions
|
||
tCY CycleTime 470 ns tT=20ns
|
||
tCE CEOnTime 3004000 ns
|
||
tco CEOutput Delay 250 ns C10ad=50pF,Load=OneTTLGate,
|
||
tACC AddresstoOutput Access 270 ns Ref=2.0V.
|
||
tWL CEtoWE 0 ns tACC=tAC+tco+1tT
|
||
twc WEtoCEon 0 ns
|
||
WRITECYCLE
|
||
Symbol Parameter Min. Max. Unit Conditions
|
||
tCY CycleTime 470 ns tT=20ns
|
||
tCE CEOnTime 3004000 ns
|
||
tw WEtoCEOff 150 ns
|
||
tcw CEtoWE 150 ns
|
||
tow[2]DINtoWESetUp 0 ns
|
||
tOH DINHoldTime 0 ns,
|
||
twP WEPulseWidth 50 ns
|
||
ReadModifyWriteCycle
|
||
Symbol Parameter Min. Max. Unit Conditions
|
||
tRwCReadModifyWrite(RMW) 590 ns tT=20ns
|
||
CycleTime
|
||
tCRWCEWidthDuringRMW 4204000 ns
|
||
!wcWEtoCEon 0 ns
|
||
twWEtoCEoff 150 nsC10ad=50pF,Load=OneTTLGate,
|
||
twp WEPulseWidth 50 nsRef=2.0V
|
||
tow DINtoWESetUp 0 ns
|
||
tOHDINHoldTime 0 ns
|
||
tcoCEtoOutputDelay 250 ns
|
||
tACCAccessTime 270 ns tACC=tAC+tco+ltT
|
||
5-86
|
||
|
||
===PAGE 153===
|
||
SILICON GATEMOS81078·4
|
||
TypicalCharacteristics
|
||
Fig.1.100AVVS.TEMPERATURE Fig.2.TYPICAL 100AVERAGE VS.CYCLETIME
|
||
tCE=300ns---f'~-t--""'~_t__-___t_-__1
|
||
II
|
||
tCE=230n5
|
||
O~- .........---....---'O""--------..-- ...........-----Io200 400 600 8001000 1200 140013t----+----+--I'---;----t-....-.....;;;-.....-----IVoo::z12.6V
|
||
Vee=-4.75V
|
||
VCC=5.25V
|
||
391-----4---+-.....-....::IIlr-+-----I1-- V1HC=13.6V
|
||
TA=25°C
|
||
~!
|
||
>26<t
|
||
o.E
|
||
70 50 25.2.0.-------.-------...------,
|
||
1.751--------4------+-----;
|
||
0w1.25N
|
||
:::i
|
||
<t:l:
|
||
IX:1.00Z
|
||
0.75>
|
||
~1.51----------+----- -+-----_1
|
||
_0
|
||
TCY(n51
|
||
40 35 30 25 20 15O----....--""""'----"'-----.a.-- .........--10Fig.4.TYPICAL V,LMAXVS.CERISETIME
|
||
1.8----,..--.....---......----,..--.....-- ___
|
||
1.4fllr------+----+---+----+----+------I1.61------+---+---+-----+---+------1
|
||
1.2
|
||
11.0
|
||
X
|
||
<{
|
||
0.8:E
|
||
.J0.6
|
||
0.4
|
||
0.2Fig.3.1002VS.TEMPERATURE
|
||
2.0
|
||
1.75
|
||
N°1.5_0
|
||
0w
|
||
N1.25~
|
||
<{
|
||
:l:a:1.00z
|
||
0.75
|
||
0.50 25 50 70
|
||
Fig.5.TYPICAL IOHVS.VOH Fig.6.TYPICAL IOlVS.VOL
|
||
-40t---~f-----+-----+-
|
||
-30
|
||
~!
|
||
~-20_0
|
||
-10
|
||
0------------'----""""'-'---01--- .............o40r----"T"'"""----r---- __--~--.....,
|
||
30t----+-----t-----+------+:.;'~-_I
|
||
~
|
||
!20t----+-----+-------7fIII-:-....L
|
||
..I
|
||
_0
|
||
101'---+-~____:IfII'9---.-_+_--_t_--_I
|
||
VOH(volts)VOL(volts)
|
||
Fig.7.TYPICAL REFRESH VS.TEMPERATURE Fig.8.TYPICAL ACCESS TIMEVS.TEMPERATURE
|
||
~~,C'-i<
|
||
70 25100~--..L-_-..L-_----~-- .....300r----"T"'"""---~-----r---_
|
||
250
|
||
..E
|
||
(J200(J
|
||
~~
|
||
150
|
||
70 25.11000
|
||
100
|
||
i10II..
|
||
W
|
||
~
|
||
TAIC)
|
||
5-87
|
||
|
||
===PAGE 154===
|
||
SILICON GATEMOS81078·4
|
||
ReadModifyWriteCycle£1]
|
||
Symbol Parameter Min.Max.Unit Conditions
|
||
tRWCReadModifyWrite(RMW) 590 ns tT=20ns
|
||
CycleTime
|
||
tCRWCEWidthDuringRMW 420 3000 ns
|
||
WCWEtoCEon 0 ns
|
||
twWEtoCEoff 150 ns
|
||
Cload=50pF,Load=OneTTLGate,
|
||
twp WEPulseWidth 50 nsRef=2.0V
|
||
tow DINtoWESetUp 0 ns
|
||
tOHDINHoldTime 0 ns
|
||
tcoCEtoOutput Delay 250 ns
|
||
tACCAccessTime 270 ns tACC=tAC+tco+ltT
|
||
(Numbers inparentheses areforminimum cycletiminginns.)
|
||
WECAN
|
||
CHANGEADDRESS CANCHANGE®
|
||
1..-------tw(150)---------1ADDRESS STABLE
|
||
®.--tAC(O)
|
||
~---tAH(50)----.f
|
||
~------------- tCRW(420)---------------~14------------------- tRWc(590)CD----------------- .....I
|
||
"'H-------lI-P ......------------ ......1VIHC----j---i-II------------------------------..l
|
||
CE'leH
|
||
ADDRESSES
|
||
ANDes
|
||
~l
|
||
--..-tow(O)
|
||
DINCAN
|
||
CHANGE
|
||
HIGH
|
||
IMPEDANCE
|
||
tCF(O)DtNSTABLE
|
||
-----VALlD--------.1~-----------------I-- -------- VOH---- -..---tcO(250)-----.1Vil----+-.....----------~DINCANCHANGEVIH----+-.....----------~
|
||
D-O-U-TIMP~~G:NCE
|
||
VOl----!:.._ ~__~ tAcc(270)-----.1
|
||
NOTES:
|
||
1.A.C.characteristics areguaranteed onlyifcumulative CEontimeduringtREFis~65%oftREF.Forcontinuous Read-Modify-Write
|
||
operation, tccandtRWCshouldbeincreased toatleast185nsand645ns,respectively.
|
||
2.V'LMAXisthereference levelformeasuring timingoftheaadresses, CS,WE,andDIN·
|
||
3.VIHMINisthereference levelformeasuring timingoftheaddresses, CS,WE,andDIN·
|
||
4.VSS+2.QVisthereference levelformeasuring timingofCEo
|
||
5.VOO-2Visthereference levelformeasuring timingofCEo
|
||
6.VSS+2.QVisthereference levelformeasuring thetimingofDOUT'
|
||
7.WEmustbeatVIHuntilendoftco.
|
||
8.DuringCEhightypically a.5mAwillbedrawnfromanyaddresspinwhichisswitched fromlowtohigh.
|
||
5-88
|
||
|
||
===PAGE 155===
|
||
SILICON GATEMOS81078·4
|
||
TypicalCurrentTransients Ys.Time
|
||
1002003004005000100200300400500
|
||
II I I IIII I II
|
||
CE~WRITE\JREAD\CYCLE CYCLE
|
||
30
|
||
20AJIce10
|
||
(rnA)0V V
|
||
2.0
|
||
1.5
|
||
NORMALIZED
|
||
1001.0
|
||
0.5
|
||
a
|
||
20
|
||
Iss10
|
||
(rnA)0
|
||
-10--f-....AP---....~~----IDo2 TYPICAL
|
||
Applications
|
||
Refresh
|
||
The81078-4 isrefreshed byeitherareadcycle,writecycle,orread-modify writecycle.Onlytheselectedrowof
|
||
niemoryarrayisrefreshed. TherowaddressisselectedbytheinputsignalsAOthruA5.Eachindividual row
|
||
addressmustreceiveatleastonerefreshcyclewithinanytwomilliseconds timeperiod.
|
||
Ifareadcycleisusedforrefreshing, thenthechipselectinput,CS,canbealogichighoralogiclow.Ifawrite
|
||
cycleorread-modify writecycleisusedtorefreshthedevice,thenCSmustbealogichigh.Thiswillprevent
|
||
writingintothememoryduringrefresh.
|
||
PowerDissipation
|
||
Theoperating powerdissipation ofaselecteddeviceisthesumofVoox100AVandVssxIss.Foracycleof
|
||
400nsandtCEof230nstypicalpowerdissipation is456mW.
|
||
Standby Power
|
||
The81078-4 isadynamic RAMtherefore whenVCE=VILCverylittlepowerisdissipated. Inatypicalsystem
|
||
mostdevicesareinstandbywithVCEatVILC.Duringthistimeonlyleakagecurrentsflow(Le.,1001,ICC1,
|
||
Iss,'LO','L1).Thepowerdissipated duringthisinactiveperiodistypically 1.4mW.Thetypicalpowerdissipa
|
||
tionrequiredtoperform refreshduringstandby istherefreshdutycycle,1.3%,multiplied bytheoperating
|
||
powerdissipation, or5.9mW.Thetotalpowerdissipation duringstandbyisthen7.3mWtypical.
|
||
SystemInterfaces andFiltering
|
||
Onthefollowing pageisanexampleofa16Kx 8bitmemorysystem.Devicedecoding isdonewiththeCEin
|
||
put.Alldevicesareunselected duringrefreshwithCS.Itisrecommended that1JJ.Fhighfrequency, lowinduc
|
||
tancecapacitors beusedondoublesidedboards.VCCtoVSSdecoupling isrequiredonlyonthedeviceslocated
|
||
aroundtheperiphery ofthearray.Foreach36devicesa100JJ.Ftantalum orequivalent capacitor shouldbe
|
||
placedfromVOOtoVSSclosetothearray.
|
||
5-89
|
||
|
||
===PAGE 156===
|
||
SILICON GATEMOS81078·4
|
||
TypicalSystem
|
||
Belowisanexample ofa16Kx 8bitmemorycircuit.Devicedecoding isdonewiththeCEinput.Alldevices
|
||
areunselected duringrefreshwithCSinput.The8210,8205and8212arestandard Intelproducts.
|
||
REFRESH0----+0- CS
|
||
8228{MEMWMEMR-------------
|
||
80801~~
|
||
Do.-------t'\/~-----.....I I/.~-----------------~0
|
||
7-----~A~-----........J,I_-------------------~
|
||
5-90
|
||
|
||
===PAGE 157===
|
||
intele
|
||
SiliconGateCMOS5101,5101-3,5101L,5101L·3
|
||
1024BIT(256x4)STATICCMOSRAM
|
||
*UltraLowStandbyCurrent:15nA/Bitforthe5101
|
||
•FastAccessTime-650ns
|
||
•Single+5VPowerSupply
|
||
•CE2ControlsUnconditional
|
||
StandbyMode•DirectlyTTLCompatible -All
|
||
InputsandOutputs
|
||
•Three-State Output
|
||
TheIntel®5101and5101-3areultra-low power1024bit(256wordsx4-bits)staticRAMsfabricated withanadvanced ion
|
||
implanted silicongateCMOStechnology. Thedeviceshavetwochipenableinputs.WhenCE2isatalowlevel,theminimum
|
||
standbycurrent isdrawnbythesedevices,regardless ofanyotherinputtransitions ontheaddresses andothercontrolinputs.
|
||
Also,whenCElisatahighlevelandaddressandothercontroltransitions areinhibited, theminimum standby currentis
|
||
drawnbythesedevices.Wheninstandby the5101and5101-3drawfromthesingle 5voltsupplyonly15microamps and
|
||
200microamps, respectively. Thesedevicesareideallysuitedforlowpowerapplications wherebatteryoperation orbattery
|
||
backupfornon-volatility arerequired.
|
||
The5101and5101-3usefullyDCstable(static)circuitry; itisnotnecessary topulsechipselectforeachaddresstransition.
|
||
Thedataisreadoutnon-destructively andhasthesamepolarity astheinputdata.AllinputsandoutputsaredirectlyTTL
|
||
compatible. The5101and5101-3haveseparate datainputanddataoutputterminals. Artoutputdisablefunction isprovided
|
||
sothatthedatainputsandoutputsmaybewireOR-edforuseincommon dataI/Osystems.
|
||
The5101Land5101L-3areidentical tothe5101and5101-3,respectively, withtheadditional featureofguaranteed data
|
||
retention atapowersupplyvoltageaslowas2.0volts.
|
||
Apincompatible N-channel staticRAM,theIntel2101,isalsoavailable forlowcostapplications wherea256x 4organi
|
||
zationisneeded.
|
||
TheIntelion-implanted, silicongate,complementary MOS(CMOS) allowsthedesignandproduction ofultra-low power,
|
||
highperformance memories.
|
||
DO,@V~ec
|
||
~GNO
|
||
o=PINNUMBERSCELLARRAY
|
||
32ROWS
|
||
32COLUMNSROW
|
||
DECODERSBLOCKDIAGRAM
|
||
@00011-014DATAINPUT 00 OUTPUT DISABLE
|
||
Ao-A., ADDRESS INPUTS 00,-004OATAOUTPUT
|
||
RIW READIWRITE INPUT Vee. POWER(+5VI
|
||
ffi,CE2 CHIPENABLEPINCONFIGURATION LOGICSYMBOL
|
||
5101 5101
|
||
A322 VeeAo
|
||
A22 21 A4 A,
|
||
A, 3 20RIWA2
|
||
Ao4 19 CE1A3
|
||
A4
|
||
As 5 1800 As
|
||
~6 17 CE2 ~
|
||
A7
|
||
A77 16004
|
||
GNO 8 15 01401, DO,
|
||
012002
|
||
01, 9 14003013003
|
||
DO, 10 13 013014 004
|
||
00
|
||
01211 12002 RIWCE2CE1
|
||
PINNAMES
|
||
5-91
|
||
|
||
===PAGE 158===
|
||
SILICON GATECMOS5101,5101-3, 5101L,5101L-3
|
||
Absolute Maximum Ratings*
|
||
Ambient Temperature UnderBias.. ...O°Cto70°C
|
||
StorageTemperature -65°Cto+150°C
|
||
VoltageOnAnyPin
|
||
WithRespecttoGround....-0.3VtoVee+0.3V
|
||
Maximum PowerSupplyVoltage +7.0V
|
||
PowerDissipation . . . . . . . . . . . . . . . . . ..1Watt*COMMENT:
|
||
Stresses abovethoselistedunder'Absolute Maximum
|
||
Rating"maycausepermanent damage tothedevice.This
|
||
isastressratingonlyandfunctional operation ofthedevice
|
||
attheseoratanyothercondition abovethoseindicated in
|
||
theoperational sectionsofthisspecification isnotimplied.
|
||
Exposure toabsolute maximum ratingconditions forex
|
||
tendedperiodsmayaffectdevicereliability.
|
||
D.C.andOperating Characteristics for5101,5101·3,5101L,5101L·3
|
||
TA=O°Cto70°C,Vee=5V±5%unlessotherwise specified.
|
||
Symbol Parameter Min.Typ.ll] Max.UnitTestConditions
|
||
'LI[2] InputCurrent 5 nAVIN=0to5.25V
|
||
'LOH[2]OutputHighLeakage 1p-ACE1=2.2V,VOuT=Vee
|
||
ILOL[2] OutputLowLeakage 1p-ACE1=2.2V,VOUT=O.OV
|
||
'CClOperating Current 9 22rnAVIN=VCCExceptCE1~0.01V
|
||
OutputsOpen
|
||
ICC2 Operating Current 13 27rnAVIN=2.2VExceptCE1~0.65V
|
||
OutputsOpen
|
||
5101Standby Current 15p-AVIN=0toVec,Except
|
||
'CCL[2l CE2~0.2V
|
||
5101-3StandbyCurrent 200 p-AVIN=0toVee,Except
|
||
'CCL[2] CE2~0.2V
|
||
Vil Input"Low"Voltage -0.3 0.65 V
|
||
VIH Input"High"Voltage 2.2 Vce V
|
||
VOL Output"Low"Voltage 0.4 VIOl=2.0rnA
|
||
VOH Output"High"Voltage 2.4 V'OH=1.0mA
|
||
LowVccDataRetention Characteristics (For5101Land5101L-3)TA=aoeto7aoe
|
||
Symbol Parameter Min.Typ.ll]Max.UnitTestConditions
|
||
VOR VeeforDataRetention 2.0 V
|
||
5101LDataRetention Current 15p-A VOR=2.0V
|
||
IceOR CE2~0.2V
|
||
5101L-3DataRetention Current 200 p-A VOR=2.0V
|
||
ICCCR
|
||
teoRChipDeselecttoDataRetention0 nsTime
|
||
tR Operation Recovery Time tRC[3] ns
|
||
NOTES: 1.TypicalvaluesareTA=250Candnominal supplyvoltage. 2.Currentthrough allinputsandoutputs included inICCl
|
||
measurement. 3.tRC=ReadCycleTime.
|
||
5-92
|
||
|
||
===PAGE 159===
|
||
SILICON GATECMOS5101,5101-3, 5101L,5101L-3
|
||
A.C.Characteristics for5101,5101·3,5101L,5101L-3
|
||
READCYCLE TA=o°cto70°C,Vcc=5V±5%,unlessotherwise specified.
|
||
Symbol Parameter Min. Typ. Max. Unit TestConditions
|
||
tAC ReadCycle 650 ns
|
||
tA AccessTime 650 ns
|
||
teol ChipEnable(CE1)toOutput 600 ns
|
||
ChipEnable(CE2)toOutput 700(Seebelow)
|
||
teo2 ns
|
||
too OutputDisableToOutput 350 ns
|
||
tOF DataOutputtoHighZState 0 150 ns
|
||
tOH1'Previous ReadDataValidwith0RespecttoAddress Changens
|
||
tOH2Previous ReadDataValidwith0RespecttoChipEnablens
|
||
WRITECYCLE
|
||
Symbol Parameter Min. Typ. Max. Unit TestConditions
|
||
twe WriteCycle 650 ns
|
||
tAW WriteDelay 150 ns
|
||
tewl ChipEnable(CE1)ToWrite 550 ns(Seebelow)
|
||
tCW2 ChipEnable(CE2)ToWrite 550 ns
|
||
tow DataSetup 400 ns
|
||
tOH DataHold 100 ns
|
||
twP WritePulse 400 ns
|
||
tWA WriteRecovery 50 ns
|
||
tos OutputDisableSetup 150 ns
|
||
A.C.CONDITIONS OFTEST C-18 [2]apacineeTA=25°C,f=1MHz
|
||
InputPulseLevels: +0.65Voltto2.2Volt
|
||
InputPulseRiseandFallTimes: 20nsec
|
||
1TTLGateandCL=100pFTimingMeasurement Reference Level:
|
||
OutputLoad:1.5VoltSymbol TestLimits(pF)
|
||
Typ.Max.
|
||
C1N InputCapacitance48(AllInputPins)V1N=OV
|
||
GoUT OutputCapacitance VOUT=OV812
|
||
5-93
|
||
|
||
===PAGE 160===
|
||
SILICON GATECMOS5101,5101-3, 5101L,5101L-3
|
||
Waveforms
|
||
WRITECYCLE
|
||
DATAIN
|
||
STABLE14----- tew1--- ...1..------- twe------~
|
||
~I----- tCW2------.t
|
||
1..---- tDw---~
|
||
--.tAW104----twP----.I ~__-+__
|
||
RIWCE2
|
||
DATA
|
||
INADDRESS
|
||
00
|
||
(COMMON I/O)(4)CE2
|
||
DATA
|
||
OUTADDRESSREADCYCLE..-- _
|
||
00
|
||
(COMMON I/O)(3]
|
||
NOTES: 1.TypicalvaluesareforTA=25°Candnominal supplyvoltage.
|
||
2.Thisparameter isperiodically sampled andisnot100%tested.
|
||
3.00maybetiedlowforseparate I/Ooperation.
|
||
4.Duringthewritecycle,00is"high"forcommon I/Oand
|
||
"don'tcare"forseparate I/Ooperation.
|
||
LowVCCDataRetention
|
||
DATARETENTION
|
||
MODE
|
||
SUPPLVVOLTAGE (Vee)
|
||
®
|
||
CHIPENABLE (CE2)@ @
|
||
W----------------<D4.75V
|
||
®VOR®VIH
|
||
@O.2V
|
||
5-94
|
||
|
||
===PAGE 161===
|
||
Schottky Bipolar8210
|
||
TTL-TO-MOS LEVELSHIFTER AND
|
||
HIGHVOLTAGE CLOCKDRIVER
|
||
•FourLowVoltageDrivers
|
||
•OneHighVoltageDriver
|
||
•TTLandOTlCompatible Inputs
|
||
•OutputsCompatible with
|
||
8107AMOSMemories•Operates fromStandard Bipolarand
|
||
MOSPowerSupplies
|
||
•Maximum MOSDeviceProtection
|
||
OutputClampDiodes
|
||
TheIntel®8210isaBipolar-to-MOS levelshifterandhighvoltagedriverwhichacceptsTTLandDTLinputs.
|
||
Itcontains four(4)lowvoltagedriversandonehighvoltagedriver,eachwithcurrentdrivingcapabilities
|
||
suitablefordrivingN-channel MOSmemorydevices. The8210isparticularly suitablefordrivingthe8107A
|
||
N-channel MOSmemory chips.The8210operates fromthe5voltand12voltpowersuppliesusedtobias
|
||
thememorydevices.
|
||
Thefourlowvoltagedriversfeaturetwocommon enableinputsperpairofdriverswhichpermitsaddressor
|
||
datadecoding. Thehighvoltagedriverswingsthe12voltsrequiredtodrivethechipenable(clock)input
|
||
forthe8107A.
|
||
The8210highvoltagedriverrequires anexternally connected PNPtransistor. ThePNPbaseisconnected
|
||
topin12,thecollector topin11,andtheemittertopin10orVoo.Theuseofafastswitching, highvol
|
||
tage,highcurrentgainPNP,likethe2N5057 isrecommended.
|
||
PINCONFIGURATION LOGICSYMBOL
|
||
°1
|
||
DATAINPUTD7 18Vee
|
||
ENABLE INPUTEA2 17D1DATAINPUTEA
|
||
DATAINPUT023 1601LOWVOLTAGE OUTPUTD2 01
|
||
DATAINPUTD34 15O2LOWVOLTAGE OUTPUT D3 °2
|
||
ENABLE INPUTEB58210 1403LOWVOLTAGE OUTPUTEB °3
|
||
DATAINPUT046 1304LOWVOLTAGE OUTPUT
|
||
04 04
|
||
DATAINPUT057 12BBASEOFPNP
|
||
D7 B
|
||
DATAINPUT068 1105HIGHVOLTAGE OUTPUT
|
||
D5
|
||
GND 9 10Voo05
|
||
°6
|
||
5-95
|
||
|
||
===PAGE 162===
|
||
SCHOTTKY BIPOLAR 8210
|
||
A.C.Characteristics TA=O°Cto70°C,VCC=5.0V±5%,VDD=12V±5%
|
||
Symbol Parameter Min. Typ. Max. Unit
|
||
tLd+ DelayPlusRiseTimeforLowVoltageDrivers 5 13 20 ns
|
||
tLd- DelayPlusFallTimeforLowVoltageDrivers 5 13 20 ns
|
||
tHd+ DelayPlusRiseTimeforHighVoltageDriver 10 30 40 ns
|
||
tHd- DelayPlusFallTimeforHighVoltageDriver 10 30 40 ns
|
||
A.C.CONDITIONS OFTEST
|
||
Symbol Test Typ. Max.
|
||
CIN InputCapacitance 6pF 12pF
|
||
*Thisparameter isperiodically sampled andisnot100%tested.
|
||
Condition ofmeasurement isf= 1MHz,Vbias=2V, VCC=OV,
|
||
andTA =25°C.TestLoad:CL=200pFforLowVoltageDrivers,
|
||
CL=350pFforHighVoltageDrivers
|
||
InputPulseAmplitudes: 3.0V
|
||
InputPulseRiseandFallTimes:5nsbetween
|
||
1voltand2volts
|
||
Measurement Points:SeeWaveforms
|
||
Waveforms Application
|
||
HIGHVOLTAGE DRIVER HIGHVOLTAGE OUTPUT CONNECTIONS
|
||
USE2N5057OR
|
||
EQUIVALENT PNP
|
||
TRANSISTOR,..-----+---- OUTPUT 1.5V
|
||
tVoo--------T- - - - - ---- - - - - ----
|
||
2V
|
||
GND---f-------T---T-----
|
||
4---tHd+-1 l~tHd--INPUT
|
||
LOWVOLTAGE DRIVER
|
||
T---
|
||
1.5V'4--tLd--~-------~----------------
|
||
~ 1.5V
|
||
~ I ~
|
||
GND---+1---T;----1
|
||
1~ILd+-1INPUT
|
||
5-96
|
||
|
||
===PAGE 163===
|
||
SCHOTTKY BIPOLAR 8210
|
||
Absolute Maximum Ratings*
|
||
Temperature UnderBias o°cto70°C
|
||
StorageTemperature -65°Cto+150°C
|
||
SupplyVoltage,Vee -0.5to+7V
|
||
SupplyVoltage,Voo -0.5to+13VAllInputVoltages -1.0to+5.5V
|
||
OutputsforLowVoltageDrivers. . . . . ...-0.5to+7V
|
||
OutputsforClockDriver -1.0to+13V
|
||
PowerDissipation at25°C 2W
|
||
*COMMENT: Stressesabovethoselistedunder"Absolute Maximum Ratings" maycausepermanent damagetothedevice.This.isa
|
||
stressratingonlyandfunctional operation ofthedeviceattheseoranyotherconditions abovethoseindicated intheoperational sec
|
||
tionsofthisspecification isnotimplied. Exposure toabsolute maximum ratingconditions forextended periodsmayaffectdevice
|
||
reliability.
|
||
D.C.Characteristics TA=O°Cto70°C,VCC=5.QV±5%,VDD=12V±5%
|
||
Symbol Parameter Min. Max. Unit TestConditions.
|
||
'FODataInputLoadCurrent -0.25 mA VF=0.45V
|
||
IFE EnableInputLoadCurrent -0.50 mA VF=0.45V
|
||
IRO Data .1nputLeakageCurrent 10 p.A VR=12.6V
|
||
IRE EnableInputLeakageCurrent 20 p.A VR=12.6V
|
||
VOLOutputLowVoltage 0.45 V IOl=3mA,V1H=2V
|
||
forallDrivers -1.0 V IOl=-5mA
|
||
VOH1OutputHighVoltage Vee-1.0 V IOH=-1mA,Vil=0.8V
|
||
forLowVoltage0rivers VCC+1.0 V 'OH=5mA
|
||
VOH2OutputHighVoltage VOO-0.75 V IOH=-1mA,Vll=0.8V
|
||
forHighVoltageDriver VOO+0.5 V IOH=5mA
|
||
101PulsedOutputSinkCurrent75 mA Vo=2V,VIH=2VforLowVoltageDrivers
|
||
102PulsedOutputSinkCurrent100 mA VO=3V, VIH=2VforHighVoltageDriver
|
||
103PulsedOutputSourceCurrent-75 mAVo=VCC-1.5V,
|
||
forLowVoltageDrivers VIL=O.8V
|
||
104PulsedOutputSourceCurrent-100 mAVa=Voo-3V,
|
||
forHighVoltageDriver VIL=0.8V
|
||
VIL InputLowVoltage,AllInputs 0.8 V
|
||
VIH InputHighVoltage,AllInputs 2 V
|
||
POWERSUPPLY CURRENT DRAINANDPOWERDISSIPATION
|
||
Alldriveroutputsareinthestateindicated
|
||
TestConditions -- Inputstatestoensure
|
||
thefollowing outputstates: Additional Test
|
||
Symbol Parameter Typ.l1]Max.UnitAllLowVoltage HighVoltage Conditions
|
||
Outputs Output
|
||
leCl CurrentfromVce 2635mA Low Low
|
||
1001 CurrentfromVoo 1216mA Low Low
|
||
POl PowerDissipation 290390 mW Low Low
|
||
ICC2 CurrentfromVcc 2128'mA Low High
|
||
1002 CurrentfromVoo 2635mA Low High
|
||
P02 Power0issipation 450600 mW Low High VCC=5.25V,
|
||
leC3 CurrentfromVec 1925mA High LowVoo=12.6V
|
||
1003 CurrentfromVoo 12 16mA High Low
|
||
P03 Power0issipation 260340 mW High Low
|
||
ICC4 CurrentfromVce 1418mA High High
|
||
1004 CurrentfromVoo2635mA High High
|
||
PD4 Power0issipation 410550 mW High High
|
||
[l]Thisparameter isperiodically sampled andisnot100%tested.Condition ofmeasurement isTA=25°C,VCC=5V,VOO=12V.
|
||
5-97
|
||
|
||
===PAGE 164===
|
||
SCHOTTKY BIPOLAR 8210
|
||
TypicalSystem
|
||
Belowisanexample ofa16Kx 8bitmemorycircuit.Devicedecoding isdonewiththeCEinput.Alldevices
|
||
areunselected duringrefreshwithCSi~put.The8210,8205and8212arestandard Intelproducts.
|
||
REFRESH
|
||
0-----+--1 cs
|
||
8228{MEMWMEMR-----4 __-----~
|
||
8080f~~
|
||
Do.-------i"J"I------ ........I/'...-----------------~
|
||
07-------t/',J-------J'\.I------------------~
|
||
5-98
|
||
|
||
===PAGE 165===
|
||
SchottkyBipolar8222
|
||
DYNAMIC MEMORY
|
||
REFRESH CONTROLLER
|
||
BLOCKDIAGRAM• InternalAddress
|
||
Multiplexer
|
||
•Upto6Ro.
|
||
(64x64,t}'
|
||
'\ff
|
||
PINCONFIGURATION•Adjustable Refresh
|
||
Request Oscillator
|
||
•Idealfor8107A,81078
|
||
4KRAMRefresh
|
||
STARTCYCLE
|
||
CYC.REQ. REFRESH ACK
|
||
BUSYREQUEST
|
||
REF.ON a LOGIC
|
||
REFREQ
|
||
CYREQ
|
||
STARTCY
|
||
ADDRESS INPUTA2 CENTER
|
||
ADDRESS INPUTA1
|
||
OUTPUT
|
||
ADDRESS INPUTAoA4ADDRESS INPUT MUX ADDRESSES
|
||
INPUTAo-As
|
||
ADDRESS OUTPUT 00 AsADDRESS INPUT ADDRESSES
|
||
ADDRESS OUTPUT 01 Vee
|
||
ADDRESS OUTPUT 02 04ADDRESS OUTPUT
|
||
cX/Rxl---REF.
|
||
GROUND 03ADDRESS OUTPUTREa. Dosc.
|
||
I
|
||
-=-The8222isarefreshcontroller fordynamic RAMsrequiring rowref.JJj"\:;; WinR,~"addresses (or4Kbitsfor64x
|
||
,'<:i"~:/:, 0 , ~'~64organization). Thedevicecontains anaccurate refreshtimer (w~~)t::,~rL, ,"'"nbe,,-setbyanexternalresistorandca-
|
||
,:~\~'r',;":::--:,0,<,:,,,:-,:<':). ,.:-~~
|
||
pacitor)plusallnecessary controlandI/Ocircuitry toprovide ~~fi~~"'~\';ra~f'~t{sM'.'f~~uirem~ts ofdynamic RAMs.Thechip's
|
||
highperformance makesitespecially suitableforusewith hi9Q{(-'-~>~~":;;~~~b_,~~J;~RAIYl~1ike the81078.The8222isdesigned
|
||
forlarge,asynchronously driven,dynamic memory systems. ~~';;~~;~'~"!J;F~j») eft
|
||
5-99
|
||
|
||
===PAGE 166===
|
||
|
||
|
||
===PAGE 167===
|
||
I/O
|
||
8212
|
||
8255
|
||
8251
|
||
|
||
===PAGE 168===
|
||
|
||
|
||
===PAGE 169===
|
||
Schottky Bipolar8212
|
||
EIGHT-BIT INPUT/OUTPUT PORT
|
||
•FullyParallel8-BitData
|
||
Register andBuffer
|
||
•ServiceRequest Flip-Flop
|
||
forInterrupt Generation
|
||
•LowInputLoadCurrent
|
||
.25mAMax.
|
||
•ThreeStateOutputs
|
||
•OutputsSink1.5mA•3.65VOutputHighVoltage
|
||
forDirectInterface to8080
|
||
CPUor8008CPU
|
||
•Asynchronous Register
|
||
Clear
|
||
•Replaces Buffers,Latches
|
||
andMultiplexers inMicro
|
||
computer Systems
|
||
•Reduces SystemPackage
|
||
Count
|
||
The8212input/output portconsistsofan8-bitlatchwith3-stateoutputbuffersalongwithcontrolanddeviceselection
|
||
logic.Alsoincluded isaservicerequestflip-flop forthegeneration andcontrolofinterrupts tothemicroprocessor.
|
||
Thedeviceismultimode innature.Itcanbeusedtoimplement latches,gatedbuffersormultiplexers. Thus,alloftheprinci
|
||
palperipheral andinput/output functions ofamicrocomputer systemcanbeimplemented withthisdevice.
|
||
PINCONFIGURATI"ON
|
||
OS1 vee
|
||
MO INT
|
||
01, Dla
|
||
DO, OOa
|
||
012017
|
||
0°2 0°7
|
||
013016
|
||
003 0°6
|
||
014 015
|
||
0°4 0°5
|
||
STB CLR
|
||
GND DS2
|
||
PINNAMES
|
||
01,.01& DATAIN
|
||
oo,-DOa DATAOUT
|
||
DSi-DS2DEVICESELECT
|
||
MD MODE
|
||
STB STROBE
|
||
INT INTERRUPT (ACTIVE LOW)
|
||
CLR CLEAR(ACTIVE LOW)
|
||
5-101LOGICDIAGRAM
|
||
SERVICE REQUEST FF
|
||
\
|
||
DEVICE SELECTION
|
||
-~[DOS1
|
||
I!DOS2
|
||
~MO----+- ........L-~
|
||
[i>STB----...----
|
||
11>013------- ....................
|
||
[[>014---------+--+-4
|
||
[9DI5-------~ .......
|
||
[g>018---------1- .......
|
||
(ACTIVE LOW)OUTPUT
|
||
BUFFER
|
||
|
||
===PAGE 170===
|
||
SCHOTTKY BIPOLAR 8212
|
||
OUTPUT
|
||
BUFFER
|
||
-INTERNAL SRFLIP-FLOPCLR(OS1-0S2)STB-SRtNT
|
||
0 0 0, ,
|
||
0,0,0 ,1'- 00 ,1 0 10 ,0 01,
|
||
1,~I,0~D18-------~ .....~017-------+-1-1DATALATCH
|
||
ff§>DIS------- ..............
|
||
IE>CLR-----001 ~~_ .......--'
|
||
(ACTIVE LOW)~MO----to4' __~
|
||
[jj>STB-- ............
|
||
[[>012--------+- .....DEVICESELECTION
|
||
-~[I>OS1
|
||
[g>OS2
|
||
C'i:R-RESETSDATALATCH
|
||
SETSSRFLlP·FLOP
|
||
(NOEFFECTONOUTPUT BUFFER)STBMD(DS,-DS2)DATAOUTEaUALS
|
||
~00 0 3-STATE ,0 0 3=STAte------
|
||
0,0 DATALATCH ,,0 DATALATCH
|
||
00,DATALATCH~01---,DATAIN
|
||
0-,-,DATAIN ,, ,DATAINSERVICE REQUEST FF
|
||
\ServiceRequestFlip-Flop
|
||
The(SR)flip-flopisusedtogenerate andcontrol
|
||
interrupts inmicrocomputer systems. Itisasyn
|
||
chronously setbytheCLRinput(activelow).When
|
||
the(SR)flip-flopis.setitisinthenon-interrupting
|
||
state.
|
||
Theoutputofthe(SR)flip-flop (Q)isconnected to
|
||
aninverting inputofa"NOR"gate.Theotherinput
|
||
tothe"NOR"gateisnon-inverting andisconnected
|
||
tothedeviceselection logic(081•082).Theoutput
|
||
ofthe"NOR"gate(INT)isactivelow(interrupting
|
||
state)forconnection toactivelowinputpriority
|
||
generating circuits.
|
||
STB(Strobe)
|
||
Thisinputisusedastheclock(C)tothedatalatch
|
||
fortheinputmodeMO=0)andtosynchronously
|
||
resettheservicerequestflip-flop(SR).
|
||
NotethattheSRflip-flop isnegativeedgetriggered.
|
||
5-102OutputBuffer
|
||
Theoutputsofthedatalatch(Q)areconnected to
|
||
3-state, non-inverting outputbuffers.Thesebuffers
|
||
haveacommon controlline(EN);thiscontrolline
|
||
eitherenablesthebuffertotransmit thedatafrom
|
||
theoutputsofthedatalatch(Q)ordisables the
|
||
buffer;forcingtheoutputintoahighimpedance
|
||
state.(3-state)
|
||
Thishigh-impedance stateallowsthedesigner to
|
||
connectthe8212directlyontothemicroprocessor
|
||
bi-directional databus.
|
||
ControlLogic
|
||
The8212hascontrolinputs051, 052, MOand
|
||
STB.Theseinputsareusedtocontroldeviceselec
|
||
tion,datalatching, outputbufferstateandservice
|
||
requestflip-flop.
|
||
MD(Mode)
|
||
Thisinputisusedtocontrolthe state oftheoutput
|
||
bufferandtodetermine thesourceoftheclockinput
|
||
(C)tothedatalatch.
|
||
WhenMOishigh(outputmode)theoutputbuffers
|
||
areenabledandthesourceofclock(C)tothedata
|
||
latchisfromthedeviceselection logic(051•OS2).
|
||
WhenMDislow(inputmode)theoutputbufferstate
|
||
isdet~rmined bythedeviceselection logic(OS1•
|
||
OS2)andthesourceofclock(C)tothedatalatchis
|
||
the.STB(Strobe)input.DS1,DS2(DeviceSelect)
|
||
These2inputsareusedfordeviceselection. When
|
||
OS1islowandOS2ishigh(OS1•OS2)thedeviceis
|
||
selected. Intheselected statetheoutputbufferis
|
||
enabled andtheservicerequestflip-flop (SR)is
|
||
asynchronously set.Functional Description
|
||
DataLatch
|
||
The8flip-flops thatmakeupthedatalatchareofa
|
||
"0"typedesign.Theoutput(Q)oftheflip-flopwill
|
||
follow th~datainput(0)whiletheclockinput(C)is
|
||
high.Latching willoccurwhentheclock(C)returns
|
||
low.
|
||
Thedatalatchisclearedbyanasynchronous reset
|
||
input(CLR).(Note:Clock(C)Overides Reset(CLR).)
|
||
|
||
===PAGE 171===
|
||
SCHOTTKY BIPOLAR 8212
|
||
8080StatusLatch
|
||
8008System
|
||
8080System:
|
||
8InputPorts
|
||
8OutputPorts
|
||
8LevelPriorityInterruptApplications OfThe8212--ForMicrocomputer Systems
|
||
IBasicSchematic Symbol VII
|
||
IIGatedBuffer VIII
|
||
IIIBi-Directional BusDriver IX
|
||
IVInterrupting InputPort
|
||
VInterrupt Instruction Port
|
||
VIOutputPort
|
||
I.BasicSchematic Symbols
|
||
Twoexamples ofwaystodrawthe8212onsystem asasystembus(buscontaining 8parallellines).
|
||
schematics-(1) thetopbeingthedetailed viewTheoutputtothedatabusissymbolic inreferenc
|
||
showing pinnumbers, and(2)thebottombeingtheing8parallellines.
|
||
symbolic viewshowing thesysteminputoroutput
|
||
BASICSCHEMATIC SYMBOLS
|
||
INPUTDEVICE OUTPUT DEVICE
|
||
SYSTEM
|
||
OUTPUT8212
|
||
INTCLR4
|
||
6
|
||
8
|
||
10
|
||
8212 15
|
||
17
|
||
19---INTCLR21
|
||
/MD'"14
|
||
DS2I~
|
||
132 1
|
||
Vee_---....- OUTPUT
|
||
FLAG11~-~
|
||
301STBDO
|
||
5
|
||
7
|
||
9
|
||
16
|
||
18
|
||
20
|
||
22
|
||
23
|
||
DATABUS(SYMBOLIC)(DETAILED)
|
||
DATABUS82128212
|
||
CLRINT
|
||
GND3
|
||
501
|
||
7
|
||
9
|
||
16
|
||
18
|
||
20
|
||
SYSTEM
|
||
INPUTINPUT
|
||
STROBE
|
||
8TB
|
||
"""'------C)I CLROUTPUT
|
||
DATA
|
||
(15mA)
|
||
(3.65VMIN)GATEDBUFFER
|
||
3-STATE
|
||
INPUT
|
||
DATA 8212
|
||
(250~A)Vee-------..----
|
||
GATING {
|
||
CONTROL
|
||
(081-082) ---......--------'II.GatedBuffer(3·STATE)
|
||
Thesimplest useofthe8212isthatofagated
|
||
buffer.Bytyingthemodesignallowandthestrobe
|
||
inputhigh,thedatalatchisactingasastraight
|
||
throughgate.Theoutputbuffersarethenenabled
|
||
fromthedeviceselection logic051and052.
|
||
Whenthedeviceselection logicisfalse,theoutputs
|
||
are3-state.
|
||
Whenthedeviceselection logicistrue,theinput
|
||
datafromthesystemisdirectlytransferred tothe
|
||
output.Theinputdataloadis250microamps.The
|
||
outputdatacansink15milliamps.Theminimum
|
||
highoutputis3.65volts.
|
||
5-103
|
||
|
||
===PAGE 172===
|
||
SCHOTTKY BIPOLAR 8212
|
||
BI-DIRECTIONAL BUSDRIVER III.Bi-Directional BusDriver
|
||
Apairof8212'swired(back-to-back) canbeused
|
||
asasymmetrical drive,bi-directional busdriver.
|
||
Thedevicesarecontrolled bythedatabusinput
|
||
controlwhichisconnected toD81onthefirst8212
|
||
andtoD82onthesecond.Onedeviceisactive,and
|
||
actingasastraightthroughbuffertheotherisin
|
||
3-statemode.Thisisaveryusefulcircuitinsmall
|
||
systemdesign.DATA---~
|
||
BUS
|
||
DATABUS
|
||
CONTROL
|
||
(o=L-R)
|
||
(I=R-L)STB
|
||
8212
|
||
GND1----'---......... OATA
|
||
BUS
|
||
STB
|
||
8212
|
||
GND
|
||
TOPRIORITY CKT_-...- (ACTIVE LOW)
|
||
OR.
|
||
TOCPU
|
||
INTERRUPT INPUTDATA
|
||
BUS
|
||
STBINTERRUPTING INPUTPORT
|
||
INPUT
|
||
STROBE
|
||
SYSTEM
|
||
INPUT
|
||
SYSTEM
|
||
RESET
|
||
PORT {
|
||
SELECTION
|
||
(DS1.DS2) --------'IV.Interrupting InputPort
|
||
Thisuseofan8212isthatofasysteminputport
|
||
thatacceptsastrobefromthesysteminputsource,
|
||
whichinturnclearstheservicerequestflip-flop
|
||
andinterrupts theprocessor. Theprocessor then
|
||
goesthroughaserviceroutine,identifies theport,
|
||
andcausesthedeviceselection logictogotrue
|
||
enabling thesysteminputdataontothedatabus.
|
||
V.Interrupt Instruction Port
|
||
The8212canbeusedtogatetheinterrupt instruc
|
||
tion,normally RESTART instructions, ontothedata
|
||
bus.Thedeviceisenabled fromtheinterrupt
|
||
acknowledge signalfromthemicroprocessor and
|
||
fromaportselection signal.Thissignalisnormally
|
||
tiedtoground.(081couldbeusedtomultiplex a
|
||
varietyofinterrupt instruction portsontoacom
|
||
monbus).INTERRUPT INSTRUCTION PORT
|
||
DATA
|
||
BUS
|
||
STB
|
||
RESTART
|
||
INSTRUCTION
|
||
(RST0-RST7)
|
||
(DSI)PORTSELECTION -........~
|
||
INTERRUPT ACKNOWLEDGE -...--_ ..........
|
||
5-104
|
||
|
||
===PAGE 173===
|
||
SCHOTTKY BIPOLAR 8212
|
||
VI.OutputPort(WithHand-Shaking)
|
||
The8212canbeusedtotransmit datafromthedata
|
||
bustoasystemoutput.Theoutputstrobecouldbe
|
||
ahand-shaking signalsuchas"reception ofdata"
|
||
fromthedevicethatthesystemisoutputting to.It
|
||
inturn,caninterrupt thesystemsignifying there
|
||
ceptionofdata.Theselection oftheportcomes
|
||
fromthedeviceselection logic.(OS1·OS2)
|
||
SYSTEM
|
||
INTERRUPTOUTPUT PORT(WITHHAND-SHAKING)
|
||
DATA
|
||
BUS
|
||
r----~- OUTPUT STROBE
|
||
STB
|
||
8212 SYSTEM OUTPUT
|
||
INTCLR11.>----...-- SYSTEM RESET
|
||
}PORTSELECTION
|
||
(LATCH CONTROL)
|
||
L..-- ..._- (OS1.0S2)
|
||
VII.8080StatusLatch
|
||
Herethe8212isusedasthestatuslatchforan8080
|
||
microcomputer system.Theinputtothe8212latch
|
||
isdirectlyfromthe8080databus.Timingshows
|
||
thatwhentheSYNCsignalistrue,whichiscon
|
||
nectedtotheOS2inputandthephase1signalis
|
||
true,whichisaTTLlevelcomingfromtheclock
|
||
generator; then,thestatusdatawillbelatchedinto
|
||
the8212.Note:Themodesignalistiedhighsothattheoutput
|
||
onthelatchisactiveandenabled allthetime.
|
||
Itisshownthatthetwoareasofconcern arethe
|
||
bidirectional databusofthemicroprocessor andthe
|
||
controlbus.
|
||
8080STATUS LATCH
|
||
OATABUS
|
||
INTA
|
||
WOT1 T2
|
||
STACK
|
||
HLTA </>1
|
||
OUT
|
||
M1BASIC</>2
|
||
INPCONTROL
|
||
MEMRBUS
|
||
SYNC
|
||
OATA
|
||
OBIN
|
||
STATUSDO10
|
||
90,
|
||
8
|
||
°27
|
||
°33
|
||
8080°44
|
||
Os5
|
||
°66
|
||
°7
|
||
SYNC19
|
||
OBIN17-
|
||
</>1 </>2STATUS
|
||
22 15LATCH
|
||
30, °04"'"'--- I---
|
||
5 6~) 7I----4 L-9~16J..L
|
||
18 8212 17
|
||
20~
|
||
19-- 22~
|
||
21CLOCKGEN.(</>1TTL) I---
|
||
&DRIVERI""--r<:CLR
|
||
14OS2MOOS,
|
||
·131211
|
||
I I
|
||
I12Vf\
|
||
ovJ\..
|
||
5-105
|
||
|
||
===PAGE 174===
|
||
SCHOTTKY BIPOLAR 8212
|
||
VIII.8008System
|
||
Thisshowsthe8212usedinan8008microcomputer
|
||
system.Theyareusedtomultiplex thedatafrom
|
||
threedifferentsourcesontothe8008inputdatabus.
|
||
Thethreesourcesofdataare:memorydata,input
|
||
data,andtheinterrupt instruction. The8212isalso
|
||
usedastheuni-directional busdrivertoprovidea
|
||
properdrivetotheaddresslatches(bothloworder
|
||
andhighorderarealso8212's)andtoprovideade
|
||
quatedrivetotheoutputdatabus.Thecontrolof
|
||
thesesix8212'sinthe8008systemisprovided by
|
||
thecontrollogicandclockgenerator circuits.These
|
||
circuitsconsistofflip-flops, decoders, andgatesto
|
||
generate thecontrolfunctions necessary for8008
|
||
microcomputer systems. Alsonotethattheinput
|
||
dataporthasastrobeinput.Thisallowstheproces-sortobeinterrupted fromtheinputportdirectly.
|
||
Thecontroloftheinputbusconsistsofthedatabus
|
||
inputsignal,controllogic,andtheappropriate
|
||
statussignalforbusdiscipline whether memory
|
||
read,input,orinterrupt acknowledge. Thecombina-
|
||
tionofthesefoursignalsdetermines whichoneof
|
||
thesethreedeviceswillhaveaccesstotheinput
|
||
databus.Thebusdriver,whichisimplemented in
|
||
an8212,isalsocontrolled bythecontrollogicand
|
||
clockgenerator soitcanbe3-stated whenneces
|
||
saryandalsoasacontroltransmission deviceto
|
||
theaddresslatches.Note:Theaddresslatchescan
|
||
be3-stated forDMApurposes andtheyprovide15
|
||
miHiampsdrive,sufficient forlargebussystems.
|
||
8008SYSTEM
|
||
INPUT
|
||
DATA
|
||
BUSBUS
|
||
DRIVERADDRESS
|
||
LATCHES
|
||
HIGHORDER
|
||
(6BITS)LOWORDER
|
||
(8BITS)
|
||
------vee
|
||
I•••••• DATABUSOUT
|
||
(04,5,6,7)tlSYNC
|
||
INT
|
||
READY~
|
||
¢2 I00-07
|
||
¢1
|
||
L-..----......----0111 MEMREAD
|
||
"""--'----------4----rJIII INPUT
|
||
---------4-----oIIIINT ACKI
|
||
-----......-----tlDATA BUSINb---------. ..WR
|
||
'-f--I------------.q,NT REO.I ..OUT
|
||
WAITREQ.------l.MI I'- J
|
||
CONTROL LOGIC
|
||
&CLOCKGEN.8212INPUT
|
||
DATAINPUT
|
||
STROBEMEMORY
|
||
DATA
|
||
INTERRUPT
|
||
INSTRUCTION
|
||
5-106
|
||
|
||
===PAGE 175===
|
||
SCHOTTKY BIPOLAR 8212.
|
||
IX.8080System
|
||
Thisdrawingshowsthe8212usedintheI/Osection
|
||
ofan8080microcomputer system.Thesystemcon
|
||
sistsof8inputports,8outputports,8levelpriority
|
||
systems, andabidirectional busdriver.(Thedata
|
||
buswithinthesystemisdarkened foremphasis).
|
||
Basically, theoperation wouldbeasfollows:The8
|
||
ports,forexample, couldbeconnected to8key
|
||
boards,eachkeyboard havingitsownprioritylevel.
|
||
Thekeyboard couldprovideastrobeinputofits
|
||
ownwhichwouldcleartheservicerequestflip-flop.
|
||
TheINTsignalsareconnected toan8levelpriority
|
||
encoding circuit.Thiscircuitprovides apositive
|
||
trueleveltothecentralprocessor (lNT)alongwith
|
||
athree-bit codetotheinterrupt instruction portfor
|
||
thegeneration ofRESTART instructions. Oncethe
|
||
processor hasbeeninterrupted anditacknowledges
|
||
thereception oftheinterrupt, theInterrupt Acknowl
|
||
edgesignalisgenerated. Thissignaltransfers data
|
||
intheformofaRESTART instruction ontothebuf
|
||
fereddatabus.WhentheDBINsignalistruethis
|
||
RESTART instruction isgatedintothemicrocom
|
||
puter,inthiscase,the8080CPU.The8080thenper
|
||
formsasoftware controlled interrupt serviceroutine,
|
||
savingthestatusofitscurrentoperation inthe
|
||
push-down stackandperforming anINPUTinstruc
|
||
tion.TheINPUTinstruction thussetstheINPstatusbit,whichiscommon toallinputports.
|
||
Alsopresentistheaddress ofthedeviceonthe
|
||
8080addressbuswhichinthissystemisconnected
|
||
toan8205,oneoutofeightdecoderwithactivelow
|
||
outputs.Theseactivelowoutputswillenableoneof
|
||
theinputports,theonethatinterrupted theproces
|
||
sor,toputitsdataontothebuffered databustobe
|
||
transmitted totheCPUwhenthedatabusinput
|
||
signalistrue.Theprocessor canalsooutputdata
|
||
fromthe8080databustothebuffered databus
|
||
whenthedatabusinputsignalisfalse.Usingthe
|
||
sameaddress selection technique fromthe8205
|
||
decoder andtheoutputstatusbit,wecanselect
|
||
withthissystemoneofeightoutputportstotrans
|
||
mitthedatatothesystem's outputdevicestructure.
|
||
Note:ThisbasicI/Oconfiguration forthe8080can
|
||
beexpanded to256inputdevicesand256output
|
||
devicesallusing8212and,ofcourse,theappropri
|
||
atedecoding.
|
||
Notethatthe8080isa3.3-voltminimum highinput
|
||
requirement andthatthe8212hasa3.65-volt mini
|
||
mumhighoutputproviding thedesigner witha350
|
||
millivoltnoisemarginworstcasefor8080systems
|
||
whenusingthe8212.
|
||
5-107
|
||
|
||
===PAGE 176===
|
||
SCHOTTKY BIPOLAR 8212
|
||
8080
|
||
ADDRESS .:...
|
||
BUS(SeeNote1)
|
||
AO-'
|
||
A1--+-
|
||
A2--+-8205
|
||
~~E1::=:-
|
||
~--0E2 ::-
|
||
Vee-..E_3__..
|
||
I/ODEVICE
|
||
SELECTORST;~;T:¢ ST:212tt:7:::~~llllltnn~ 8212=>~:~~T
|
||
~;:N~~- :IIII[_~L~ee?
|
||
INP--......----t-t-t-t-t-+--+-t------------+-6
|
||
STATUS
|
||
BITS-STROBE 2---.STB
|
||
INPUT~
|
||
PORT2L-Y 8212 8212~OUTPUTWPORT2
|
||
~CLR
|
||
~OUTPUTWPORT3
|
||
~OUTPUTWPORT4
|
||
~OUTPUThi"PORT68212Ill::
|
||
ttm::zb ill\:,z:Zht~
|
||
y~f y
|
||
:111_~L:eeySTROBE 4--.STB
|
||
INPUT~
|
||
PORT4L.-,I 8212
|
||
:::::
|
||
ST;~;;~¢ ST:212~m:~~j!II!:w::7::~3 8212t>~~~~~T
|
||
~~~~~_. I!!!!-~~eI
|
||
ST;;;;T:¢ST:2~ ::::::::::::::::::::::~~ II::::::::::::::::::::? 8212
|
||
.......------<=.11 INTCLR~~ :~:~:~CLR
|
||
1G~DL-_ \l~\l-~ VeeII
|
||
PRIORITY
|
||
ENCODER &
|
||
INTERRUPT
|
||
GENERATING
|
||
LOGICCIRCUITS
|
||
(USERDESIGNED)_OUT----t------r-t-t-t-t----ir+-t-----------+--+----1~:::::f_4
|
||
ST;;;;T::: ST:212m::ili::~Jtmm:~ 8212
|
||
_----L.-,I-<~J11INT CLR0-<1-Y[[~\!.:CLR
|
||
.1G~DL-_ :::[:[,_-.J VeeY
|
||
8212
|
||
INTERRUPT
|
||
INSTRUCTION
|
||
PORT(RST)BUFFERED
|
||
DATA
|
||
BUS
|
||
8212
|
||
+--.s>
|
||
GNDu
|
||
BI-DIRECTIONAL
|
||
BUSDRIVERINT--------004----------1
|
||
r--,
|
||
I I
|
||
I IIVeeI I
|
||
I I
|
||
I I
|
||
~I 0'1IO-++++----4~
|
||
~I 1 IO-++++-.-.....~
|
||
~I 21O-++++---oIt-- .....
|
||
~H 3IO-++++-.....-~
|
||
-~ 41O-++++---oIt---------<:::JIINT CLR~
|
||
---I 51O-++++---oIt--_=: ~ 1G~DL-~
|
||
................ I I
|
||
v~eI:i
|
||
GND I I
|
||
I IL__II_..I
|
||
INT-----..----t:
|
||
ACK8080--...J..
|
||
D:J:~!I. 8212
|
||
DalN-t?!NrJII
|
||
STROBE 7---+-STB
|
||
8212 8212~OUTPUTWPORT7
|
||
SYSTEM--.....
|
||
RESET
|
||
Note1.ThisbasicI/Oconfiguration forthe8080canbeexpanded to256inputdevicesand256outputdevicesallusing8212andtheappropriate decoding.
|
||
5-108
|
||
|
||
===PAGE 177===
|
||
SCHOTTKY BIPOLAR 8212
|
||
Absolute Maximum Ratings·
|
||
Temperature UnderBiasPlastic..-65°Cto+75°C
|
||
StorageTemperature -65°Cto+160°C
|
||
AllOutputorSupplyVoltages -0.5to+ 7Volts
|
||
,AllInputVoltages -1.0to5.5Volts
|
||
OutputCurrents 125mA
|
||
D.C.Characteristics
|
||
TA=O°Cto+75°C'Vee=+5V±5°k*COMMENT: Stresses abovethoselistedunder"Absolute Maximum Ratings"
|
||
maycausepermanent damage tothedevice.Thisisastressratingonlyand
|
||
functional operation ofthedeviceattheseoratanyothercondition above
|
||
thoseindicated intheoperational sections ofthisspecification isnotimplied.
|
||
Symbol ParameterLimitsUnit TestConditions
|
||
Min. Typ. Max.
|
||
IF InputLoadCurrent -.25 mAVF=.45V
|
||
ACK,052,CR,Oll-OlsInputs
|
||
IF InputLoadCurrent -.75 mAVF=.45V
|
||
MOInput
|
||
IF InputLoadCurrent -1.0 mAVF=.45V
|
||
OSIInput
|
||
IR InputLeakage Current 10}lAVR=5.25V
|
||
ACK,OS,CR,Oil-DisInputs
|
||
IR InputLeakage Current 30 JvtAVR=5.25V
|
||
MOInput
|
||
IR InputLeakage Current 40{tAVR=5.25V
|
||
OSIInput
|
||
VcInputForwardVoltageClamp -1 VIe=-5mA
|
||
V1LInput"Low"Voltage .85 V
|
||
V1HInput"High"Voltage 2.0 V
|
||
VOL Output"Low"Voltage .45 Vlal=15mA
|
||
VOHOutput"High"Voltage 3.65 4.0 V 10H=-1mA
|
||
Ise ShortCircuitOutputCurrent -15 -75 mAVa=OV
|
||
1101OutputLeakage Current 20{tAVa=.45V/5.25V
|
||
HighImpedance State
|
||
lee PowerSupplyCurrent 90 130 mA
|
||
5-109
|
||
|
||
===PAGE 178===
|
||
SCHOTTKY BIPOLAR 8212
|
||
TypicalCharacteristics
|
||
INPUTCURRENT YS.INPUTYOLTAGE OUTPUT CURRENT VS.OUTPUT "LOW"YOLTAGE
|
||
.8 .6 .4 .2O'---~~'-----'-----.L..------'o«E
|
||
I-60zwa:a:
|
||
:::Ju
|
||
I-40:;)a.....
|
||
:;)
|
||
0
|
||
20100....----.,...----.,...----~--____.
|
||
Vee=+5.0V
|
||
801-----1----1----+--------4
|
||
+3 +2 +1o -1 -2r~Vee=+5.0V
|
||
~~(;"
|
||
I
|
||
TA=o°c""'"'//TA=25°C
|
||
V:/TA=75°C
|
||
V
|
||
-300-3-250o
|
||
-50
|
||
«-100
|
||
..=:
|
||
....zw
|
||
~-150
|
||
:::Ju
|
||
I-
|
||
:::Ja.
|
||
~-200
|
||
INPUTVOLTAGE (vt OUTPUT "LOW"VOLTAGE (V)
|
||
300 250 200 150 100DATATOOUTPUT DELAY
|
||
YS.LOADCAPACITANCE
|
||
50I
|
||
Vee=-+5.0V
|
||
TA=25°C
|
||
.,.,-0iI'
|
||
.,.,---.,.,-
|
||
\++.,.,-""-~.,.,-~ .-.,.,-~ .,.,-""--.,.,-""-~~-'~......-50
|
||
40
|
||
E.
|
||
>et
|
||
~w300
|
||
I-
|
||
:::J
|
||
CLI-
|
||
:::J
|
||
0
|
||
020
|
||
I-
|
||
etI-et
|
||
0
|
||
10
|
||
5.0 4.0 3.0 2.0TA=75"C
|
||
1.0OUTPUT CURRENT YS.
|
||
OUTPUT "HIGH"YOLTAGE
|
||
TA=25"C
|
||
1----+------.,~~-4---= TA=O"'C«-10
|
||
!
|
||
I-z-15wa:a:
|
||
:::Ju-20I-
|
||
:::>
|
||
CLI-
|
||
:::J
|
||
0-25
|
||
-30
|
||
-35O.-5I-----+----+----+------#~----IO---.......---------------.--~-
|
||
Vee=+5.0V
|
||
OUTPUT "HIGH"VOLTAGE (V) LOADCAPACITANCE (pF)
|
||
DATATOOUTPUT DELAY
|
||
YS.TEMPERATUREWRITEENABLE TOOUTPUT DELAY
|
||
YS.TEMPERATURE
|
||
T
|
||
Vee=+5.0V
|
||
//
|
||
~
|
||
1..0'/
|
||
\.';,'c""
|
||
",,"
|
||
~" t---~1
|
||
vee=+5.0V
|
||
II
|
||
\.'c~
|
||
""filii'
|
||
--~,,-""- -\'-\.'-,----~----____f'"
|
||
5TB<.,.,-t+_
|
||
052~...-----------
|
||
05,<::t-_~~ ............
|
||
--3522
|
||
20
|
||
III.:
|
||
>18«
|
||
~w
|
||
0
|
||
I-
|
||
:::J16 CLI-
|
||
:::J
|
||
0
|
||
0I-
|
||
et14
|
||
I-et
|
||
0
|
||
12
|
||
10
|
||
-25 o 25 50 75 10040
|
||
E.
|
||
>et
|
||
~wc30
|
||
I-
|
||
:::J
|
||
CLI-
|
||
:::Jo25oI-
|
||
W
|
||
~co
|
||
~20
|
||
w
|
||
wI-
|
||
~
|
||
~15
|
||
10
|
||
-25 o 25 50 75 100
|
||
TEMPERATURE (OC) TEMPERATURE rc)
|
||
5-110
|
||
|
||
===PAGE 179===
|
||
SCHOTTKY BIPOLAR 8212
|
||
TimingDiagram
|
||
DATA 1.5Vy----------y.5V
|
||
_____ -J. I;==t
|
||
pw~I_tH:.j'----
|
||
STBoroSl•oS2 1.5vl ''-1._5V _
|
||
~twE=J
|
||
OUTPUT -/'10-:-------
|
||
oSl.OS2 1.5Vj \1.5V
|
||
________ l_tE_~r_~E~~~W_) __~-t-D-~---- YVOH
|
||
OUTPUTX ~----,~t- VOL
|
||
~tpw~ fI I .5V
|
||
eLR 1.5V\. 11.5V
|
||
~~~~~~~~~~~~1r-----
|
||
DO ><"-:._5V_
|
||
DATA 1.SVX----------------'i1.5V_____ J. _'I~ _
|
||
_______ --+-_--_--_- _tS_E_T_--__'-_"r- tH-j
|
||
STBorOS,•DS2 1.5V
|
||
'OUTPUT
|
||
STB~tPD-jJ{SV-- - - - - - - - --
|
||
_______ .J
|
||
-----,I \~1.5V _
|
||
!--tpw
|
||
1.5V
|
||
NOTE:ALTERNATIVE TESTLOAD~tPw-~ts
|
||
I
|
||
Vcc
|
||
10K
|
||
OUT0---....----.
|
||
CL ·lK
|
||
5-111
|
||
|
||
===PAGE 180===
|
||
SCHOTTKY BIPOLAR 8212
|
||
A.C.Characteristics
|
||
TA=O°Cto+75°C Vee=+5V±5%
|
||
Symbol ParameterLimitsUnit TestConditions
|
||
Min. Typ. Max.
|
||
tpw PulseWidth 30 ns
|
||
tpd DataToOutputDelay 30 ns
|
||
twe WriteEnableToOutputDelay 40 ns
|
||
tset DataSetu·pTime 15 ns
|
||
th DataHoldTime 20 ns
|
||
tr ResetToOutputDelay 40 ns
|
||
ts SetToOutputDelay 30 ns
|
||
te OutputEnable/Disable Time 45 ns
|
||
tc ClearToOutputDelay 55 ns
|
||
CAPACITANCE *F=1MHzVsrAs=2.5VVee=+5VTA=25°C
|
||
Symbol TestLIMITS
|
||
Typ. Max.
|
||
CIN DSIMDInputCapacitance 9pF12pF
|
||
CIN DS2,CK,ACK,Oil-Dis 5pF9pF
|
||
InputCapacitance
|
||
COUT DOl-DOs OutputCapacitance 8pF12pF
|
||
*Thisparameter issampled andnot100%tested.
|
||
Switching Characteristics
|
||
CONDITIONS OFTEST
|
||
InputPulseAmplitude =2.5V
|
||
InputRiseandFallTimes5ns
|
||
Between 1Vand2VMeasurements madeat1.5V
|
||
with15rnA&30pFTestLoadTESTLOAD
|
||
15mA&30pF
|
||
TO
|
||
D.U.T.300
|
||
600
|
||
5-112*INCLUDING JIG&PROBECAPACITANCE
|
||
|
||
===PAGE 181===
|
||
SiliconGateMOS8255
|
||
PROGRAMMABLE PERIPHERAL INTERFACE
|
||
•24Programmable I/OPins
|
||
•Completely TTLCompatible
|
||
•FullyComp.atible withMCS™-8and
|
||
MCSTM'_80Microprocessor Families•DirectBitSet/Reset Capability
|
||
EasingControlApplication Interface
|
||
•40PinDualIn-LinePackage
|
||
•Reduces SystemPackage Count
|
||
The8255isageneralpurpose programmable I/Odevicedesigned forusewithboththe8008and8080
|
||
microprocessors. Ithas24I/Opinswhichmaybeindividually programmed intwogroupsoftwelveand
|
||
usedinthreemajormodesofoperation. Inthefirstmode(Mode0),eachgroupoftwelveI/Opinsmaybe
|
||
programmed insetsof4tobeinputoroutput.InMode1,thesecondmode,eachgroupmaybeprogrammed
|
||
tohave8linesofinputoroutput.Oftheremaining fourpinsthreeareusedforhandshaking andinterrupt
|
||
controlsignals.Thethirdmodeofoperation (Mode2)isaBidirectional Busmodewhichuses8linesfora
|
||
bidirectional bus,andfivelines,borrowing onefromtheothergroup,forhandshaking.
|
||
Otherfeaturesofthe8255includebitsetandresetcapability andtheabilitytosource1mAofcurrentat
|
||
1.5volts.Thisallowsdarlington transistors tobedirectlydrivenforapplications suchasprintersandhigh
|
||
voltagedisplays.
|
||
PINCONFIGURATION 8255BLOCKDIAGRAM
|
||
./'--""_ ,1/0
|
||
1'\......--.- /PBrPBoI/~-~ 1'0
|
||
1'\......--.- ..../PC3·PCO1'0
|
||
1'\.....-----./ PCrPC4S~~~lEI~S1-- +SV--GND 1'0
|
||
1'\.,....---./ PA7·PAO
|
||
Ao---I
|
||
cs------'iffi 0
|
||
WR---0 :~~~~
|
||
A, IC~~~~~L
|
||
RESET---IBI·DIRECTIONAl DATABUS
|
||
PINNAMESPA31
|
||
PA22 39PA5
|
||
PAl3 38PA6
|
||
PAO4 37PA7
|
||
AD5 36WR
|
||
csG 35RESET
|
||
GNO 7 34DO
|
||
Al8 3301
|
||
AO9 32O2
|
||
PC710 3103
|
||
PCG1182553004
|
||
PC512 29Os
|
||
PC413 2806
|
||
PCO14 27~
|
||
PCl15 26VCC
|
||
PC216 25PB7
|
||
PC317 24PB6
|
||
PBO18 23PB5
|
||
PB119 22PB4
|
||
PB220 21PB3
|
||
07-00 DATABUS(BI-DIRECTIONAL)
|
||
RESET RESETINPUT
|
||
CS CHIPSELECT
|
||
RD READINPUT
|
||
WR WRITEINPUT
|
||
AO,A1 PORTADDRESS
|
||
PA7·PAO. PORTA(BIT)
|
||
PB7·PBO PORTB(BIT)
|
||
PC7·PCO PORTC(BIT)
|
||
VCC +5VOLTS
|
||
GND gVOLTS
|
||
5-113
|
||
|
||
===PAGE 182===
|
||
SILICON GATEMOS8255
|
||
8255BASICFUNCTIONAL DESCRIPTION
|
||
General
|
||
The8255isaProgrammable Peripheral Interface (PPI)de
|
||
vicedesigned forusein8080Microcomputer Systems. Its
|
||
function isthatofageneralpurpose I/Ocomponent tointer
|
||
faceperipheral equipment tothe8080systembus.The
|
||
functional configuration ofthe8255isprogrammed bythe
|
||
systemsoftware sothatnormally noexternal logicisnec
|
||
essarytointerface peripheral devicesorstructures.
|
||
DataBusBuffer
|
||
This3-state, bi-directional, eightbitbufferisusedtointer
|
||
facethe8255tothe8080systemdatabus.Dataistrans
|
||
mittedorreceived bythebufferuponexecution ofINput
|
||
orOUTput instructions bythe8080cPU.Control Words
|
||
andStatusinformation arealsotransferred through theData
|
||
Busbuffer.
|
||
Read/Write andControlLogic
|
||
Thefunction ofthisblockistomanagealloftheinternal
|
||
andexternal transfers ofbothDataandControl orStatus
|
||
words.Itaccepts inputsfromthe8080CPUAddress and
|
||
Control bussesandinturn,issuescommands tobothofthe
|
||
ControlGroups.
|
||
ChipSelect:A"low"onthisinputpinenablesthecom
|
||
munication between the8255andthe8080CPU.(RD)
|
||
Read:AII10w"onthisinputpinenablesthe8255tosend
|
||
theDataorStatusinformation tothe8080CPUonthe
|
||
DataBus.Inessence, itallowsthe8080CPUtoIIreadfrom"
|
||
the8255.
|
||
(WR)
|
||
Write:A"low"onthisinputpinenablesthe8080CPUto
|
||
writeDataorControlwordsintothe8255.
|
||
(AOandA1)
|
||
PortSelect0andPortSelect1:Theseinputsignals,incon
|
||
junction withtheRDandWRinputs,controltheselection of
|
||
oneofthethreeportsortheControl WordRegister. They
|
||
arenormally connected totheleastsignificant bitsofthe
|
||
Address Bus(AoandA1).
|
||
8255BASICOPERATION
|
||
A1AORDWRCSINPUTOPERATION (READ)
|
||
00010PORTA~DATABUS
|
||
01010PORTB=>DATABUS
|
||
10 0 10PORTC=>DATABUS
|
||
OUTPUT OPERATION
|
||
(WRITE)
|
||
00100DATABUS=>PORTA
|
||
01 1 0 0 DATABUS=>PORTB
|
||
1010 0 DATA BUS~PORTC
|
||
1 1 100DATABUS=>CONTROL
|
||
DISABLE FUNCTION
|
||
X X X X1DATABUS=>3-STATE
|
||
11010ILLEGAL CONDITION
|
||
8255BlockDiagram
|
||
5-114
|
||
|
||
===PAGE 183===
|
||
SILICON GATEMOS8255
|
||
(RESET)
|
||
Reset:A"high"onthisinputclearsallinternalregisters in
|
||
cludingtheControl Register andallports(A,B,C)areset
|
||
totheinputmode.
|
||
GroupAandGroupBControls
|
||
Thefunctional configuration ofeachportisprogrammed
|
||
bythesystems software. Inessence, the8080CPU"out
|
||
puts"acontrolwordtothe8255.Thecontrolwordcon
|
||
tainsinformation suchas"mode", "bitset","bitreset"
|
||
etc.thatinitializes thefunctional configuration ofthe8255.
|
||
EachoftheControlblocks(GroupAandGroupB)accepts
|
||
"commands" fromtheRead/Write. Control Logic,receives
|
||
"control words"fromtheinternaldatabusandissuesthe
|
||
propercommands toitsassociated ports.
|
||
ControlGroupA -PortAandPortCupper(C7-C4)
|
||
ControlGroupB -PortBandPortClower(C3-CO)
|
||
TheControl WordRegister canOnlybewritteninto.No
|
||
Readoperation oftheControl WordRegister isallowed.
|
||
8255BLOCKDIAGRAMPortsA,B,andC
|
||
The8255contains three8-bitports(A,S,andC).Allcan
|
||
beconfigured inawidevarietyoffunctional characteristics
|
||
bythesystemsoftware buteachhasitsownspecialfeatures
|
||
or"personality" tofurtherenhance thepowerandflexi
|
||
bilityofthe8255.
|
||
PortA:One8-bitdataoutputlatch/buffer andone8-bit
|
||
datainputlatch.
|
||
PortB:One8-bitdatainput/output latch/buffer andone
|
||
8-bitdatainputbuffer.
|
||
PortC:One8-bitdataoutputlatch/buffer andone8-bit
|
||
datainputbuffer(nolatchforinput).Thisportcanbedi
|
||
videdintotwo4-bitportsunderthemodecontrol. Each4
|
||
bitportcontains a4-bitlatchanditcanbeusedforthe
|
||
controlsignaloutputs andstatussignalinputsinconjunc
|
||
tionwithPortsAandB.
|
||
PINCONFIGURATION
|
||
5-115PA3 1 PA4
|
||
PA2 2 39PA5
|
||
PAl3 38PA6
|
||
PAO4 37PA7
|
||
AD5 36WR
|
||
cs6 35RESET
|
||
GNO 7 34DO
|
||
A18 330,
|
||
AO9 32O2
|
||
PC710 3103
|
||
PC61182553004
|
||
PC512Os
|
||
PC413 06
|
||
PCO140,
|
||
PC115 26VCC
|
||
PC216 P87
|
||
PC3 17 24P86
|
||
P8018 23P85
|
||
P8119 22P84
|
||
P8220 21P83
|
||
PINNAMES
|
||
07-00 DATABUS(BI-DIRECTIONAL)
|
||
RESET RESETINPUT
|
||
CS CHIPSELECT
|
||
RD READINPUT
|
||
WR WRITEINPUT
|
||
AO,A1 PORTADDRESS
|
||
PA7·PAO PORTA(BIT)
|
||
PB7·PBO PORTB(BIT)
|
||
PC7·PCO PORTC(SfT) j
|
||
VCC +5VOL1S 1
|
||
GND "VOLTS
|
||
|
||
===PAGE 184===
|
||
SILICON GATEMOS8255
|
||
8255DETAILED OPERATIONAL DESCRIPTION
|
||
ModeSelection
|
||
Therearethreebasicmodesofoperation thatcanbeselect
|
||
edbythesystemsoftware:
|
||
Mode0 -BasicInput/Output
|
||
Mode1 -Strobed Input/Output
|
||
Mode2 -Bi-Directional Bus
|
||
WhentheRESETinputgoes"high"allportswillbesetto
|
||
theInputmode(Le.,all24lineswillbeinthehighim
|
||
pedance state).AftertheRESET isremoved the8255can
|
||
remainintheInputmodewithnoadditional initialization
|
||
required. Duringtheexecution ofthesystemprogram any
|
||
oftheothermodesmaybeselected usingasingleOUTput
|
||
instruction. Thisallowsasingle8255toserviceavarietyof
|
||
peripheral deviceswithasimplesoftware maintenance rou
|
||
tine.
|
||
ThemodesforPortAandPortBcanbeseparately defined,
|
||
whilePortCisdividedintotwoportions asrequired bythe
|
||
PortAandPortBdefinitions. Alloftheoutputregisters, in
|
||
cludingthestatusflip-flops, willberesetwhenever the
|
||
modeischanged. Modesmaybecombined sothattheir
|
||
functional definition canbe"tailored" toalmostanyI/O
|
||
structure. Forinstance; GroupBcanbeprogrammed in
|
||
Mode0tomonitor simpleswitchclosingsordisplaycompu
|
||
tational results,GroupAcouldbeprogrammed inMode1
|
||
tomonitor akeyboard ortapereaderonaninterrupt-driven
|
||
basis.CONTROL WORD
|
||
~ GROUPB'"
|
||
PORTC(LOWER)~ 1=INPUT
|
||
0=OUTPUT
|
||
PORTB
|
||
1=INPUT
|
||
0=OUTPUT
|
||
MODESELECTION
|
||
0=MODE0
|
||
1=MODE1
|
||
;I' GROUPA'"
|
||
PORTC(UPPER)
|
||
1=INPUT
|
||
0=OUTPUT
|
||
PORTA
|
||
1=INPUT
|
||
0=OUTPUT
|
||
MODESELECTION
|
||
00=MODE0
|
||
01=MODE1
|
||
1X=MODE2
|
||
MODESETFLAG
|
||
1=ACTIVE
|
||
BasicModeDefinitions andBusInterfaceC
|
||
MODE1--....rL.~~8~B -1/-o..J;itllfTm=;;;;:;;:::;:t:=::::;:::;:;:::;;J.i-~~:~I.J/O
|
||
Pa,.PBoCONTROL CONTROL PA7·pAo
|
||
ORI/O ORI/O
|
||
SingleBitSet/Reset Feature
|
||
AnyoftheeightbitsofPortCcanbeSetorResetusinga
|
||
singleOUTput instruction. Thisfeaturereduces software
|
||
requirements inControl-based applications.ModeDefinition Format
|
||
TheModedefinitions andpossible Modecombinations may
|
||
seemconfusing atfirstbutafteracursory reviewofthe
|
||
complete deviceoperation asimple,logicalI/Oapproach
|
||
willsurface.Thedesignofthe8255hastakenintoaccount
|
||
thingssuchasefficient PCboardlayout,controlsignaldefi
|
||
nitionvsPClayoutandcomplete functional flexibility to
|
||
supportalmostanyperipheral devicewithnoexternal logic.
|
||
Suchdesignrepresents themaximum useoftheavailable
|
||
pins.Ar
|
||
~I.DIRECTIONALMODE2~"'----rrrnmi
|
||
I/O ICONtROL I
|
||
5-116
|
||
|
||
===PAGE 185===
|
||
SILICON GATEMOS8255
|
||
CONTROL WORD
|
||
r07t06I05104I031O2I0,IDOI
|
||
IIILBITSET/RESET,x Xx, 1=SET
|
||
I0::RESET
|
||
DON'T
|
||
CARE
|
||
BITSELECT
|
||
o12 34 56 7
|
||
o1o1o1o1801
|
||
o01 1o01 1B,-l
|
||
o0o01 11 1B21
|
||
BITSET/RESET FLAG
|
||
OmACTIVEWhenPortCisbeingusedasstatus/control forPortAorB,
|
||
thesebitscanbesetorresetbyusingtheBitSet/Reset op
|
||
erationjustasiftheyweredataoutputports.
|
||
Interrupt ControlFunctions
|
||
When'the-'8255isprogrammed tooperate inMode1or
|
||
Mode2,controlsignalsareprovided thatcanbeusedas
|
||
interrupt requestinputstotheCPU.Theinterrupt request
|
||
signals,generated fromPortC,canbeinhibited orenabled
|
||
bysettingorresetting theassociated INTEflip-flop, using
|
||
the'Bitset/reset function ofPortC.
|
||
Thisfunction allowstheProgrammer todisalloworallowa
|
||
.specific I/Odevicetointerrupt theCPUwithout effecting
|
||
anyotherdeviceintheinterrupt structure.
|
||
INTEflip-flop definition:
|
||
(BIT-SET) -INTEisSET-Interrupt enable
|
||
(BIT-RESET) -INTEisRESET-Interrupt disable
|
||
BitSet/Reset FormatNote:AllMaskflip-flops areautomatically resetduring
|
||
modeselection anddeviceReset.
|
||
Operating Modes
|
||
Mode0(BasicInput/Output)
|
||
Thisfunctional configuratioD provides simple .1nputand
|
||
Outputoperations foreach,ofthethreeports.No"hand
|
||
shaking" isrequired, dataissimplywrittentoorreadfrom
|
||
aspecified port.Mode0BasicFunctional Definitions:
|
||
•Two8-bitportsandtwo4-bitports.
|
||
•Anyportcanbeinputoroutput.
|
||
•Outputs arelatched.
|
||
•Inputsarenotlatched.
|
||
•16different Input/Output configurations arepossible
|
||
inthisMode.
|
||
---------tDELAYTIME
|
||
FROMINPUTDATAtDELAYTIME
|
||
FROMRDBASICINPUT
|
||
TIMING (07-00
|
||
FOLLOWS INPUT, INPUT
|
||
NOLATCHING)
|
||
BASICOUTPUT
|
||
TIMING (OUTPUTS
|
||
LATCHED)
|
||
OUTPUT
|
||
tDATA-.
|
||
SET·UP~SET·UPVIOLATION-------X X------------- ------
|
||
Mode0Timing
|
||
5-117
|
||
|
||
===PAGE 186===
|
||
SILICON GATEMOS8255
|
||
MODE0PORTDEFINITION CHART
|
||
A B GROUPA GROUPB
|
||
04PORTC PORTC0301DOPORTA(UPPER)#PORTB(LOWER)
|
||
000 0 OUTPUT OUTPUT 0OUTPUT OUTPUT
|
||
0 0 01OUTPUT OUTPUT 1OUTPUT INPUT
|
||
0 0 10OUTPUT OUTPUT 2INPUT OUTPUT
|
||
0011OUTPUT OUTPUT 3INPUT INPUT
|
||
0100OUTPUT INPUT 4OUTPUT OUTPUT
|
||
0101OUTPUT INPUT 5OUTPUT INPUT
|
||
0 1 10OUTPUT INPUT 6INPUT OUTPUT
|
||
0111OUTPUT INPUT 7INPUT INPUT
|
||
1000INPUT OUTPUT 8OUTPUT OUTPUT
|
||
1001INPUT OUTPUT 9OUTPUT INPUT
|
||
1010INPUT OUTPUT 10INPUT OUTPUT
|
||
101 1 INPUT OUTPUT 11INPUT INPUT
|
||
1100INPUT INPUT 12OUTPUT OUTPUT
|
||
1 1 01INPUT INPUT 13OUTPUT INPUT
|
||
1110INPUT INPUT 14INPUT OUTPUT
|
||
1111INPUT INPUT 15INPUT INPUT
|
||
MODE0CONFIGURATIONS
|
||
CONTROL WORD#0
|
||
~06050403O20,DO
|
||
A.18
|
||
8255
|
||
c{,4
|
||
I..
|
||
,4,
|
||
B.18,
|
||
CONTROL WORO#1
|
||
0706050403020,DOCONTROL WORD#2
|
||
D706050403020,00
|
||
A,8,
|
||
8255
|
||
,4
|
||
c{/4---,
|
||
B.18
|
||
I
|
||
CONTROL WORD#3
|
||
07060504D3O20,DO
|
||
A8PA7·pAo
|
||
8255
|
||
4PC,-PC4
|
||
°7-°0 c{ °7·°0
|
||
;,4PC3·PCO
|
||
8Ps.,.PBo B
|
||
5-118A.18-,
|
||
8255
|
||
,4-. .,c{,4
|
||
I
|
||
B ' 8I Ps.,.PBO
|
||
|
||
===PAGE 187===
|
||
SILICON GATEMOS8255
|
||
CONTROL WORD#4
|
||
A18,
|
||
8255
|
||
,4
|
||
c{,.•,4-,
|
||
B18
|
||
I
|
||
CONTROL WORD#5
|
||
0, 05P~.PBOCONTROL WORD#8
|
||
0706Os0403,020,DO
|
||
A.,8
|
||
I
|
||
8255
|
||
,4
|
||
c{,..
|
||
,4-,
|
||
B18-,
|
||
CONTROL WORD#9
|
||
0706050403O20,DO
|
||
A,8-,
|
||
8255
|
||
,4
|
||
c{-,.•,4,
|
||
B,8
|
||
I
|
||
CONTROL WORD#6
|
||
0706050403
|
||
A,8-,
|
||
8255
|
||
14
|
||
c{,4,
|
||
B ' 8-,
|
||
CONTROL WORD#7
|
||
0706050403PA7-PAo A.I,8PA7·pAo
|
||
8255
|
||
pc'-PC4,4PC7·PC4c{-,
|
||
07-00
|
||
PC3-PCO,4PC3-PCO -,
|
||
P~-PBO B,8
|
||
P~.PBOI
|
||
CONTROL WORD#10
|
||
0706060403O20,DO
|
||
A,8,
|
||
8255
|
||
14
|
||
c{
|
||
14,
|
||
B,8-,
|
||
CONTROL WORD#11
|
||
070605
|
||
A8 8PA7·pAo A PA7·pAo
|
||
8255 8255
|
||
4PC7·PC44
|
||
c{ c{PC7·PC4
|
||
07-0007.00
|
||
4PC3·PCO4PC3-PCO
|
||
B8
|
||
P~.PBo8B PS,-PBo
|
||
5-119
|
||
|
||
===PAGE 188===
|
||
SILICON GATEMOS8255
|
||
CONTROL WORD#12
|
||
0706050403O201
|
||
A,8
|
||
F
|
||
8255
|
||
c{·,4
|
||
/
|
||
•.
|
||
,4,
|
||
B,8
|
||
I~
|
||
CONTROL WORD#13
|
||
0706050403O20,DOCONTROL WORD#14
|
||
0706050403O20,DO
|
||
A.,8
|
||
I
|
||
8255
|
||
c{.,4
|
||
I.•,4
|
||
B.,8
|
||
I
|
||
CONTROL WORD#15
|
||
0706050403O20,DO
|
||
A,8
|
||
7
|
||
8255
|
||
, 4
|
||
c{I
|
||
,4
|
||
7
|
||
B,8
|
||
IA,8
|
||
8255
|
||
,4
|
||
c{1
|
||
,4
|
||
7
|
||
B,8, P~.PBO
|
||
Operating Modes
|
||
Mode1(Strobed Input/Output)
|
||
Thisfunctional configuration provides ameansfor.trans
|
||
ferringI/Odatatoorfromaspecified portinconjunction
|
||
withstrobesor"handshaking'~ signals.InMode1,PortA
|
||
andPortBusetheIinesonPortCtogenerate oraccept
|
||
these "handshaking~' signals.
|
||
5-120Mode1BasicFunctional Definitions:
|
||
•TwoGroups(GroupAandGroupB)
|
||
•Eachgroupcontains one8-bit·data-port andone4-bit
|
||
control/data port.
|
||
•The8-bitdataportcanbeeitherinput or output.
|
||
Bothinputsandoutputsarelatched.
|
||
•The4-bitportisusedforcontrolandstatusofthe
|
||
8-bitdataport.
|
||
|
||
===PAGE 189===
|
||
SILICON GATEMOS8255
|
||
InputControlSignalDefinition
|
||
STB(Strobe(nput)
|
||
A"low"onthisinputloadsdataintotheinputlatch.
|
||
IBF(InputBufferFullF/F)
|
||
A"high"onthisoutputindicates thatthedatahasbeen
|
||
loadedintotheinputlatch;inessence,anacknowledgement
|
||
ISFissetbythefallingedgeoftheSTBinputandisreset
|
||
bytherisingedgeoftheRDinput.
|
||
INTR(Interrupt Request)
|
||
A"high"onthisoutputcanbeusedtointerrupt theCPU
|
||
whenaninputdeviceisrequesting service.INTRissetby
|
||
therisingedgeofSTBifIBFisa"one"andINTEisa
|
||
"one".ItisresetbythefallingedgeofRD.Thisprocedure
|
||
allowsaninputdevicetorequestservicefromtheCPUby
|
||
simplystrobing itsdataintotheport.
|
||
INTEA
|
||
Controlled bybitset/reset ofPC4.
|
||
INTEB
|
||
Controlled bybitset/reset ofPC2.
|
||
MODE1(STROBED INPUT)
|
||
BASICTIMING
|
||
IBF
|
||
(INPUTBUFFER FULL)
|
||
DATA
|
||
INPUT
|
||
INTERNAL
|
||
INPUTLATCH
|
||
INTR
|
||
BasicTimingInput
|
||
5-121MODE1(PORTA)
|
||
CONTROL WORD
|
||
STBA
|
||
IBFA
|
||
INTRA
|
||
RD
|
||
I/O
|
||
MODE1(PORTB)
|
||
Mode1Input
|
||
"""""""'..........,~
|
||
NOPROTECTION
|
||
FORTHISOPERATION
|
||
\\-_--------
|
||
|
||
===PAGE 190===
|
||
SILICON GATEMOS8255
|
||
PC, OBFBP~.PBo 8r---,
|
||
IINTEI
|
||
IA I__.JMODE1(PORTA)
|
||
MODE1(PORTB)CONTROL WORD
|
||
CONTROL WORD
|
||
0706Os0403O20,Do
|
||
INTEA
|
||
Controlled bybitset/reset ofPC6.
|
||
INTEB
|
||
Controlled bybitset/reset ofPC2.OutputControlSignalDefinition
|
||
OBF(OutputBufferFullF/F)
|
||
TheOBFoutputwillgo~'Iow"toindicatethattheCPUhas
|
||
writtendataouttothespecified port.TheOBFF/Fwillbe
|
||
setbytherisingedgeoftheWRinputandresetbythefail
|
||
ingedgeoftheACKinputsignal.
|
||
ACK(Acknowledge Input)
|
||
A"Iow"onthisinputinformsthe8255thatthedatafrom
|
||
PortAorPortBhasbeenaccepted. Inessence, aresponse
|
||
fromtheperipheral deviceindicatingthatithasreceived
|
||
thedataoutputbytheCPU.
|
||
INTR(Interrupt Request)
|
||
A"high"onthisoutputcanbeusedtointerrupt theCPU
|
||
whenanoutputdevicehasaccepted datatransmitted bythe
|
||
CPU.INTRissetbytherisingedgeofACKifOBFisa
|
||
"one"andINTEisa"one".Itisresetbythefallingedge
|
||
ofWR.
|
||
Mode1Output
|
||
(OUTPUT BUFFER FULL)
|
||
/
|
||
NOPROTECTION
|
||
FORTHISOPERATION
|
||
DATABUS
|
||
OUTPUT\
|
||
~-----------------
|
||
BasicTimingOutput
|
||
5-122
|
||
|
||
===PAGE 191===
|
||
SILICON GATEMOS8255
|
||
Combinations ofMode1
|
||
PortAandPortBcanbeindividually definedasinputor
|
||
outputinMode1tosupportawidevarietyofstrobedI/O
|
||
applications.
|
||
PA7-PAO8
|
||
PC7OBFA
|
||
PC6-+-- ACKA
|
||
PC3 INTRA
|
||
2
|
||
PC4•5 I/O
|
||
PB7-PBo
|
||
PC2 STBB
|
||
PC, IBFB
|
||
PCo INTRBCONTROL WORD
|
||
PC,2
|
||
PC6•7..-.;-.-.. I/O
|
||
P~-PBO 8PA7-PAo 8
|
||
PC4 STBA
|
||
PCs IBFA
|
||
PC3 INTRA
|
||
INTRB
|
||
PORTA -(STROBED INPUT)
|
||
PORTB -(STROBED OUTPUT)PORTA -(STROBED OUTPUT)
|
||
PORTB -(STROBED INPUT)
|
||
Operating Modes
|
||
Mode2(Strobed Bi-Directional BusI/O)
|
||
Thisfunctional configuration provides ameansforcom
|
||
municating withaperipheral deviceorstructure onasingle
|
||
8-bitbusforbothtransmitting andreceiving data(bi-direc
|
||
tionalbusI/O)."Handshaking" signalsareprovided tomain
|
||
tainproperbusflowdiscipline inasimilarmannertoMode
|
||
1.Interrupt generation andenable/disable functionsare
|
||
alsoavailable.OutputOperations
|
||
OBF(OutputBufferFull)
|
||
TheOBFoutputwillgo"low"toindicatethattheCPUhas
|
||
writtendataouttoPortA.
|
||
ACK(Acknowledge)
|
||
A"Iow"onthisinputenablesthetri-stateoutputbufferof
|
||
PortAtosendoutthedata.Otherwise, theoutputbuffer
|
||
willbeinthehigh-impedance state.
|
||
Mode2BasicFunctional Definitions:
|
||
•UsedinGroupAonly.
|
||
•One8-bit,bi-directional busPort(PortA)anda5-bit
|
||
controlPort(PortC).
|
||
•Bothinputsandoutputsarelatched.
|
||
•The5-bitcontrolport(PortC)isusedforcontrol
|
||
andstatusforthe8-bit,bi-directional busport(Port
|
||
A).
|
||
Bi-Directional BusI/OControlSignalDefinition
|
||
INTR(Interrupt Request)
|
||
Ahighonthisoutputcanbeusedtointerrupt theCPUfor
|
||
bothinputoroutputoperations.INTE1(TheINTEFlip-Flop associated withOBF)
|
||
Controlled bybitset/reset ofPCs.
|
||
InputOperations
|
||
STB(StrobeInput)
|
||
A"low"onthisinputloadsdataintotheinputlatch.
|
||
IBF(InputBufferFullF/F)
|
||
A"high"onthisoutputindicates thatdatahasbeenloaded
|
||
intotheinputlatch.
|
||
INTE2(TheINTEFlip-Flop associated withIBF)
|
||
Controlled bybitset/reset ofPC4.
|
||
5-123
|
||
|
||
===PAGE 192===
|
||
SILICON GATEMOS8255
|
||
CONTROL WORD
|
||
Mode2ControlWordOBFA
|
||
pC200ACKA1=INPUT
|
||
0=OUTPUT
|
||
PORTBr--l
|
||
1=INPUTIN;EIPC4. STBA
|
||
0=OUTPUTL__J
|
||
PCsIBFA
|
||
WRGROUPBMODE
|
||
0=MODE0
|
||
1=MODE13
|
||
AD PC200.I/
|
||
•I/O
|
||
Mode2
|
||
INTR\'----" 1
|
||
IBF
|
||
DATABUS
|
||
(BETWEEN I/OCHIP- - - - - - -
|
||
ANDI/ODEVICE)
|
||
DATA
|
||
I/ODEVICE -+-I/OCHIP
|
||
Mode2(Bi-directional) Timing
|
||
5-124DATA
|
||
I/OCHIP -+I/ODEVICE
|
||
|
||
===PAGE 193===
|
||
SILICON GATEMOS8255
|
||
MODE2ANDMODE0(INPUT) MODE2ANDMODE0(OUTPUT)
|
||
PC3INTRA PC3INTRA
|
||
PA7-PAO PA7-PAo
|
||
~OBFA P~ OBFA
|
||
CONTROL WORD PC6. ACKA CONTROL WORD PC6. ACKA
|
||
070605 0403O20,DO 0706050403O20,DO
|
||
PC4STBA PC4. STBA
|
||
PC2.() PC5IBFAPC2.() PC5IBFA
|
||
1=INPUT 1=INPUT
|
||
O=OUTPUT 0=OUTPUT
|
||
3 3
|
||
PC2.() I/O PC2.().II"I/O
|
||
AD RO
|
||
P~-PBO PB7-PBO8
|
||
WR WR
|
||
MODE2ANDMODE1(OUTPUT) MODE2ANDMODE1(INPUT)
|
||
PC3
|
||
A -".
|
||
PA7-PAo~8
|
||
'fy
|
||
PC7
|
||
°PC6
|
||
20,DO
|
||
1PC4
|
||
PCs
|
||
A
|
||
PB7-PBOK8I
|
||
.....,
|
||
PC2.
|
||
.- PC,
|
||
. PCOWRROCONTROLWOR
|
||
ACKBPC3
|
||
A. ~
|
||
PA77PAo( 8~
|
||
PC7
|
||
°PC6
|
||
20,DO
|
||
0PC4
|
||
PCs
|
||
t-...
|
||
PB7-PBO 8)
|
||
PC2
|
||
PC,
|
||
PCORO
|
||
WRCONTROLWOR
|
||
Mode2Combinations
|
||
5-125
|
||
|
||
===PAGE 194===
|
||
SILICON GATEMOS8255
|
||
MODEDEFINITION SUMMARY TABLE
|
||
MODE0
|
||
IN OUT
|
||
PAO IN OUT
|
||
PA1 IN OUT
|
||
PA2 IN OUT
|
||
PA3 IN OUT
|
||
PA4 IN OUT
|
||
PAS IN OUT
|
||
PAe IN OUT
|
||
PA7 IN OUT
|
||
PBO IN OUT
|
||
P81 IN OUT
|
||
PB2 IN OUT
|
||
PB3 IN OUT
|
||
PB4 IN OUT
|
||
PB5 IN OUT
|
||
PBe IN OUT
|
||
PB7 IN OUT
|
||
PCO IN OUT
|
||
PC, IN OUT
|
||
PC2 IN OUT
|
||
PC3 IN OUT
|
||
PC4 IN OUT
|
||
PCS IN OUT
|
||
PC6 IN OUT
|
||
PC7 IN OUTMODE1
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
IN OUT
|
||
INTRB INTRB
|
||
IBFB OBFB
|
||
STBB ACKB
|
||
INTRA INTRA
|
||
STBA I/O
|
||
IBFA I/O
|
||
I/O ACKA
|
||
I/O OBFAMODE2
|
||
GROUPAONLY
|
||
~•••... ~
|
||
......
|
||
••... ~
|
||
~•... ~
|
||
----------------
|
||
I/O
|
||
I/O
|
||
I/O
|
||
INTRA
|
||
STBA
|
||
'IBFA
|
||
ACKA
|
||
OBFAMODE0
|
||
ORMODE1
|
||
ONLY
|
||
i
|
||
GROUPBi
|
||
GROUPAI i
|
||
GROUPA GROUPSINPUTCONFIGURATION
|
||
Os 03 Do
|
||
i i
|
||
GROUPA GROUPB
|
||
(DEFINED BYMODE0ORMODE1SELECTION)OUTPUT CONFIGURATION
|
||
0706Os0403O201Do
|
||
Mode1StatusWordFormat
|
||
Mode2StatusWordFormatallowstheprogrammer totestorverifythe"status" ofeach
|
||
peripheral deviceandchangetheprogram flowaccordingly..
|
||
Thereisnospecialinstruction toreadthestatusinforma
|
||
tionfromPortC.Anormalreadoperation ofPortCis
|
||
executed toperform thisfunction.
|
||
ReadingPortCStatus
|
||
InMode0,PortCtransfers datatoorfromtheperipheral
|
||
device.Whenthe8255isprogrammed tofunction inModes
|
||
1or2,PortCgenerates oraccepts"hand-shaking" signals
|
||
withtheperipheral device.Reading thecontents ofPortCSpecialModeCombination Considerations
|
||
Thereareseveralcombinations ofmodeswhennotallofthe
|
||
bitsinPortCareusedforcontrolorstatus.Theremaining
|
||
bitscanbeusedasfollows:
|
||
IfProgrammed asInputs-
|
||
Allinputlinescanbeaccessed duringanormalPortC
|
||
read.
|
||
IfProgrammed asOutputs -
|
||
BitsinCupper(PC7-PC4) mustbeindividually accessed
|
||
usingthebitset/reset function.
|
||
BitsinClower (PC3-PCO) canbeaccessed usingthebit
|
||
set/reset function oraccessed asathreesome bywriting
|
||
intoPortC.
|
||
SourceCurrentCapability onPortBandPortC
|
||
Anysetofeightoutputbuffers, selected randomly from
|
||
PortsBandCcansourcelmAat1.5volts.Thisfeature
|
||
allowsthe8255todirectly driveDarlington typedrivers
|
||
andhigh-voltage 'displays thatrequiresuchsourcecurrent.
|
||
5·126
|
||
|
||
===PAGE 195===
|
||
SILICON GATEMOS8255
|
||
PrinterInterfaceAPPLICATIONS OFTHE8255
|
||
TERMINAL
|
||
ADDRESSSTi
|
||
PC3-
|
||
PAo Ro
|
||
8255PA, R,
|
||
PA2R2FULLY
|
||
PA3R3DECODED
|
||
KEYBOARD
|
||
PA4R4
|
||
MODE1 _PAs Rs
|
||
(INPUT)PA6SHIFT
|
||
PA7CONTROL
|
||
PC4STROBE
|
||
PCsACK
|
||
~
|
||
-
|
||
PBoBo
|
||
PB, B,
|
||
PB2B2BURROUGHS
|
||
SELF·SCAN
|
||
PB3B3DISPLAY
|
||
PB4B4
|
||
PBs BsMODE1 _PB6BACKSPACE(OUTPUT)
|
||
PB7CLEAR
|
||
PC, DATAREADY
|
||
PC2ACK
|
||
PC6BLANKING
|
||
PCoL.fC7CANCEL WORD
|
||
UPT~
|
||
STi
|
||
PC3PAo Ro
|
||
PA, R,
|
||
PA2R2
|
||
PA3R3FULLY
|
||
MODE1 DECODED
|
||
(INPUT) -PA4R4KEYBOARD
|
||
PAs Rs
|
||
IPA6SHIFT
|
||
8255
|
||
PA7CONTROL
|
||
PC4STROBE
|
||
PCsACKNOWLEDGE
|
||
PC6BUSYLT
|
||
PC7TESTLT
|
||
f-------_----PBo....'0
|
||
PB, --~ ....
|
||
PB2 --'t>--"0MODE0PB3....
|
||
(INPUT) -PB4 --....
|
||
PBs--"",--PB6....--PB7....
|
||
~INTERR
|
||
REQUESTINTERRUPT
|
||
REQUE
|
||
INTERRUPT
|
||
REQUEKeyboard andDisplayInterfaceHIGH-SPEED
|
||
PRINTER
|
||
HAMMER
|
||
RELAYS
|
||
DATAREADY
|
||
ACK
|
||
PAPERFEED
|
||
FORWARD/REV
|
||
RIBBON
|
||
CARRIAGE SEN.DATAREADY
|
||
ACK
|
||
PAPERFEED
|
||
FORWARD/REV
|
||
CONTROL LOGICANDDRIVERSPC, DATAREADY
|
||
PC2ACK8255
|
||
MODEl
|
||
(OUTPUT)MODEl
|
||
(OUTPUT)The8255isaverypowerful toolforinterfacing peripheral
|
||
equipment tothe8080microcomputer system.Itrepresents
|
||
theoptimum useofavailable pinsandisflexibleenoughto
|
||
interface almostanyI/Odevicewithout theneedforad
|
||
ditionalexternal logic.
|
||
Eachperipheral deviceinaMicrocomputer systemusually
|
||
hasa"service routine" associated withit.Theroutineman
|
||
agesthesoftware interface between thedeviceandtheCPU.
|
||
Thefunctional definition ofthe8255isprogrammed bythe
|
||
I/Oserviceroutineandbecomes anextension ofthesys
|
||
temssoftware. Byexamining theI/Odevicesinterface char
|
||
acteristics forbothdatatransfer andtiming,andmatching
|
||
thisinformation totheexamples andtablesintheDetailed
|
||
Operational Description, acontrolwordcaneasilybede
|
||
velopedtoinitialize the8255toexactly"fit"theapplica
|
||
tion.Hereareafewexamples oftypicalapplications ofthe
|
||
8255.
|
||
INTERRUPT
|
||
REQUEST
|
||
INTERRUPT
|
||
REQUEST
|
||
Keyboard andTerminal Address Interface
|
||
5-127
|
||
|
||
===PAGE 196===
|
||
SILICON GATEMOS8255
|
||
STi
|
||
PC3r--
|
||
PBO Do
|
||
PB, 0,
|
||
PB2O2
|
||
PB303FLOPPY DISK
|
||
PB4..04CONTROLLER
|
||
ANDDRIVE
|
||
PBs DS
|
||
MODE2-PB606
|
||
PB707
|
||
PC4DATASTB
|
||
PCSACK(IN)
|
||
PC7DATAREADY
|
||
_Pe6ACK(OUT)
|
||
8255
|
||
PC2TRACK"0"SENSOR
|
||
PCoSYNCREADY
|
||
PC, INDEX
|
||
r-
|
||
PAO ENGAGE HEAD
|
||
PAl FORWARD/REV.
|
||
P~ READENABLE
|
||
MODE0 _P~ WRITEENABLE
|
||
(OUTPUT) PA4DISCSELECT
|
||
PAs ENABLE CRC
|
||
PAGTEST
|
||
_PA7 BUSYLTANALOG INPUTANALOG OUTPUTIP~LSB
|
||
PAl
|
||
PA2
|
||
IPA3JPA4
|
||
MODE0PASf-----------..
|
||
(OUTPUT) ;PA6 12-BIT
|
||
PA7D-A---.
|
||
CONVERTER
|
||
PC4(DAC)
|
||
PCS
|
||
8255PC6
|
||
'-PC7MSB
|
||
,PCOSTBDATA
|
||
PC, OUTPUT EN
|
||
BIT I
|
||
SET/RESETlPC2SAMPLE EN
|
||
PC3STB
|
||
,...-
|
||
PBOLSB
|
||
PB,8-BIT
|
||
A-D
|
||
PB2CONVERTER ..--
|
||
MODE0PB3(ADC)
|
||
-
|
||
(INPUT) PB4
|
||
PBS
|
||
PB6
|
||
P~ MSBINTERRUPT
|
||
REQUE
|
||
DigitaltoAnalog,AnalogtoDigital BasicFloppyDiscInterface
|
||
8LEVEL
|
||
PAPER
|
||
TAPE
|
||
READERPAo....-----1 RO
|
||
PAl R,
|
||
PA2R2
|
||
PA3R3
|
||
PA4R4
|
||
MODE1PAs Rs
|
||
(INPUT) -PAG RG
|
||
PA7R7CRTCONTROLLER
|
||
•CHARACTER GEN.
|
||
•REFRESH BUFFER
|
||
•CURSOR CONTROLINTERRUPT
|
||
REQUESTI
|
||
...-------------.--. PC3INTERRUPT
|
||
REQUESTi
|
||
PC3""-PAo~------t~. Ro
|
||
PAl R,
|
||
PA2R2
|
||
PA3R3
|
||
PA4R4
|
||
PAs RS
|
||
MODE1PA6SHIFT
|
||
(OUTPUT) -PA7CONTROL
|
||
PC7I-------t~. DATAREADY
|
||
PC6ACK
|
||
PCSBLANKED
|
||
PC4BLACK/WHITE
|
||
8255 L.- 8255PC4....---- ....STB
|
||
PCs ACK
|
||
PCGSTOP/GO L.- .... ...
|
||
MACHINE TOOL
|
||
-PC2I--------li~. ROWSTB
|
||
PC, COLUMN STB
|
||
PCOCURSORHNSTB{PCo START/STOP
|
||
MODE0PC.....-----1 LIMITSENSOR (H/V)(INPUT) 1
|
||
PC2....-----IOUTOF FLUID
|
||
PBOI--------t~.l
|
||
MODE0 _PB, !
|
||
(OUTPUT) PB2i
|
||
1
|
||
1CURSOR/ROW/COLUMN
|
||
PB3 :--ADDRESS
|
||
PB4 !H&V
|
||
PBs I
|
||
PB6J
|
||
,-P~.....----_.. .._------------~IPB CHANGE TOOLIPB:1--------t~.LEFT/RIGHT
|
||
JPB2 UP/DOWN
|
||
MODE0PB3HOR.STEPSTROBE
|
||
(OUTPUT) lPB4 VERT.STEPSTROBE
|
||
PBs SLEW/STEP
|
||
PBGFLUIDENABLE
|
||
PB7EMERGENCY STOP............__..1._-----------_ ...
|
||
BasicCRTController Interface Machine ToolController Interface
|
||
5-128
|
||
|
||
===PAGE 197===
|
||
~v ~V "",,-/7 "v'7
|
||
8080MEMORY8255
|
||
CPUROMAND 8255MODE2RAM
|
||
A~~ ..t. ~8255
|
||
MODE2SILICON GATEMOS8255
|
||
I
|
||
r--- ~----
|
||
MASTER CPUSYSTEM BUS(0,A,ANDC)
|
||
I-----,,-- 1----.--- t-----,
|
||
I
|
||
I
|
||
I
|
||
I
|
||
I
|
||
I
|
||
I
|
||
MASTER
|
||
I/O
|
||
L J8080
|
||
CPU
|
||
MEMORY
|
||
I/O8080
|
||
CPU
|
||
MEMORY
|
||
I/O
|
||
Distributed IntelligenceMulti-Processor Interface
|
||
5-129
|
||
|
||
===PAGE 198===
|
||
SILICON GATEMOS8255
|
||
D.C.CHARACTERISTICS TA=o°cto70°C;Vee=+5V±5%;vss=OV
|
||
Symbol Parameter Min. Typ. Max. Unit TestConditions
|
||
Vil InputLowVoltage .8 V
|
||
VIH InputHighVoltage 2.0 V
|
||
Val OutputLowVoltage .4 VIOl=1.6mA
|
||
VOH OutputHighVoltage 2.4 VIOH=-50JlA(-1OOJlAforD.B.Port)
|
||
IOH[1] Darlington DriveCurrent 2.0 rnAVOH=1.5V, REXT=390n
|
||
Ice PowerSupplyCurrent 40 rnA
|
||
NOTE:
|
||
1.Availableon8pinsonly.
|
||
A.C.CHARACTERISTICS TA=o°cto70°C;Vee=+5V±6%;Vss=OV
|
||
Symbol Parameter Min.Typ.Max. Unit TestCondition
|
||
twP PulseWidthofWR 430 ns
|
||
tow TimeD.B.StableBeforeWR 10 ns
|
||
two TimeD.B.StableAfterWR 65 ns
|
||
tAW TimeAddressStableBeforeWR 20 ns
|
||
tWA TimeAddressStableAfterWR 35 ns
|
||
tew TimeCSStableBeforeWR 20 ns
|
||
twe TimeCSStableAfterWR 35 ns
|
||
tWB DelayFromWRToOutput 500 ns
|
||
tRP PulseWidthofRD 430 ns
|
||
-50tlR RDSet-UpTime ns
|
||
tHR InputHoldTime 50 ns
|
||
tRO DelayFromRD= 0ToSystemBus 350 ns
|
||
too DelayFromRD= 1ToSystemBus 150 ns
|
||
tAR TimeAddressStableBeforeRD 50 ns
|
||
teR TimeCSStableBeforeRD 50 ns
|
||
tAK WidthOfACKPulse 500 ns
|
||
tST WidthOfSTBPulse 350 ns
|
||
tps Set-UpTimeForPeripheral 150 ns
|
||
tpH HoldTimeForPeripheral 150 ns
|
||
tRA HoldTimeforA1,AoAfterRD= 1 379 ns
|
||
'IRe HoldTimeForCSAfterRD= 1 5 ns
|
||
tAD TimeFromACK= 0ToOutput(Mode 2) 500 ns
|
||
tKO TimeFromACK= 1ToOutputFloating 300 ns
|
||
two TimeFromWR= 1ToOBF= 0 300 ns
|
||
tAO TimeFromACK= 0ToOBF= 1 500 ns
|
||
-600tSI TimeFromSTB= 0ToIBF ns
|
||
tRI TimeFromRD= 1ToIBF= 0 300 ns
|
||
5-130
|
||
|
||
===PAGE 199===
|
||
SILICON GATEMOS8255
|
||
INPUT
|
||
A1,AO.. tRP~
|
||
~
|
||
~ 7I[
|
||
.--t'R---' ~tHR-----"
|
||
>: K
|
||
tAR ~tRA--"
|
||
~~:~
|
||
~tCR----' tRC
|
||
\~ JV
|
||
:0- -------------~
|
||
tRD .. too ..
|
||
Mode0(BasicInput)
|
||
A1,AO
|
||
cs
|
||
OUTPUTtwp ..
|
||
~{
|
||
,--7f--
|
||
\
|
||
~tDW~ ~twD--'
|
||
)( K
|
||
tAW ..twA ..
|
||
)( JK
|
||
.. tcw .. twc~
|
||
\\r--J
|
||
)(.twB -------.
|
||
Mode0(BasicOutput)
|
||
5-131
|
||
|
||
===PAGE 200===
|
||
SILICON GATEMOS8255
|
||
IBF
|
||
~tRI
|
||
INTR
|
||
INPUTFROM _
|
||
PERIPHERAL
|
||
I...-----t ps-----.·
|
||
Mode1(Strobed Input)
|
||
INTR
|
||
OUTPUT
|
||
Mode1(Strobed Output)
|
||
5-132
|
||
|
||
===PAGE 201===
|
||
SILICON GATEMOS8255.
|
||
WR
|
||
tAO
|
||
OBF
|
||
INTR
|
||
ACK
|
||
STB
|
||
IBF
|
||
PERIPHERAL _
|
||
BUS
|
||
DATAFROM
|
||
PERIPHERAL TO8255
|
||
Mode2(Bi-directional)
|
||
5-133DATAFROM
|
||
8255TO8080
|
||
|
||
===PAGE 202===
|
||
|
||
|
||
===PAGE 203===
|
||
SiliconGateMOS8251
|
||
PROGRAMMABLE COMMUNICATION INTERFACE
|
||
..Synchronous andAsynchronous
|
||
Operation
|
||
•Synchronous:
|
||
5-8BitCharacters
|
||
InternalorExternalCharacter
|
||
Synchronization
|
||
Automatic Sy.ncInsertion
|
||
•Asynchronous:
|
||
5-8BitCharacters
|
||
ClockRate-1,16or64Times
|
||
BaudRate
|
||
BreakCharacter Generation
|
||
1,11h,or2StopBits
|
||
FalseStartBitDetection•BaudRate-DCto56kBaud(SyncMode)
|
||
DCt09.6kBaud(AsyncMode)
|
||
•FullDuplex,DoubleBuffered,
|
||
Transmitter andReceiver
|
||
•ErrorDetection -Parity,Overrun,
|
||
andFraming
|
||
•FullyCompatible with8080CPU
|
||
•28-PinDIPPackage
|
||
•AllInputsandOutputsAre
|
||
TTLCompatible
|
||
•Single5VoltSupply
|
||
•SingleTTLClock
|
||
The8251isaUniversal Synchronous/Asynchronous Receiver/Transmitter (USART)Chipdesigned fordata
|
||
communications inmicrocomputer systems. TheUSART isusedasaperipheral deviceandisprogrammed
|
||
bytheCPUtooperateusingvirtually anyserialdatatransmission technique presently inuse(including IBM
|
||
Bi-Sync). TheUSARTacceptsdatacharacters fromtheCPUinparallelformatandthenconverts theminto
|
||
acontinuous serialdatastreamfortransmission. Simultaneously itcanreceiveserialdatastreamsandcon
|
||
verttheminto.paralleldatacharacters fortheCPU.TheUSARTwillsignaltheCPUwhenever itcanaccept
|
||
anewcharacter fortransmission orwhenever ithasreceivedacharacter fortheCPU.TheCPUcanreadthe
|
||
complete statusoftheUSARTatanytime.Theseincludedatatransmission errorsandcontrolsignalssuch
|
||
asSYNDET, TxEMPT. Thechipisconstructed usingN-channel silicongatetechnology.
|
||
RxRDY
|
||
RxCRxDTxD
|
||
.....SYNDETTxRDY
|
||
TRANSMIT TxE
|
||
CONTROLTRANSMIT
|
||
BUFFER
|
||
(p....S)BLOCKDIAGRAM
|
||
/
|
||
INTERNAL
|
||
DATABUSPinName PinFunction
|
||
DSR DataSetReady
|
||
DTR DataTerminal Ready
|
||
SYNDET SyncDetect
|
||
RTS RequesttoSendData
|
||
CTS CleartoSendData
|
||
TxE Transmitter Empty
|
||
Vee +5VoltSupply
|
||
GND GroundPINCONFIGURATION
|
||
O201
|
||
03 Do
|
||
RxD Vee
|
||
GND RxC
|
||
04DTR 07-00
|
||
05 RTS
|
||
06DSR
|
||
07RESET
|
||
fXC CLK
|
||
WR TxD
|
||
CS TxEMPTY
|
||
C/O CTS
|
||
RD SYNDET
|
||
RxRDY TxRDY
|
||
PinNamePinFunction
|
||
07-00DataBus(8bits)
|
||
C/O ControlorDataistobeWrittenorRead
|
||
AD ReadDataCommand
|
||
WR WriteDataorControlCommand
|
||
Cs ChipEnable
|
||
CLK ClockPulse(TTL)
|
||
RESET Reset
|
||
TxC Transmitter Clock
|
||
TxD Transmitter Data
|
||
RxC ReceiverClock
|
||
RxD ReceiverData
|
||
RxRDY ReceiverReady(hascharacter for8080)
|
||
TxRDY Transmitter Ready(readyforchar.from8080)
|
||
5-135
|
||
|
||
===PAGE 204===
|
||
SILICON GATEMOS8251
|
||
8251BASICFUNCTIONAL DESCRIPTION
|
||
General
|
||
The8251isaUniversal Synchronous! Asynchronous Re
|
||
ceiver/Transmitter designed specifically forthe8080Micro
|
||
computer System.likeotherI!Odevicesinthe8080Micro
|
||
computer Systemitsfunctional configuration isprogrammed
|
||
bythesystemssoftware formaximum flexibility. The8251
|
||
cansupport virtually anyserialdatatechnique currently
|
||
inuse(including IBM"bi-sync").
|
||
Inacommunication environment aninterface devicemust
|
||
convert parallelformatsystemdataintoserialformatfor
|
||
transmission andconvert incoming serialformatdatainto
|
||
parallelsystemdataforreception. Theinterface devicemust
|
||
alsodeleteorinsertbitsorcharacters thatarefunctionally
|
||
uniquetothecommunication technique. Inessence, the
|
||
interface shouldappear"transparent" totheCPU,asimple
|
||
inputoroutputofbyte-oriented systemdata.
|
||
DataBusBuffer
|
||
This3-state, bi-directional,8-bit bufferisusedtointerface
|
||
the8251tothe8080systemDataBus.Dataistransmitted
|
||
orreceived bythebufferuponexecution ofINputorOUT
|
||
putinstructions ofthe8080CPU.Controlwords,Command
|
||
wordsandStatusinformation arealsotransferred through
|
||
theDataBusBuffer.
|
||
ReadlWrite Controllogic
|
||
Thisfunctional blockacceptsinputsfromthe8080Control
|
||
busandgenerates controlsignalsforoveralldeviceoperation.
|
||
Itcontains theControlWordRegister andCommand Word
|
||
Register thatstorethevariouscontrolformats fordevice
|
||
functional definition.
|
||
RESET(Reset)
|
||
A"high"onthisinputforcesthe8251intoan"Idie"mode.
|
||
Thedevicewillremainat"Idle"untilanewsetofcontrol
|
||
wordsiswrittenintothe8251toprogram itsfunctional
|
||
definition.
|
||
ClK(Clock)C/D(Control/Data)
|
||
Thisinput,inconjunction withtheWRandRDinputsin
|
||
formsthe8251thatthewordontheDataBusiseithera
|
||
datacharacter, controlwordorstatusinformation.
|
||
1=CONTROL 0=DATA
|
||
CS(ChipSelect)
|
||
A"low"onthisinputenablesthe8251.Noreadingorwrit
|
||
ingwilloccurunlessthedeviceisselected.
|
||
TheClKinputisusedtogenerate internaldevicetiming
|
||
andisnormally connected tothePhase2(TTL)outputof
|
||
the8224ClockGenerator. Noexternal inputs oroutputs
|
||
arereferenced toClKbutthefrequency ofClKmustbe
|
||
greaterthan30timestheReceiver orTransmitter clockin
|
||
putsforsynchronous mode(4.5timesforasynchronous
|
||
mode).
|
||
WR(Write)
|
||
A"Iow"onthisinputinformsthe8251thattheCPUis
|
||
outputting dataorcontrolwords,inessence, theCPUis
|
||
writingouttothe8251.
|
||
RD(Read)
|
||
A"Iow"onthisinputinformsthe8251thattheCPUisin
|
||
puttingdataorstatusinformation, inessence, theCPUis
|
||
readingfromthe8251.
|
||
5-136c/oRDWRCS
|
||
o0 1 0
|
||
o1 0 0
|
||
1 0 1 0
|
||
1 1 0 0
|
||
X X X 18251=>DATABUS
|
||
DATABUS=>8251
|
||
STATUS=> DATABUS
|
||
DATABUS=>CONTROL
|
||
DATABUS=>3-STATE
|
||
|
||
===PAGE 205===
|
||
SILICON GATEMOS8251
|
||
ModemControl
|
||
The8251hasasetofcontrolinputsandoutputsthatcan
|
||
beusedtosimplify theinterface toalmostanyModem.
|
||
Themodemcontrolsignalsaregeneralpurpose innature
|
||
andcanbeusedforfunctions otherthanModemcontrol,
|
||
ifnecessary.
|
||
DSR(DataSetReady)
|
||
TheDSRinputsignalisgeneralpurpose innature.Itscon
|
||
ditioncanbetestedbytheCPUusingaStatusReadopera
|
||
tion.TheDSRinputisnormally usedtotestModemcon
|
||
ditionssuchasDataSetReady.
|
||
DTR(DataTermin·al Ready)
|
||
TheDTRoutputsignalisgeneralpurpose innature.Itcan
|
||
beset"low"byprogramming theappropriate bitinthe
|
||
Command Instruction word.TheDTRoutputsignalisnorm
|
||
allyusedforModemcontrolsuchasDataTerminal Ready
|
||
orRateSelect.
|
||
RTS(Request toSend)
|
||
TheRTSoutputsignalisgeneralpurpose innature.Itcan
|
||
beset"low"byprogramr:ning theappropriate bitinthe
|
||
Command Instruction word.TheRTSoutputsignalisnorm
|
||
allyusedforModemcontrolsuchasRequest toSend.
|
||
CTS(CleartoSend)
|
||
A"low"onthisinputenablesthe8251totransmit data
|
||
(serial)iftheTxENbitintheCommand byteissettoa
|
||
"one."
|
||
Transmitter Buffer
|
||
TheTransmitter BufferacceptsparalleldatafromtheData
|
||
BusBuffer,converts ittoaserialbitstream,insertstheap
|
||
propriate characters orbits(basedonthe'communication
|
||
technique) andoutputsacomposite serialstreamofdataon
|
||
theTxDoutputpin.
|
||
Transmitter Control
|
||
TheTransmitter Control manages allactivities associated
|
||
withthetransmission ofserialdata.Itacceptsandissues
|
||
signalsbothexternally andinternally toaccomplish this
|
||
function.
|
||
TxRDY(Transmitter Ready)
|
||
ThisoutputsignalstheCPUthatthetransmitter isready
|
||
toacceptadata character~ Itcanbeusedasaninterrupt to
|
||
thesystemorforthePolledoperation theCPUcancheck
|
||
TxRDY usingastatusreadoperation. TxRDY isautomatic
|
||
allyresetwhenacharacter isloadedfromtheCPU.TxE(Transmitter Empty)
|
||
Whenthe8251hasnocharacters totransmit,theTxEout
|
||
putwillgo"high". Itresetsautomatically uponreceiving a
|
||
character fromtheCPU.TxEcanbeusedtoindicate the
|
||
endofatransmission mode,sothattheCPU"knows" when
|
||
to"turnthelinearound" inthehalf-duplexed operational
|
||
mode.
|
||
InSYNChronous mode,a"high"onthisoutputindicates
|
||
thatacharacter hasnotbeenloadedandtheSYNCcharac
|
||
terorcharacters areabouttobetransmitted automatically
|
||
as"fillers".
|
||
TxC(Transmitter Clock)
|
||
TheTransmitter Clockcontrols therateatwhichthechar
|
||
acteristobetransmitted. IntheSynchronous transmission
|
||
mode,thefrequency ofTxCisequaltotheactualBaud
|
||
Rate(1X).InAsynchronous transmission mode,thefre
|
||
quencyofTxCisamultiple oftheactualBaudRate.A
|
||
portion ofthemodeinstruction selectsthevalueofthe
|
||
multiplier; itcanbe1x,16xor64xtheBaudRate.
|
||
ForExample:
|
||
IfBaudRateequals110Baud,
|
||
TxCequals110Hz(1x)
|
||
TxCequals1.76kHz(16x)
|
||
TxCequals7.04kHz(64x).
|
||
IfBaudRateequals9600Baud,
|
||
TxCequals614.4kHz(64x).
|
||
ThefallingedgeofTxCshiftstheserialdataoutofthe
|
||
8251.
|
||
5-137
|
||
|
||
===PAGE 206===
|
||
ForExample:SILICON GATEMOS8251
|
||
ReceiverBuffer
|
||
TheReceiver acceptsserialdata,converts thisserialinput
|
||
toparallelformat, checksforbitsorcharacters thatare
|
||
uniquetothecommunication technique andsendsan
|
||
"assembled" character totheCPU.Serialdataisinputto
|
||
theRxDpin.
|
||
ReceiverControl
|
||
Thisfunctional blockmanages allreceiver-related activities.
|
||
RxRDY(Receiver Ready)
|
||
Thisoutputindicates thatthe8251contains acharacter that
|
||
isreadytobeinputtotheCPU.RxRDY canbeconnected
|
||
totheinterrupt structure oftheCPUorforPolledopera
|
||
tiontheCPUcancheckthecondition ofRxRDY usinga
|
||
statusreadoperation. RxRDY isautomatically resetwhen
|
||
thecharacter isreadbytheCPU.
|
||
RxC(Receiver Clock)
|
||
TheReceiver Clockcontrols therateatwhichthecharacter
|
||
istobereceived. InSynchronous Mode,thefrequency of
|
||
RxCisequal totheactualBaudRate(1x).InAsynchronous
|
||
Mode,thefrequency ofRxCisamultiple oftheactual
|
||
BaudRate.Aportionofthemodeinstruction selectsthe
|
||
valueofthemultiplier;itcanbe1x,16xor64xtheBaud
|
||
Rate.
|
||
IfBaudRateequals300Baud,
|
||
RxCequals300Hz(1x)
|
||
RxCequals4800Hz(16x)
|
||
RxCequals19.2kHz(64x).
|
||
IfBaudRateequals2400Baud,
|
||
RxCequals2400Hz(1x)
|
||
RxCequals38.4kHz(16x)
|
||
RxCequals153.6kHz(64x).
|
||
Dataissampled intothe8251ontherisingedgeofRxC.
|
||
NOTE:Inmostcommunications systems, the8251willbe
|
||
handling boththetransmission andreception operations of
|
||
asinglelink.Consequently, theReceiveandTransmit Baud
|
||
Rateswillbethesame.BothTxCandRxCwillrequireiden
|
||
ticalfrequencies forthisoperation andcanbetiedtogether
|
||
andconnected toasinglefrequency source(BaudRate
|
||
Generator) tosimplifytheinterface.
|
||
SYNDET (SYNCDetect)
|
||
ThispinisusedinSYNChronous Modeonly.Itisusedas
|
||
eitherinputoroutput,programmable through theControl
|
||
Word.Itisresetto"low"uponRESET. Whenusedasan
|
||
output (internal Syncmode),theSYNDET pinwillgo
|
||
"high"toindicate thatthe8251haslocatedtheSYNC
|
||
character intheReceive mode.Ifthe8251isprogrammed
|
||
tousedoubleSynccharacters (bi-sync), thenSYNDET will
|
||
go"high"inthemiddleofthelastbitofthesecondSync
|
||
character. SYNDET isautomatically resetuponaStatus
|
||
Readoperation.Whenusedasaninput,(external SYNCdetectmode),a
|
||
positivegoingsignalwillcausethe8251tostartassembling
|
||
datacharacters onthefallingedgeofthenextRxC.Once
|
||
inSYNC,the"high"inputsignalcanberemoved. Thedura
|
||
tionofthehighsignalshouldbeatleastequaltotheperiod
|
||
ofRxC.
|
||
\ADDRESS BUS \
|
||
Ao
|
||
\CONTROL BUS \
|
||
I/ORI/OWRESET t/>2
|
||
(TTL)
|
||
\ DATABUS \n
|
||
(~7 t'\ (
|
||
C/Ocs 07-00RD WRRESET ClK
|
||
8251
|
||
8251Interface to8080Standard SystemBus
|
||
5-138
|
||
|
||
===PAGE 207===
|
||
SILICON GATEMOS8251
|
||
DETAILED OPERATION DESCRIPTION
|
||
General
|
||
Thecomplete functional definition ofthe8251isprogram
|
||
medbythesystemssoftware. Asetofcontrolwordsmust
|
||
besentoutbytheCPUtoinitialize the8251tosupportthe
|
||
desiredcommunications format.Thesecontrolwordswill
|
||
program the:BAUDRATE,CHARACTER LENGTH,
|
||
NUMBER OFSTOPBITS,SYNCHRONOUS orASYNCH
|
||
RONOUS OPERATION, EVEN/ODD PARITY etc.Inthe
|
||
Synchronous Mode,optionsarealsoprovided toselecteither
|
||
internalorexternalcharacter synchronization.
|
||
Once programmed~ the8251isreadytoperform itscom
|
||
munication functions. TheTxRDYoutputisraised"high"
|
||
tosignaltheCPUthatthe8251isreadytoreceiveachar
|
||
acter.Thisoutput(TxRDY) isresetautomatically whenthe
|
||
CPUwdtesacharacter intothe8251.Ontheotherhand,
|
||
the8251receivesserialdatafromtheMODEM orI/Ode
|
||
vice,uponreceiving anentirecharacter theRxRDYoutput
|
||
israised"high"tosignaltheCPUthatthe8251hasacom
|
||
pletecharacter readyfortheCPUtofetch.RxRDYisreset
|
||
automatically upontheCPUreadoperation.
|
||
The8251cannotbegintransmission untiltheTxEN(Trans
|
||
mitterEnable)bitissetintheCommand Instruction and
|
||
ithasreceived aClearToSend(CTS)input.TheTxDout
|
||
putwillbeheldinthemarkingstateuponReset.
|
||
Programming the8251
|
||
Priortostartingdatatransmission orreception, the8251
|
||
mustbeloadedwithasetofcontrolwordsgenerated by
|
||
theCPU.Thesecontrolsignalsdefinethecomplete func
|
||
tionaldefinition ofthe8251andmustimmediately follow
|
||
aResetoperation (internal orexternal).
|
||
Thecontrolwordsaresplitintotwoformats:
|
||
1.ModeInstruction
|
||
2.Command Instruction
|
||
ModeInstruction
|
||
Thisformatdefinesthegeneraloperational characteristics
|
||
ofthe8251.ItmustfollowaResetoperation (internal or
|
||
external). OncetheModeinstruction hasbeenwritteninto
|
||
the8251bytheCPU,SYNCcharacters orCommand in
|
||
structions maybeinserted.
|
||
Command Instruction
|
||
Thisformatdefinesastatuswordthatisusedtocontrol
|
||
theactualoperation ofthe8251.
|
||
BoththeModeandCommand instructions mustconform to
|
||
aspecified sequence forproperdeviceoperation. TheMode
|
||
Instruction mustbeinsertedimmediately following aReset
|
||
operation, priortousingthe8251fordatacommunication.Allcontrolwordswrittenintothe8251aftertheModeIn
|
||
struction willloadtheCommand Instruction. Command In
|
||
structions canbewrittenintothe8251atanytimeinthe
|
||
datablockduringtheoperation ofthe8251.Toreturnto
|
||
theModeInstruction formatabitintheCommand Instruc
|
||
tionwordcanbesettoinitiateaninternalResetoperation
|
||
whichautomatically placesthe8251backintotheMode
|
||
Instruction format.Command Instructions mustfollowthe
|
||
ModeInstructions orSynccharacters.
|
||
C/O::1MODEINSTRUCTION
|
||
C/O::1SYNCCHARACTER 1
|
||
}SYNCMODE
|
||
C/o=1SYNCCHARACTER 2ONLY·
|
||
C/D::1COMMAND INSTRUCTION
|
||
C/D::0 DATA
|
||
C/o::1COMMAND INSTRUCTION
|
||
C/o:;;:0 DATA
|
||
C/O::::1COMMAND INSTRUCTION
|
||
·ThesecondSYNCcharacter isskippedifMODEinstruction
|
||
hasprogrammed the8251tosinglecharacter InternalSYNC
|
||
Mode.BothSYNCcharacters areskippedifMODEinstruction
|
||
hasprogrammed the8251toASYNCmode.
|
||
TypicalDataBlock
|
||
5-139
|
||
|
||
===PAGE 208===
|
||
SILICON GATEMOS8251
|
||
ModeInstruction Definition
|
||
The8251canbeusedforeitherAsynchronous orSynchro
|
||
nousdatacommunication. Tounderstand howtheMode
|
||
Instruction definesthefunctional operation ofthe8251the
|
||
designercanbestviewthedeviceastwoseparate components
|
||
sharingthesamepackage. OneAsynchronous theother
|
||
Synchronous. Theformatdefinition canbechanged lion
|
||
thefly"butforexplanation purposes thetwoformatswill
|
||
beisolated.
|
||
Asynchronous Mode(Transmission)
|
||
Whenever adatacharacter issentbytheCPUthe8251
|
||
automatically addsaStartbit(lowlevel)andtheprogram
|
||
mednumberofStopbitstoeachcharacter. Also,aneven
|
||
oroddParitybitisinserted priortotheStopbit(s),asde
|
||
finedbytheModeInstruction. Thecharacter isthentrans
|
||
mittedasaserialdatastreamontheTxDoutput.Theserial
|
||
dataisshiftedoutonthefallingedgeofTxCatarateequal
|
||
to1,1/16,or1/64thatoftheTxC,asdefinedbytheMode
|
||
Instruction. 8REAKcharacters canbecontinuously sentto
|
||
theTxDifcommanded todoso.
|
||
Whennodatacharacters haveloadedintothe8251the
|
||
TxDoutputremains"high"(marking) unlessaBreak(con
|
||
tinuously low)hasbeenprogrammed.I~I81IEPIPENI~1 L11B21B1I
|
||
LBAUDRATEFACTOR
|
||
0 1 0 1
|
||
0 0 1 1
|
||
SYNC(1X)(16X)(64X)MODE
|
||
CHARACTER LENGTH
|
||
010 1
|
||
00 1 1
|
||
567 8
|
||
BITSBITSBITS BITS
|
||
PARITY ENABLE
|
||
1=ENABLE 0=DISABLE
|
||
EVENPARITYGENERATION/CHE
|
||
1=EVEN0=000
|
||
NUMBER OFSTOPBITS
|
||
0 1 0 1
|
||
0 0 1 1
|
||
INVALID11% 2
|
||
BITBITSBITS
|
||
ModeInstruction Format,Asynchronous ModeCK
|
||
Asynchronous Mode(Receive)
|
||
TRANSMITTER OUTPUT
|
||
ASSEMBLED SERIALDATAOUTPUT (TxD)ST6;"l
|
||
BrTSLST~
|
||
BITSL
|
||
STO[]BITS
|
||
......---..a---...&----fDATA:B\-IT_S_....-.__...
|
||
SERIALDATAINPUT(RxD)CPUBYTE(5·8BITS/CHAR)
|
||
DATAC~~RACTER
|
||
DATACHARACTERSTART
|
||
BIT
|
||
RECEIVE FORMATRxD
|
||
TRANSMISSION FORMATRECEIVER INPUTTxDMARKINGTheRxDlineisnormally high.Afallingedgeonthisline
|
||
triggersthebeginning ofaSTART bit.Thevalidityofthis
|
||
STARTbitischecked byagainstrobing thisbitatitsnom
|
||
inalcenter.Ifalowisdetected again,itisavalidSTART
|
||
bit,andthebitcounterwillstartcounting. Thebitcounter
|
||
locatesthecenterofthedatabits,theparitybit(ifitex
|
||
ists)andthestopbits.Ifparityerroroccurs,theparityer
|
||
rorflagisset. Data andparitybitsaresampled ontheRxD
|
||
pinwiththerisingedgeofRxC.Ifalowlevelisdetected as
|
||
theSTOPbit,theFraming Errorflagwillbeset.TheSTOP
|
||
bitsignalstheendofacharacter. Thischaracter isthen
|
||
loadedintotheparallelI/Obufferofthe8251.TheRxRDY
|
||
pinisraisedtosignaltheCPUthatacharacter isreadyto
|
||
befetched. If aprevious character hasnotbeenfetchedby
|
||
theCPU,thepresentcharacter replaces itintheI/Obuf
|
||
fer,andtheOVERRUN flagisraised(thustheprevious
|
||
character islost).Alloftheerrorflagscanberesetbya
|
||
command instruction. Theoccurrence ofanyoftheseer
|
||
rorswillnotstoptheoperation ofthe8251.
|
||
DATACHARACTER STOtJBITSf----.&.---.Iooo----t
|
||
CPUBYTE(5·8BITS/CHAR)*
|
||
DATACH:;ACTER
|
||
*NOTE:IFCHARACTER LENGTH ISDEFINED AS5,6OR7
|
||
BITSTHEUNUSED BITSARESETTO"ZERO".
|
||
Asynchronous Mode
|
||
5-140
|
||
|
||
===PAGE 209===
|
||
SILICON GATEMOS8251
|
||
o 0 1 1
|
||
5 6 7 8
|
||
BITS BITS BITSBITS
|
||
L.....- -..PARITY ENABLE
|
||
(1=ENABLE)
|
||
(0=DISABLE)1 0CHARACTER LENGTH
|
||
o
|
||
L.....- ..EVENPARITYGENERATION/CHECK
|
||
1cEVEN
|
||
0=000Synchronous Mode(Transmission)
|
||
TheTxDoutputiscontinuously highuntiltheCPUsends
|
||
itsfirstcharacter tothe8251whichusuallyisaSYNC
|
||
character. WhentheCTSlinegoeslow,thefirstcharacter
|
||
isseriallytransmitted out.Allcharacters areshiftedouton
|
||
thefallingedgeofTxC.Dataisshiftedoutatthesame
|
||
rateastheTxC.
|
||
Oncetransmission hasstarted,thedatastreamatTxDout
|
||
putmustcontinue attheTxCrate.IftheCPUdoesnotpro
|
||
videthe8251withacharacter beforethe8251becomes
|
||
empty,theSYNCcharacters (orcharacter ifinsingleSYNC
|
||
wordmode)willbeautomatically insertedintheTxDdata
|
||
stream.Inthiscase,theTxEMPTY pinisraisedhightosig
|
||
nalthatthe8251isemptyandSYNCcharacters arebeing
|
||
sentout.TheTxEMPTY pinisinternally resetbythenext
|
||
character beingwrittenintothe8251.'"-----------.. EXTERNAL SYNCDETECT
|
||
1=SYNDET ISANINPUTo=SYNDET ISANOUTPUT
|
||
SERIALDATAINPUT(RxD)RECEIVE FORMAT
|
||
DATACHAR~~C_TE_R_S ___
|
||
CPUBYTES(5-8BITS/CHAR)
|
||
~f
|
||
DATA CH:~ACTERSCPUBYTES(5-8BITS/CHAR)
|
||
DATAC~~RACTERS
|
||
ASSEMBLED SERIALDATAOUTPUT (TxD)
|
||
DATACHA~~AC_T_E_RS ~"------------- ....SINGLECHARACTER SYNC
|
||
1=SINGLESYNCCHARACTER
|
||
0=DOUBLE SYNCCHARACTER
|
||
ModeInstruction Format,Synchronous ModeSynchronous Mode(Receive)
|
||
Inthismode,character synchronization canbeinternally
|
||
orexternally achieved. IftheinternalSYNCmodehasbeen
|
||
programmed, thereceiverstartsinaHUNTmode.Dataon
|
||
theRx.Dpinisthensampled inontherisingedgeofRxC.
|
||
Thecontent oftheRxbufferiscontinuously compared
|
||
withthefirstSYNCcharacter untilamatchoccurs.Ifthe
|
||
8251hasbeenprogrammed fortwoSYNCcharacters, the
|
||
subsequent received character isalsocompared; whenboth
|
||
SYNCcharacters havebeendetected, theUSARTendsthe
|
||
HUNTmodeandisincharacter synchronization. TheSYN
|
||
DETpinisthensethigh,andisresetautomatically bya
|
||
STATUS READ.
|
||
IntheexternalSYNCmode,synchronization isachieved by
|
||
applying ahighlevelontheSYNDET pin.Thehighlevelcan
|
||
beremoved afteroneRxCcycle.
|
||
Parityerrorandoverrunerrorarebothchecked inthesame
|
||
wayasintheAsynchronous Rxmode.
|
||
TheCPUcancommand thereceivertoentertheHUNT
|
||
modeifsynchronization islost.
|
||
Synchronous Mode,Transmission Format
|
||
5-141
|
||
|
||
===PAGE 210===
|
||
SILICON GATEMOS8251
|
||
COMMAND INSTRUCTION DEFINITION
|
||
Oncethefunctional definition ofthe8251hasbeenpro
|
||
grammed bytheModeInstruction andtheSyncCharacters
|
||
areloaded(ifin·SyncMode)thenthedeviceisreadytobe
|
||
usedfordatacommunication. TheCommand Instruction
|
||
controls theactualoperation oftheselectedformat.Func
|
||
tionssuchas:EnableTransmit/Receive, ErrorResetand
|
||
ModemControls areprovided bytheCommand Instruction.
|
||
OncetheModeInstruction hasbeenwrittenintothe8251
|
||
andSynccharacters inserted, ifnecessary, thenallfurther
|
||
"control writes" (C/O=1)willloadtheCommand In
|
||
struction. AResetoperation (internal orexternal) will
|
||
returnthe8251totheModeInstruction Format.STATUS READDEFINITION
|
||
Indatacommunication systems itisoftennecessary to
|
||
examine the"status" oftheactivedevicetoascertain if
|
||
errorshaveoccurredorotherconditionsthatrequirethe
|
||
processor's attention. The8251hasfacilitiesthatallowthe
|
||
programmer to"read"thestatusofthedeviceatanytime
|
||
duringthefunctionaloperation.
|
||
Anormal"read"command isissuedbytheCPUwiththe
|
||
C/Oinputatonetoaccomplish thisfunction.
|
||
SomeofthebitsintheStatusReadFormathaveidentical
|
||
meanings toexternal outputpinssothatthe8251canbe
|
||
usedinacompletely Polledenvironment orinaninterrupt
|
||
drivenenvironment.
|
||
TRANSMIT ENABLE
|
||
1=enable
|
||
0=disableSAMEDEFINITIONS ASI/OPINS
|
||
DATATERMINAL~ READY
|
||
"high"willforceDTR
|
||
outputtozero
|
||
RECEIVE ENABLE
|
||
'------~ 1=enable
|
||
0=disable
|
||
SENDBREAK
|
||
CHARACTER
|
||
1=forcesTxD"Iow"o=normaloperation
|
||
ERROR RESET-----------.. 1=resetallerrorflags
|
||
PE,OE,FE
|
||
REQUEST TOSEND
|
||
L.-- --.."high"willforceRTS
|
||
outputtozero
|
||
INTERNAL RESET
|
||
L.-- ......."high"returns8251to
|
||
ModeInstruction Format
|
||
ENTERHUNTMODE
|
||
L.-- --..1=enablesearchforSync
|
||
Characters
|
||
Command Instruction FormatPARITY ERROR
|
||
ThePEflagissetwhenaparity
|
||
errorisdetected. Itisresetby
|
||
theERbitoftheCommand
|
||
Instruction. PEdoesnotinhibit
|
||
operation ofthe8251.
|
||
OVERRUN ERROR
|
||
TheOEflagissetwhentheCPU
|
||
doesnotreadacharacter before
|
||
thenextonebecomes available.
|
||
ItisresetbytheERbitofthe
|
||
Command Instruction. OEdoes
|
||
notinhibitoperation ofthe8251;
|
||
however, thepreviously overrun
|
||
character islost.
|
||
FRAMING ERROR (Asynconly)
|
||
TheFEflagissetwhenavalid
|
||
Stopbitisnotdetected atthe
|
||
endofeverycharacter. Itisreset
|
||
bytheERbitoftheCommand
|
||
Instruction. FEdoesnotinhibit
|
||
theoperation ofthe8251.
|
||
StatusReadFormat
|
||
5-142
|
||
|
||
===PAGE 211===
|
||
SILICON GATEMOS8251
|
||
APPLICATIONS OFTHE8251
|
||
ADDRESS BUS ADDRESS BUS
|
||
CONTROL BUS CONTROL BUS
|
||
DATABUS DATABUS
|
||
r----'
|
||
IEIATOTTL:.QJ)ICONVERTI
|
||
PHONE (OPT)8251L____ J::ASYNC LINE
|
||
MODEM INTER·
|
||
BAUDRATECRTFACE
|
||
TxCGENERATORTERMINAL8251
|
||
Asynchronous SerialInterface toCRTTerminal,
|
||
DC-9600 Baud
|
||
Asynchronous Interface toTelephone LinesTELEPHONE
|
||
LINE
|
||
ADDRESS BUS L.- .....
|
||
SYNCHRONOUS
|
||
TERMINAL
|
||
ORPERIPHERAL
|
||
DEVICE
|
||
SYNDET1-----+1
|
||
Synchronous Interface toTerminal orPeripheral Device
|
||
5-143SYNC
|
||
MODEM
|
||
Synchronous Interface toTelephone LinesPHONE
|
||
LINE
|
||
INTER·
|
||
FACE
|
||
TELEPHONE
|
||
LINE
|
||
|
||
===PAGE 212===
|
||
SILICON GATEMOS8251
|
||
D.C.Characteristics:
|
||
Symbol Parameter Min. Typ. Max. Unit TestConditions
|
||
V,L InputLowVoltage Vss-·5 0.8 V
|
||
VIH InputHighVoltage 2.0 Vee V
|
||
VOL OutputLowVoltage 0.45 V IOl=1.6mA
|
||
VOH OutputHighVoltage 2.2 V IOH=-1001lA(DBo-7)
|
||
IOH=-1001lA(Others)
|
||
IOL DataBusLeakage 50 IJ.A VOUT=4.5V
|
||
ILl InputLoadCurrent 10IlA @5.5V
|
||
Icc PowerSupplyCurrent 45 80
|
||
Capacitance
|
||
TA=25°C;Vee=vss=OV
|
||
Symbol Parameter Min. Typ. Max. Unit TestConditions
|
||
CtN InputCapacitance 10 pF fc=1MHz
|
||
CliO I/OCapacitance 20 pF Unmeasured pinsreturnedtoVss.
|
||
5-144
|
||
|
||
===PAGE 213===
|
||
SILICON GATEMOS8251
|
||
A.C.Characteristics:
|
||
TA=o°cto70°C;VCC=5.0V±5%;Vss=OV
|
||
Symbol Parameter Min.Typ. Max. Unit TestConditions
|
||
tCY ClockPeriod .420 1.35 JlS
|
||
t</JW ClockPulseWidth 220 300 ns
|
||
tR,tF ClockRiseandFallTime 0 50 ns
|
||
tWR WRITEPulseWidth 430 ns
|
||
tos DataSet-UpTimeforWRITE 0 ns
|
||
tOH DataHoldTimeforWRITE 65 ns
|
||
tAW AddressStablebeforeWRITE 20 ns
|
||
tWA AddressHoldTimeforWRITE 35 ns
|
||
tRO READPulseWidth 430 ns
|
||
too DataDelayfromREAD 350 ns CL=100pF
|
||
tOF READtoDataFloating 150 ns Cl=100pF
|
||
tAR1 AddressStablebeforeREAD,CE(C/D) 50 ns
|
||
tRA1 AddressHoldTimeforREAD,CE 5 ns
|
||
tRA2 AddressHoldTimeforREAD,C/O 370 ns
|
||
tOTx TxDDelayfromFallingEdgeofTxC 1 JlS CL=100pF
|
||
tSRx RxDataSet-UpTimetoSampling Pulse 2 J.l.S Cl=100pF
|
||
tHRx RxDataHoldTimetoSampling Pulse 2 J.l.S CL=100pF
|
||
fTx Transmitter InputClockFrequency
|
||
1XBaudRate DC 56 KHz
|
||
16Xand64XBaudRate DC 615 KHz
|
||
fRx Receiver InputClockFrequency
|
||
1XBaudRate DC 56 KHz
|
||
16Xand64XBaudRate DC 615 KHz
|
||
tTx TxRDYDelayfromCenterofDataBit 16ClKPeriod CL=50pF
|
||
tRx RxRDYDelayfromCenterofDataBit 15 20ClKPeriod
|
||
tiS InternalSyndetDelayfromCenterofDataBit 20 25ClKPeriod
|
||
tES External SyndetSet-UpTimebeforeFalling 15ClKPeriod
|
||
EdgeofRxC
|
||
Note:TheTxCandRxefrequencies havethefollowing IimitationwithrespecttoClK.
|
||
ForASYNCMode,tTxortRx~4.5tCY
|
||
ForSYNCMode,tTxortRx~30tCY
|
||
5-145
|
||
|
||
===PAGE 214===
|
||
SILICON GATEMOS8251
|
||
READANDWRITETIMING
|
||
CID,CS. ..,1'----------------""1"---------"1'--
|
||
D7-DO-----..--'I~
|
||
~-- tDS-------1~ ..--
|
||
*WRITE------J---..:.-/'..--- twR
|
||
1""-'-----...,t.......---
|
||
·WRITEANDREADPULSESHAVENOTIMINGLIMITATION WITHRESPECT TOClK.
|
||
TRANSMITTER CLOCKANDDATA
|
||
TxC(1xBAUDI
|
||
TxC(16xBAUD) 4IlI
|
||
--~~fTxD __I J;:-
|
||
16TxCPERIODS-------::;C _
|
||
___x---
|
||
RECEIVER CLOCKANDDATA
|
||
RXD=..:..t_-tsRX---f:l:--tHRX--~ - - ---
|
||
RxC(1xBAUD)~'-____________ \
|
||
INTERNAL
|
||
SAMPLING n PULSE 10- _
|
||
RXD~----STARTBIT----:r __~st~A~A:T_-.:-3l=----
|
||
14111--- tSRX~4IlI---- tHRX~
|
||
RiC(16xBAUD)
|
||
INTERNAL
|
||
~~~~ING ---.1 ~~ _
|
||
TxRDYANDRxRDYTIMING (ASYNC MODE)
|
||
RxD---, STARTBITIDATABITS
|
||
tRXq
|
||
RXRDY___________ __
|
||
READ
|
||
WRITE
|
||
WRITE1stBYTEWRITE2ndBYTE
|
||
TxDMA'R'i<'i'NGJ STARTBIT-I--D-A-TA-BI-T-l~l\-----...------+--~~~~
|
||
I. 1stDATABYTe--------.-1TxRDYTxEMPTY
|
||
INTERNAL SYNCDETECT
|
||
1......,---------- SYNCCHARACTER (01101001)---------1·.-11
|
||
RxD-----I 1stBIT 1 1 ~ASTBIT,----1-
|
||
RESETBY
|
||
SYNDET tiS~/ SOFTWARE
|
||
(OUTPUT)--------------------------~ COMMAND
|
||
EXTERNAL SYNCDETECT
|
||
nRxC---,~ ... 1~ ~~I00...- __ """'"------1F tESSYNDET -
|
||
(INPUT)
|
||
~D:==:==::::==~I~~~~~~~~~~~~~~~~I
|
||
114.,...------- 1stDATABYTE------ ••11
|
||
5-146
|
||
|
||
===PAGE 215===
|
||
Peripherals
|
||
8205
|
||
8214
|
||
8216/8226
|
||
|
||
===PAGE 216===
|
||
|
||
|
||
===PAGE 217===
|
||
Schottky Bipolar8205
|
||
HIGHSPEED1OUTOF8BINARYDECODER
|
||
•110PortorMemorySelector
|
||
•SimpleExpansion -EnableInputs
|
||
•HighSpeedSchottky Bipolar
|
||
Technology -18nsMax.Delay
|
||
•DirectlyCompatible withTTLLogic
|
||
Circuits•LowInputLoadCurrent-.25mA
|
||
max.,1/6Standard TTLInputLoad
|
||
•Minimum Line Reflection -Low
|
||
VoltageDiodeInputClamp
|
||
•OutputsSink10mAmin.
|
||
•16-PinDual-In-Line Ceramicor
|
||
PlasticPackage
|
||
The8205decoder canbeusedforexpansion ofsystemswhichutilizeinputports,outputports,andmem
|
||
orycomponents withactivelowchipselectinput.Whenthe8205isenabled, oneofitseightoutputs goes
|
||
"Iow",thusasinglerowofamemory systemisselected. The3chipenableinputsonthe8205alloweasy
|
||
systemexpansion. Forverylargesystems, 8205decoders canbecascaded suchthateachdecoder candrive
|
||
eightotherdecoders forarbitrary memory expansions.
|
||
TheIntel@8205 ispackaged in"astandard 16pindual-in-line package; anditsperformance isspecified over
|
||
thetemperature rangeofO°Cto+75°C,ambient. TheuseofSchottky barrierdiodeclamped transistors to
|
||
obtainfastswitching speedsresultsinhigherperformance thanequivalent devicesmadewithagolddiffu
|
||
sionprocess.
|
||
PINCONFIGURATION LOGICSYMBOL
|
||
Ao 16 V-cc Ao 00
|
||
A12 15°0A, 0,
|
||
A23 1401 A2 02
|
||
E14 13°2 0382058205
|
||
E25 12°3 04
|
||
E36 1104 E, Os
|
||
077 10°5 E2 06
|
||
GRD 8 9°6 E3 07
|
||
PINNAMES
|
||
AO-A2 ADDRESS INPUTS
|
||
E,-E3ENABLE INPUTS
|
||
°0.°7 DECODED OUTPUTSADDRESS ENABLE OUTPUTS
|
||
AoA,A2E,E2E30,234567
|
||
l l lllHL H H H H HHH
|
||
HLLL L H H lH H HHHH
|
||
L H LlL H H HLHHHHH
|
||
H H LL L HH H HL H H H H
|
||
LLHL L HHHHHL H H H
|
||
HLHL L H H HH H HLHH
|
||
lHHL L H H HH H HHLH
|
||
H H HLLH H H H H HH H L
|
||
X X XLLLHH H H...HHH
|
||
XXXHLLHH H HHHHH
|
||
XXXL H LHH H HHH H H
|
||
XXXHHLHH H H HH H H
|
||
XXXHLHHH H HHHHH
|
||
X X XLHH H HH H H HHH
|
||
XXXHHHHHHHHH H H,
|
||
5-147
|
||
|
||
===PAGE 218===
|
||
SCHOTTKY BIPOLAR 8205
|
||
FUNCTIONAL DESCRIPTION
|
||
Decoder
|
||
The8205contains aoneoutofeightbinarydecoder. Itac
|
||
ceptsathreebitbinarycodeandbygatingthisinput,creates
|
||
anexclusive outputthatrepresents thevalueoftheinput
|
||
code.
|
||
Forexample, ifabinarycodeof101waspresentontheAO,
|
||
A1andA2addressinputlines,andthedevicewasenabled,
|
||
anactivelowsignalwouldappearonthe05outputline.
|
||
Notethatalloftheotheroutputpinsaresittingatalogic
|
||
high,thusthedecoded outputissaidtobeexclusive. The
|
||
decoders outputswillfollowthetruthtableshownbelowin
|
||
thesamemannerforallotherinputvariations.
|
||
EnableGate
|
||
Whenusingadecoder itisoftennecessary togatetheout
|
||
putswithtimingorenabling signalssothattheexclusive
|
||
outputofthedecoded valueissynchronous withtheoverall
|
||
system.
|
||
The8205hasabuitt-infunction forsuchgating.Thethree
|
||
enableinputs(E1,E2,E3)areANDedtogether andcreate
|
||
asingleenablesignalforthedecoder. Thecombination of
|
||
bothactive"high"andactive"Iow"deviceenableinputs
|
||
providesthedesigner withapowerfully flexiblegatingfunc
|
||
tiontohelpreducepackagecountinhissystem.~
|
||
I"".l-
|
||
I"".I-.
|
||
I""
|
||
....-DECODER-....
|
||
l-
|
||
I""
|
||
-....
|
||
...........
|
||
ENABLE GATE--_"I"' (E'i·"E2·E3).!......I
|
||
ADDRESS ENABLE OUTPUTS
|
||
AoA,A2E,E2E301 2 34567
|
||
LL L L L H L HHH H H HH
|
||
HLLLLHHLH H HHHH
|
||
LHLL L HH H L H H HH H
|
||
HHL L L HHHHLHH H H
|
||
LLHL L HHHHHLHH H
|
||
HLHLLH H HHHHLHH
|
||
LHHL L HHHHHHHLH
|
||
HHHLLH H H H H H HHL
|
||
XX X L L L H HHHHHHH
|
||
XXXHL L HH H H HHHH
|
||
XXXLHLHHHH H H H H
|
||
X X X HH L H H H H H H HH
|
||
XXXH L H H H HHHHH H
|
||
X X XL H H H H H H HHHH
|
||
X X X HHH·H H H HHH H H
|
||
5-148
|
||
|
||
===PAGE 219===
|
||
SCHOTTKY BIPOLAR 8205
|
||
APPLICATIONS OFTHE8205
|
||
The8205canbeusedinawidevarietyofapplications in
|
||
microcomputer systems. I/Oportscanbedecoded fromthe
|
||
addressbus,chipselectsignalscanbegenerated toselect
|
||
memory devicesandthetypeofmachine statesuchasin
|
||
8008systemscanbederivedfromasimpledecoding ofthe
|
||
statelines(SO,S1,S2)ofthe8008CPU.
|
||
I/OPortDecoder
|
||
Showninthefigurebelowisatypicalapplication ofthe
|
||
8205.Address inputlinesaredecoded byagroupof8205s
|
||
(3).Eachinputhasabinaryweight.Forexample, AOisas
|
||
signedavalueof1andistheLSB;A4isassigned avalueof
|
||
16andistheMSB.Byconnecting themtothedecoders as
|
||
shown,anactivelowsignalthatisexclusive innatureand
|
||
represents thevalueoftheinputaddresslines,isavailable at
|
||
theoutputsofthe8205s.
|
||
Thiscircuitcanbeusedtogenerate enablesignalsforI/O
|
||
portsoranyotherdecoder relatedapplication.
|
||
Notethatnoexternal gatingisrequired todecodeupto24
|
||
exclusive devicesandthatasimpleaddition ofaninverter
|
||
ortwowillallowexpansion toevenlargerdecoder net
|
||
works.rayof8205scanbeusedtocreateasimpleinterface toa
|
||
24Kmemory system.
|
||
Thememory devicesusedcanbeeitherROMorRAMand
|
||
are1Kinstoragecapacity. 8308sand8102sarethedevices
|
||
typically usedforthisapplication. Thistypeofmemory de
|
||
vicehasten(10)addressinputsandanactive"low"chip
|
||
select(CS).ThelowerorderaddressbitsAO-A9whichcome
|
||
fromthemicroprocessor are"bussed" toallmemory ele
|
||
mentsandthechipselecttoenableaspecificdeviceorgroup
|
||
ofdevicescomesfrom t~earrayof8205s.Theoutputof
|
||
the8205isactivelowsoitisdirectlycompatible withthe
|
||
memory components.
|
||
Basicoperation isthattheCPUissuesanaddresstoidentify
|
||
aspecificmemory location inwhichitwishesto"write"or
|
||
"read"data.Themostsignificant addressbitsA1O-A14are
|
||
decoded bythearrayof8205sandanexclusive, activelow,
|
||
chipselectisgenerated thatenablesaspecificmemory de
|
||
vice.Theleastsignificant address bitsAO-A9identify a
|
||
specific location withintheselected device.Thus,allad:
|
||
dressesthroughout theentirememory arrayareexclusive
|
||
innatureandarenon-redundant.
|
||
Thistechnique canbeexpanded almostindefinitely tosup
|
||
portevenlargersystemswiththeaddition ofafewinverters
|
||
andanextradecoder (8205).
|
||
:>~~MORIES
|
||
Ao ~
|
||
A, 0, CS,
|
||
A2CS2
|
||
CS3
|
||
8205
|
||
CS4
|
||
~ CSs
|
||
E; CS6
|
||
E3 CS;
|
||
Ao cs;
|
||
A, csg
|
||
A2 CS,o
|
||
CSllCHIP8205
|
||
CS'2SELECTS
|
||
~CSt3
|
||
e; CS'4
|
||
E3 ~
|
||
Ao CS'6
|
||
A, ~CS17
|
||
A2 CS'8
|
||
CS'9
|
||
8205
|
||
CS20
|
||
e; CS2,
|
||
e; CS22
|
||
E3CS23A,O----~......-.-I
|
||
All----.-..-t--I
|
||
A'2---""-'+--+---4
|
||
24KMemory InterfaceAo-Ag''- _
|
||
fo
|
||
fi
|
||
PORT
|
||
1"2NUMBERS
|
||
13
|
||
14GND
|
||
15
|
||
i6
|
||
17
|
||
is
|
||
f9
|
||
20
|
||
21
|
||
22
|
||
23ChipSelectDecoder
|
||
UsingaverysimilarcircuittotheI/Oportdecoder, anar-
|
||
Ao Ao °0
|
||
A, A, 0,
|
||
A2A2 °2
|
||
°3
|
||
8205
|
||
°4
|
||
A3 E; Os
|
||
A4 E2
|
||
EN E3
|
||
Ao °0
|
||
A, 0,
|
||
A2 °2
|
||
°3
|
||
8205
|
||
°4
|
||
E; °5
|
||
EN~ °6
|
||
E3
|
||
Ao
|
||
A, 0,
|
||
A2 °2
|
||
°3
|
||
8205
|
||
°4
|
||
~ °5
|
||
ENE2 °6
|
||
E3°7
|
||
I/OPortDecoder
|
||
5-149
|
||
|
||
===PAGE 220===
|
||
SCHOTTKY BIPOLAR 8205
|
||
LogicElement Example
|
||
Probably themostoverlooked application ofthe8205is
|
||
thatofageneralpurposelogicelement. Usingthelion-chip"
|
||
enablinggate,the8205canbe configu redtogate itsde
|
||
codedoutputs withsystemtimingsignalsandgenerate
|
||
strobesthatcanbedirectlyconnected tolatches,flip-flops
|
||
andone-shots thatareusedthroughout thesystem.
|
||
Anexcellent example ofsuchanapplicationisthe"state
|
||
decoder" inan8008CPUbasedsystem.The8008CPUis
|
||
suesthreebitsofinformation (SO,S1,S2)thatindicatethe
|
||
natureofthedataontheDataBusduringeachmachine
|
||
state.Decoding ofthesesignalsisvitaltogenerate strobes
|
||
thatcanloadtheaddresslatches,controlbusdiscipline and
|
||
generalmachine functions.
|
||
Inthefigurebelowacircuitisshownusingthe8205asthe
|
||
"statedecoder" foran8008CPUthatnotonlydecodesthe
|
||
SO,51,52outputsbutgatesthesesignalswiththeclock
|
||
(phase2)andtheSYNCoutputofthe8008CPU.TheT1andT2decoded strobescanconnectdirectlytodeviceslike
|
||
8212sforlatching theaddressinformation. Theotherde
|
||
codedstrobescanbeusedtogenerate signalstocontrolthe
|
||
systemdatabus,memory timingfunctions andinterrupt
|
||
structure. RESET isconnected totheenablegatesothat
|
||
strobesarenotgenerated duringsystemreset,eliminating
|
||
accidental loading.
|
||
Thepowerofsuchacircuitbecomes evidentwhenasingle
|
||
decoded strobeislogically brokendown.Consider T1out
|
||
put,thebooleanequation foritwouldbe:
|
||
Tl=(SO·S1·S2)"(SYNC·Phase 2·Reset)
|
||
AsixinputNANDgateplusafewinverters wouldbeneed
|
||
edtoimplement thisfunction. Thesevenremaining outputs
|
||
wouldneedasimilarcircuittoduplicate theirfunction,
|
||
obviously asubstantial savings incomponents canbe
|
||
achieved whenusingsuchatechnique.
|
||
STOPT3II-----i+----+-I
|
||
I'----++-------tM---~1
|
||
I I I I
|
||
I I I I1 I
|
||
6\lJI IIII I
|
||
- I 1 I2~ IIIi I
|
||
4"----.....,~r----+I---+I--t-I -""'"""I""'"--Ito Iro----++-----:I--+---..-I------~\lJ II I
|
||
l------------,.wr----+\--:....1 ---+-1
|
||
3"---------------,JJ,.--+-I ----.....17----------------,1 I
|
||
5 w--r'illOUTPUTS
|
||
FROM
|
||
8205820~32S13o
|
||
S12,
|
||
S1128008
|
||
CPU
|
||
SYSTEM RESET
|
||
StateControlCoding
|
||
SoS,S2STATE
|
||
010T1
|
||
011T11
|
||
0a1T2a0 0 WAIT
|
||
10 0 T3
|
||
110STOP
|
||
11 1 T4
|
||
101T5
|
||
5-150
|
||
|
||
===PAGE 221===
|
||
SCHOTTKY BIPOLAR 8205
|
||
ABSOLUTE MAXIMUM RATINGS·
|
||
Temperatu reUnderBias:Ceramic
|
||
Plastic
|
||
StorageTemperature
|
||
AllOutputorSupplyVoltages
|
||
AllInputVoltages
|
||
OutputCurrents-65°Cto+125°C
|
||
-65°Cto+75°C
|
||
-65°Cto+1600C
|
||
-0.5to+7Volts
|
||
-1.0to+5.5Volts
|
||
125rnA*COMMENT
|
||
Stressesabovethoselistedunder"Absolute Maximum Rat
|
||
ing"maycausepermanent damagetothedevice.Thisisastress
|
||
ratingonlyandfunctional operation ofthedeviceattheseorat
|
||
anyothercondition abovethoseindicated intheoperational
|
||
sectionsofthisspecification isnotimplied.Exposure toabsolute
|
||
maximum ratingconditions forextended periodsmayaffect
|
||
devicereliability.
|
||
D.C.CHARACTERISTICS TA=OOCto+75°C,Vee=5.0V±5%
|
||
8205
|
||
SYMBOL PARAMETERLIMITUNIT TESTCONDITIONSMIN. MAX.
|
||
IF INPUTLOADCURRENT -0.25 rnA Vee=5.25V,VF=0.45V
|
||
'RINPUTLEAKAGE CURRENT 10 ~A Vee=5.25V,VR=5.25V
|
||
VeINPUTFORWARD CLAMPVOLTAGE -1.0 V Vee=4.75V,Ie=-5.0rnA
|
||
VOLOUTPUT "LOW"VOLTAGE 0.45 V Vee=4.75V,IOl=10.0rnA
|
||
VOHOUTPUT HIGHVOLTAGE 2.4 V Vee=4.75V,IOH=-1.5rnA
|
||
V1lINPUT"LOW"VOLTAGE 0.85 V Vee=5.0V
|
||
V'HINPUT"HIGH" VOLTAGE 2.0 V Vee=5.0V
|
||
'seOUTPUT HIGHSHORT -40 -120 rnA Vee=5.0V,VOUT=OV
|
||
CIRCUIT CURRENT
|
||
VoxOUTPUT "LOW"VOLTAGE 0.8 V Vee=5.0V,lox=40rnA
|
||
@HIGHCURRENT
|
||
'eePOWERSUPPLY CURRENT 70 rnA Vee=5.25V
|
||
TYPICAL CHARACTERISTICS
|
||
I I
|
||
Vee::;:5.0V--
|
||
-..... TA-OOC
|
||
\~f\<
|
||
TA=2SoC-rl--..\~
|
||
TA::;:75OC_~\,\
|
||
\\\
|
||
1\1\,
|
||
\."-~DATATRANSFER FUNCTION
|
||
o
|
||
o.2.4.6 .8 1.01.21.41.61.82.0
|
||
INPUTVOLTAGE (V)5.0
|
||
4.0
|
||
~
|
||
w
|
||
~3.0::{...
|
||
...Ja>...2.0~
|
||
4-...
|
||
::::>a
|
||
1.0
|
||
5.0 1.0 2.0 3.0 4.0
|
||
OUTPUT "HIGH" VOLTAGE (V)OUTPUT CURRENT VS.
|
||
OUTPUT "HIGH" VOLTAGE
|
||
III~I(---vee=s.ovIfIt~II.........TA::;:25°C
|
||
TA::;:O°C-nrt"TA::;:75°C
|
||
I
|
||
~,
|
||
I,
|
||
I
|
||
I
|
||
Ao
|
||
-10
|
||
-50
|
||
o<.§.
|
||
~-20
|
||
wa:a:
|
||
~
|
||
~-30
|
||
~
|
||
4...
|
||
~
|
||
a-40
|
||
1.0 .2 .4 .6 .8
|
||
OUTPUT "LOW"VOLTAGE (V)0I000o-............... --1000..........----'-''''''---..1--'''''----1..----1
|
||
o100--.....,....----~.....--....-------OUTPUT CURRENT VS.
|
||
OUTPUT IILOW"VOLTAGE
|
||
80t---+--+---+---+-----Ir----+---+---:.~--#-----t«
|
||
.§.
|
||
...z60t---t-----t---+---+---f~oII--_+__-f---+-~
|
||
U.la:a:
|
||
::>
|
||
(.)
|
||
...40t----+--f---+--+-""""*"if---+---+---+----+-----4
|
||
::>
|
||
~...
|
||
::>o
|
||
20t---t---+---JT-~----lf---+---+-----+----+-----t
|
||
5-151
|
||
|
||
===PAGE 222===
|
||
SCHOTTKY BIPOLAR 8205
|
||
8205SWITCHING CHARACTERISTICS
|
||
CONDITIONS OFTEST: TESTLOAD:
|
||
Inputpulseamplitudes: 2.5V
|
||
Inputriseandfalltimes:5nsec
|
||
between 1Vand2V
|
||
Measurements aremadeat1.5V390n
|
||
2K
|
||
AllTransistors 2N2369 orEquivalent. eL=30pF
|
||
---..1'1 1'---___
|
||
_____~__t+_-_'....t++I-: =b~:.:~-I.-,..--------
|
||
I , , , ,
|
||
OUTPUTADDRESS ORENABLE
|
||
INPUTPULSETESTWAVEFORMS
|
||
A.C.CHARACTERISTICS TA=aocto+75°C,Vee=5.0V±5%unlessotherwise specified.
|
||
SYMBOL PARAMETER MAX.LIMIT UNIT TESTCONDITIONS
|
||
t++ 18 ns
|
||
t_+ ADDRESS ORENABLE TO 18 ns
|
||
t+_OUTPUT DELAY18 ns
|
||
t--18 ns
|
||
C,N(1;INPUTCAPACITANCE P8205 4(typ.) pF f=1MHz,Vee=OV
|
||
C8205 5(typ.) pF VSIAS=2.0V,TA::250e
|
||
1.Thisparameter ispenodically sampled andisnot100%tested.
|
||
TYPICAL CHARACTERISTICS
|
||
ADDRESS ORENABLE TOOUTPUT
|
||
DELAYVS.LOADCAPACITANCEADDRESS ORENABLE TOOUTPUT
|
||
DELAYVS.AMBIENT TEMPERATURE
|
||
20,....-..-------~--........------ 20,....-..---...,....-----,-----
|
||
Vee=5.0V
|
||
Cl=30pf
|
||
o15t------+ ----~I--------I
|
||
1-- 1 WIII
|
||
~..:. ~ t~_..:.~:.. _
|
||
~~ t_+ I
|
||
w..J
|
||
~~10
|
||
~5wCL
|
||
~50°«51------+------+------1Vee=5.0V
|
||
TA=25"C
|
||
~_15~----+
|
||
~Cm-
|
||
~~
|
||
~g10t------+---+----+:::-...-=:;;---4oI- \...",
|
||
~~
|
||
~5
|
||
00«51------1----+-----+-----1
|
||
75 25 SO
|
||
AMBIENT TEMPERATURE (OC)OL..-----....L.....------'-------
|
||
o 200 50 100 150
|
||
LOADCAPACITANCE (pf)ol-.-__ ..L..-__ ..1--__ .......I...-__ ~
|
||
o
|
||
5-152
|
||
|
||
===PAGE 223===
|
||
Schottky Bipolar8214
|
||
PRIORITY INTERRUPT CONTROL UNIT
|
||
•EightPriorityLevels
|
||
•CurrentStatusRegister
|
||
•PriorityComparator•FullyExpandable
|
||
•HighPerformance (50ns)
|
||
•24-PinDualIn-LinePackage
|
||
The8214isaneightlevelpriorityinterrupt controlunitdesignedtosimplifyinterrupt drivenmicrocomputer
|
||
systems.
|
||
ThePICUcanaccepteightrequesting levels;determine thehighestpriority, compare thisprioritytoasoft
|
||
warecontrolled currentstatusregisterandissueaninterrupt tothesystemalongwithvectorinformation to
|
||
identifytheserviceroutine.
|
||
The8214isfullyexpandable bytheuseofopencollector interrupt outputandvectorinformation. Control
|
||
signalsarealsoprovided tosimplifythisfunction.
|
||
ThePICUisdesigned tosupportawidevarietyofvectored interrupt structures andreducepackagecount
|
||
ininterrupt drivenmicrocomputer systems.
|
||
PINCONFIGURATION LOGICDIAGRAM
|
||
[TI>ElR
|
||
Bo24Vee[}DETlG--
|
||
REQUEST ACTIVITY
|
||
B,2 23ECSl!PRo(OPENCOllECTOR)
|
||
B23 22R7 ~R,
|
||
~[DITI>R;
|
||
SGS 4 21R6 ~R;~CD
|
||
INT 5 20Rs[1D~~~A2
|
||
elK 6 19R4 ~~}A8214
|
||
INTE 18R3~~
|
||
Ao8 17R2A>B
|
||
IT> 60
|
||
}BA,9 16R, ED ~
|
||
A210 15Ro[I>S;
|
||
EDSGS PRIORITY
|
||
COMPARATORElR 11 14ENLG~ECS
|
||
GND 12 13ETLG
|
||
PINNAMESIT>INTE------------~
|
||
[]>ClK-------------~
|
||
INPUTS
|
||
Ro·R7 REQUEST LEVELS (R7HIGHEST PRIORITY)
|
||
Bo·B2 CURRENT STATUS
|
||
SGS STATUSGROUPSELECT
|
||
ECS ENABLE CURRENT STA"fUS
|
||
INTE INTERRUPT ENABLE
|
||
CLK CLOCK(tNTF·F)
|
||
ELR ENABLE LEVELREAD
|
||
E1'\.G ENABLE THISLEVELGROUP
|
||
OUTPUTS:
|
||
Ao·A2 REQUEST LEVELSJ-OPEN
|
||
INT INTERRUPT (ACT.LOW) COLLECTOR
|
||
ENLG ENABLE NEXTLEVELGROUP
|
||
5-153
|
||
|
||
===PAGE 224===
|
||
SCHOTTKY BIPOLAR 8214
|
||
INTERRUPTS INMICROCOMPUTER SYSTEMS
|
||
Microcomputer systemdesignrequiresthatI/Odevicessuch
|
||
askeyboards, displays, sensorsandothercomponents re
|
||
ceiveservicing inanefficient methodsothatlargeamounts
|
||
ofthetotalsystems taskscanbeassumed bythemicro
|
||
computer withlittleornoeffectonthroughput.
|
||
Themostcommon methodofservicing suchdevicesisthe
|
||
Polledapproach. Thisiswheretheprocessor musttesteach
|
||
deviceinsequence andineffect"ask"eachoneifitneeds
|
||
servicing. Itiseasytoseethatalargeportionofthemain
|
||
program isloopingthrough thiscontinuence pollingcycle
|
||
andthatsuchamethodwouldhaveaserious,detrimental
|
||
effectonsystemthroughput thuslimitingthetasksthat
|
||
couldbeassumed bythemicrocomputer andreducing the
|
||
costeffectiven.ess ofusingsuchdevices.
|
||
Amoredesireable methodwouldbeonethatwouldallow
|
||
themicroprocessor tobeexecuting itsmainprogram and
|
||
onlystoptoserviceperipheral deviceswhenitistoldtodo
|
||
sobythedeviceitself.Ineffect,themethodwouldprovide
|
||
anexternal asynchronous inputthatwouldinformthe
|
||
processor thatitshouldcompiete whatever instruction that
|
||
iscurrently beingexecuted andfetchanewroutinethat
|
||
willservicetherequesting device.Oncethisservicing iscom
|
||
pletehowever theprocessor wouldresumeexactlywhereit
|
||
leftoff.
|
||
Thismethod iscalledInterrupt. Itiseasytoseethatsystem
|
||
throughput woulddrastically increase, andthusmoretasks
|
||
couldbeassumed bythemicrocomputer tofurtherenhance
|
||
itscosteffectiveness.
|
||
ThePriority Interrupt Control Unit(PICU)functions asan
|
||
overallmanager inanInterrupt-Driven systemenvironment.
|
||
Itacceptsrequests fromtheperipheral equipment, determ
|
||
ineswhichoftheincoming requests isofthehighestim
|
||
portance (priority), ascertains whether theincoming request
|
||
hasahigherpriority valuethanthelevelcurrently being
|
||
serviced andissuesanInterrupt totheCPUbasedonthis
|
||
determination.
|
||
Eachperipheral devi~eorstructure usuallyhasaspecial
|
||
program or"routine" thatisassociated withitsspecific
|
||
functional oroperational requirements; thisisreferredto
|
||
asa"service routine". ThePICU,afterissuinganInterrupt
|
||
totheCPU,mustsomehow inputinformation intotheCPU
|
||
thatcan"point" theProgram Countertotheservicerou
|
||
tineassociated withtherequesting device.ThePICUen
|
||
codestherequesting levelintosuchinformation foruseas
|
||
a"vector" tothecorrectInterrupt ServiceRoutine.
|
||
5-154RAM
|
||
ROM
|
||
PolledMethod
|
||
RAM
|
||
ROM
|
||
Interrupt MethodCPU
|
||
CPU INTCPU·DRIVEN
|
||
MULTIPLEXOR
|
||
--"""'""
|
||
|
||
===PAGE 225===
|
||
SCHOTTKY BIPOLAR 8214
|
||
FUNCTIONAL DESCRIPTION
|
||
General
|
||
'he8214isadevicespecifically designed foruseinreal
|
||
time,interrupt driven,microcomputer systems. Basically it
|
||
isaneight(8)levelprioritycontrolunitthatcanaccept
|
||
eightdifferent interrupt requests, determine whichhasthe
|
||
highestpriority,compare thatleveltoasoftware maintained
|
||
currentstatusregisterandissueaninterrupt tothesystem
|
||
basedonthiscomparison alongwithvectorinformation to
|
||
indicatethelocationoftheserviceroutine.
|
||
PriorityEncoder
|
||
Theeightrequests inputs,whichareactivelow,comeinto
|
||
thePriorityEncoder. Thiscircuitdetermines whichrequest
|
||
inputisthemostimportant (highestpriority) aspreassigned
|
||
bythedesigner. (R7)isthehighestpriority inputtothe
|
||
8214and(RO)isthelowest.ThelogicofthePriority En
|
||
coderissuchthatiftwoormoreinputlevelsarriveatthe
|
||
sametimethentheinputhavingthehighestprioritywilltake
|
||
presidence andathreebitoutput,corresponding totheact
|
||
ivelevel(modulo 8)willbesentout.ThePriorityEncoder
|
||
alsocontains alatchtostoretherequest input. Thislatchis
|
||
controlled bytheInterrupt DisableFlip-flop sothatonce
|
||
aninterrupt hasbeenissuedbythe8214therequestlatch
|
||
isnolongeropen.(Notethatthelatchdoesnotstoreinact
|
||
iverequests. Inorderforarequesttobemonitored bythe
|
||
8214itmustremainpresentuntilithasbeenserviced.)
|
||
CurrentStatusRegister
|
||
Inaninterrupt drivenmicrocomputer systemitisimportant
|
||
tonotonlyprioritize incomingrequests buttoascertain
|
||
whethersucharequestisahigherprioritythantheinterrupt
|
||
currently beingserviced.
|
||
TheCurrent StatusRegister isasimple4-bitlatchthatis
|
||
treatedasanaddressable outport portbythemicrocom
|
||
putersystem. ItisloadedwhentheECSinputgoeslow.
|
||
Maintenance oftheCurrentStatusRegister isperformed as
|
||
aportionoftheserviceroutine.Basically, whenaninterrupt
|
||
isissuedtothesystemtheprogrammer outputs abinary
|
||
code(modulo 8)thatisthecompliment oftheinterrupt
|
||
level.ThisvalueisstoredintheCurrentStatusRegisterand
|
||
iscompared toallfurtherprioritized incoming requests by
|
||
thePriorityComparator. Inessence, acopyofthecurrent
|
||
interrupt leveliswrittenintothe8214tobeusedasaref
|
||
erenceforcomparison. Thereisnorestriction tothismain
|
||
tenance, otherlevelvaluescanbewrittenintothisregister
|
||
asreferences sothatgroupsofinterrupt requests maybe
|
||
disallowed undercomplete controloftheprogrammer.
|
||
5-155NotethatthefourthbitintheregisterisSGS.Thisinputis
|
||
partofthevaluewrittenoutbytheprogrammer andper
|
||
formsaspecialfunction. ThePriorityComparator willonly
|
||
issueanoutputthatindicates therequestlevelisgreaterthan
|
||
theCurrentStatusRegister. Ifbothcomparator inputsare
|
||
equaltozeronooutputwillbepresent. TheSGSinput
|
||
allowstheprogrammer to,ineffect,disablethiscomparison
|
||
andallowthe8214toissueaninterrupt tothesystemthat
|
||
isbasedonlyonthelogicofthepriorityencoder.
|
||
|
||
===PAGE 226===
|
||
SCHOTTKY BIPOLAR 8214
|
||
ControlSignals
|
||
The8214alsohasseveralinputsthatenablethedesignerto
|
||
synchronize theinterrupt issuedtothemicroprocessor and
|
||
toallowordisallow suchanissuance. Also,signalsarepro
|
||
videdthatpermitsimpleexpansion toother8214ssothat
|
||
morethaneightlevelscanbecontrolled.
|
||
INTE,elK
|
||
TheINTE(Interrupt Enable) inputallowsthedesigner to
|
||
"shutoff" theinterrupt systemundercontrolofexternal
|
||
logicorpossibly undersoftware maintenance. A"zero"on
|
||
thislinewillnotallowinterrupts tobeissuedtothemicro
|
||
computer system.
|
||
TheClK(Clock)inputisactually thetriggerthatstrobes
|
||
theInterrupt Flip-Flop. Itcanbeconnected tooneofthe
|
||
clocksofthemicroprocessor sothattheinterrupt issued
|
||
meetstheCPUset-uptimespecification. Notethatdueto
|
||
thegatingoftheinputtotheInterrupt Flip-Flop theINT
|
||
outputwillonlybeactiveforthetimeofasingleclockpe
|
||
riod,soexternal latching mayberequired toholdthissig
|
||
nal.
|
||
ElR,ETlG,ENGl
|
||
Thesethreesignalsallow8214stobecascaded sothatmore
|
||
thaneightlevelsofinterrupt requests canbecontrolled.
|
||
Basically, theENLGoutputofone8214isconnected to
|
||
theETLGinputofthenextandsoon,withthefirst8214
|
||
havingitsETLGinputpulled"high"andassigned thehigh
|
||
estpriority. WhentheENlGoutputis"high"itindicates
|
||
thatthereisnointerrupt pending onthatdeviceandthat
|
||
interrupts canbemonitored onthenextlowerpriority
|
||
8214.
|
||
This"cascading" canbeexpanded almostindefinitely to
|
||
accomodate eventhelargestofinterrupt drivensystem
|
||
architectures.
|
||
AO,A1,A2
|
||
Inordertoidentify whichdevicehasinterrupted thepro
|
||
cessorsothattheserviceroutineassociated withitcanbe
|
||
addressed, apointeror"vector" mustaccompany theinter
|
||
ruptissuedtothemicrocomputer system.
|
||
TheAD,A1andA2outputs represent thecomplement of
|
||
theactiveinterrupt level(modulo 8).Byusingthesesignals
|
||
toencodethespecialinstruction, RST,theprogram counter
|
||
ofthemicroprocessor, canpointtothelocation ofthe
|
||
serviceroutine. Notethatthesethreeoutputs aregatedby
|
||
theELRinputandareopencollector sothatexpansion is
|
||
simplified.INT
|
||
TheINToutputofthe8214isthesignalthatisissuedto
|
||
themicroprocessor toinitiatetheinterrupt sequence. As
|
||
soonaINTisactivetheINTDISFFisset,inhibiting further
|
||
requests fromentering theRequest Latch.Onlythewriting
|
||
outofthecurrentstatusinformation bystrobing theECS
|
||
inputwillcleartheINTDISFFandallowrequeststoenter
|
||
thelatch.
|
||
NotethatINTisalsoopencollector sothatwhencascaded
|
||
toother8214saninterrupt inanyoftheactivedeviceswill
|
||
setalllNTDISFFsintheentirearray.
|
||
5-156
|
||
|
||
===PAGE 227===
|
||
SCHOTTKY BIPOLAR 8214
|
||
APPLICATIONS OFTHE8214
|
||
8LevelController (8080)
|
||
Themostcommon ofapplications ofthe8214isthatofan
|
||
eightlevelprioritystructure for8080or8008microcom
|
||
putersystems.
|
||
Showninthefigurebelowisadetailed logicschematic ofa
|
||
simplecircuitthatwillaccepteightinputrequests, maintain
|
||
currentstatus,issuetheinterrupt signaltothe8080anden
|
||
codetheproperRSTinstruction togateontothedatabus.
|
||
Theeightrequests areconnected tothe8214bythede
|
||
signerinwhatever orderofpriority istobepreassigned. For
|
||
example, eightkeyboards couldbemonitored andeachas
|
||
signedadegreeofimportance (levelofpriority) sothat
|
||
fasterprocessor attention oraccesscanbeassignedtothe
|
||
criticalortimedependent tasks.
|
||
TheinputstotheCurrentStatusRegisterareconnected to
|
||
theDataBussothatdatacanbewrittenoutintothis"port".
|
||
An8212isusedtoencodetheRSTinstruction andalsoto
|
||
actasa3-stategatetoplacetheproperRSTinstruction
|
||
whenthe8080DataBusisintheinputmode.Notethatthe
|
||
INTsignalfromthe8214islatchedintheSRflip-flop of
|
||
the8212sothatpropertimingismaintained. The8212is
|
||
selected (enabled) whentheINTAsignalfromthe8080
|
||
statuslatchandtheDBINfromthe8080areactive,thisas
|
||
suresthattheRSTinstruction willbeplacedontheData
|
||
Busatthepropertime.NotethattheINToutputfromthe
|
||
8212isinverted andpulledupbeforeitisconnected tothe
|
||
8080.Thisistogenerate anINTsignaltothe8080thathas
|
||
thecorrectpolarity andmeetstheinputvoltagerequire
|
||
ment(3.3V).BasicOperation
|
||
Whentheinitialinterrupt requestispresented tothe8214
|
||
itwillissueaninterrupt tothe8080ifthestructure isen
|
||
abled.The8214willencodetherequestinto3bits(modulo
|
||
8)andoutputthemtothe8212.Aftertheacknowledge
|
||
mentoftheinterrupt hasbeenissuedbythe8080theen
|
||
codedRSTinstruction isgatedontotheDataBusbythe
|
||
8212.Theprocessor executes theinstruction andpointsthe
|
||
program counter tothedesiredserviced routine. Inthis
|
||
routinetheprogrammer willprobably savethestatusofthe
|
||
registerarrayandflagswithinaseriesofPUSHinstructions
|
||
(4).Thenacopyofthecurrentinterrupt level(modulo 8)
|
||
canbe"built"intheAccumulator andoutputtotheCur
|
||
rentStatusRegister ofthe8214foruseasacomparison
|
||
reference forallfurtherincoming requests tothesystem.
|
||
ThisVectored EightLevelPriority Interrupt Structure for
|
||
8080microcomputer systems isapowerful yetflexiblecir
|
||
cuitthatishighperformance andhasaminimalcomponent
|
||
count.
|
||
IPRIORITYRST1 1A2AlAo1 1 1REQUEST
|
||
LOWEST 0 7 1 1 1 1 1 1 1 1
|
||
161111 0 111
|
||
251110 1 111
|
||
341110 0 111
|
||
43 1 1 0 1 11 1 1
|
||
52 1 1 010111
|
||
61 1 10 0 1 1 11
|
||
HIGHEST 7-0110 0 0 1 1 1
|
||
-RST0WILLVECTOR PROGRAM COUNTER TOLOCATIONo(ZERO)ANDINVOKE THESAMEROUTINE AS"RESET"
|
||
INPUTTO8080.
|
||
THISCOULDRE·INITlALIZE THESYSTEM BASEDONTHE
|
||
ROUTINE INVOKED.
|
||
(ACAUTION TOSYSTEM PROGRAMMERS.)
|
||
8080BI-DIRECTIONAL BUS
|
||
14)Vee
|
||
A6 1K><C:1K >10K
|
||
ClK>
|
||
7INTE INTb5 11INT....23STB 'J INT
|
||
(8080PIN
|
||
8212
|
||
15_
|
||
~ ~ Do 000...!....-
|
||
'6~Fr.; ~ 01 0°16
|
||
17~ ~8
|
||
18:::R2AQ",8 9O200210
|
||
19~AiAi....9 1603 00315
|
||
20~R;
|
||
~10 1804 0°417
|
||
21....R5 Ai~05 0°519
|
||
22;::R68214 ~06 0°621R7 07 0°7
|
||
ETlG13 11-ClR....
|
||
~~ DS2MDOSl
|
||
3....S;
|
||
11312014~B2
|
||
....SGSGND
|
||
E23....NT ....ECS
|
||
S
|
||
DECODER)ElR
|
||
1~1INTAENABl
|
||
CURRE
|
||
STATU
|
||
(FROMI/OPORTREQUESTSINTErj>2(TTL)
|
||
GND
|
||
8LevelController
|
||
5-157
|
||
|
||
===PAGE 228===
|
||
SCHOTTKY BIPOLAR 8214
|
||
DO 8080BI-olRECTIONAL BUS
|
||
~ ~
|
||
~ ~
|
||
~ ~
|
||
~ ~
|
||
0
|
||
5T 04
|
||
~ I T ~
|
||
~ IIT ~
|
||
I I I T 07
|
||
~10Kmmn ~
|
||
INTp23I I I I I I I I c4> '(808~Np1N 14)1K~~~:
|
||
INTE •I I I I • I 7IINTE~2(TIL) •I I I I ,6clClKETLGINTI:>5I I I ~b 11ISTB
|
||
PRIORITY
|
||
ARRAYEN
|
||
(FROMI/OPORT
|
||
DECODER)GND :Do
|
||
0,
|
||
7 092
|
||
16~38212
|
||
1804
|
||
205
|
||
2206
|
||
07
|
||
RESET 14CLR
|
||
oS2Moos,ffl1
|
||
I/ORGNDAO~Ai9
|
||
A210
|
||
8214
|
||
~GND
|
||
~ 13 7ClKETlG
|
||
INTE -p5
|
||
1~ INT
|
||
,~~~
|
||
17~R,
|
||
1B~R2
|
||
"'::lIRi~~ 7n::3R'4 A 9
|
||
21~R6J!10
|
||
?~~ 8214 2
|
||
~~
|
||
3~
|
||
4 B2~
|
||
2~.....-1ECS
|
||
ErR ENLG~
|
||
GND~ECSmJ-
|
||
2~
|
||
3~4if;sPRsPFlg
|
||
f5Rl0
|
||
PAll
|
||
PR12PR13PR14
|
||
PA15
|
||
PRO
|
||
Pfil
|
||
fiR2
|
||
PR3PR4PA5PR6
|
||
PR7
|
||
ENABLE
|
||
CURRENT
|
||
STATUS 2------~l-
|
||
(FROMI/OPORT
|
||
DECODER)ENABLE
|
||
CURRENT
|
||
STATUS 1
|
||
(FROMI/OPORT
|
||
DECODER)REQUESTS
|
||
16LevelController
|
||
5-158
|
||
|
||
===PAGE 229===
|
||
SCHOTTKY BIPOLAR 8214
|
||
APPLICATIONS OFTHE8214
|
||
Cascading the8214
|
||
Whengreaterthaneightlevelsofinterrupts mustbepriori
|
||
tizedandserviced, the8214canbecascaded withother
|
||
8214stosupportsuchan.architecture.
|
||
Ontheprevious pageasimplecircuitisshownthatcancon
|
||
trol16levelsofinterrupt andiseasilyexpandable tosup
|
||
portupto40levelsofinterrupt byjustcascading more
|
||
8214s.
|
||
Asdescribed previously, therearesignalsprovided inthe
|
||
8214forcascading (ELR,ETLG,ENLG)andineffectthe
|
||
ENLGoutputofthefirst8214"ripples" downtothenext
|
||
andsoon.Theentirearrayof8214sregardless ofsize,can
|
||
bethought ofasasingleprioritycontrolunit,withthefirst
|
||
havingthehighestpriorityandthenext8214havingalower
|
||
priorityandsoon.
|
||
Inthisapplication, themannerinwhichsoftware handles
|
||
theservicing oftheinterrupt willchange.Sincemorethan
|
||
eightvectorsmustbegenerated amethod otherthanthe
|
||
common RSTinstruction mustbeimplemented. Basically,
|
||
thepriority controlarraymustsomehow modifythecon
|
||
tentsofthe8080Program Counter sothatitcanpoint
|
||
("vector") tooneof16(orhowmanylevelsaretobe
|
||
serviced) andfetchtheproperserviceroutine. Asimpleap-
|
||
proachistotreattheprioritycontrolarrayasasingleinput
|
||
portthatcaninputavalueintotheAccumulator anduse
|
||
thisvalueasanoffsettomodifytheProgram Counter (In
|
||
directJump).
|
||
AninitialCALLisneededtoinvokethisIndirect Jump
|
||
routinesothecircuitry isconfigured toinsertanRST7
|
||
(FFh)forallinterrupts, thustheIndirect JumpRoutine
|
||
startsatlocation (56d).
|
||
TheAssembly Codefortheflowchartisasfollows:RST7
|
||
SAVE
|
||
PROCESSOR
|
||
STATUS
|
||
INPUT
|
||
PRIORITY ARRAY
|
||
VALUE
|
||
LOAD
|
||
BASEVALUE
|
||
INTOHREGISTER
|
||
TRANSFER
|
||
H&LREGISTER
|
||
TOPROGRAM COUNTER
|
||
SERVICE ROUTINE
|
||
IREQUEST (PR)D-78-15--0 0 0PRIORITIES ENENA2A,Ao
|
||
LOWEST 001 1 1 1 000
|
||
1011 1 00 0 0
|
||
2011010 0 0
|
||
301 1 0 0 000
|
||
4010110 0 0
|
||
50 1 0 1 0000
|
||
601001000
|
||
701000 0 0 0
|
||
8 1 0 1 1 1000
|
||
9 1 01 1 0 0 0 0
|
||
1010101000
|
||
111010 0 0 0 0
|
||
12100 1 1000
|
||
1310 0 1 0 000
|
||
141000100 0
|
||
HIGHEST 15100 0 0 0 0 0
|
||
(Theexecution timeforthetotalroutine is35.5micro
|
||
secondsbasedonan8080clockperiodof500ns.)
|
||
Following isabasicflowchart ofthepriorityarrayIndirect
|
||
Jumproutine. Notethatthelaststepintheroutine will
|
||
vectortheprocessor tofetchtheproperserviceroutineas
|
||
dictated bytheinterrupting level.PUSH
|
||
PUSH
|
||
PUSH
|
||
PUSH
|
||
IN
|
||
MOV
|
||
MVI
|
||
PCHL:SW} (saveprocessor status)
|
||
o (22microseconds)
|
||
H
|
||
(n) (inputPriorityArrayValue)
|
||
L,A (transfer Accumulator toLregister)
|
||
H,(n) (loadBaseAddress intoHregister)
|
||
(transfer H&LtoProgram Counter)Showninthefigureaboveisachartofthe16different array
|
||
valuesthatareusedtooffsettheProgram Counter andvec
|
||
tortotheproperserviceroutine. Thesevaluesaretheones
|
||
thatareloadedintotheilL"register; thevalueloadedinto
|
||
the"H"registerwithan"immediate instruction" isusedto
|
||
identify themajorareaofmemory wheretheservicerou
|
||
tinesarestored,similartoa"coursesetting" andthevalue
|
||
intheilL"register isusedtoidentify aspecific location,
|
||
similartoa"finesetting".
|
||
NotethatDO,01,andD2arealwayssetto"zero",thispro
|
||
videstheprogrammer eight(8)memory locations between
|
||
thestartofeachserviceroutinesothatmaintenance ofthe
|
||
associated CurrentStatusRegister andaJUMPorCALLin
|
||
struction canbeimplemented.
|
||
Thismethodofinterrupt controlcanbealmostindefinitely
|
||
expanded andprovides thesystemdesigner withapowerful
|
||
tooltoenhance totalsystemthroughput.
|
||
5-159
|
||
|
||
===PAGE 230===
|
||
SCHOTTKY BIPOLAR 8214
|
||
D.C.ANDOPERATING CHARACTERISTICS
|
||
ABSOLUTE MAXIMUM RATINGS*
|
||
Temperature UnderBias O°Cto70°C
|
||
StorageTemperature -65°Cto+150°C
|
||
AllOutputandSupplyVoltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..-0.5Vto+7V
|
||
AllInputVoltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..-1.0Vto+5.5V
|
||
OutputCurrents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..100rnA
|
||
*COMMENT: Stressesabovethoselistedunder"Absolute Maximum Rating"maycausepermanent damagetothedevice.Thisisastressrating
|
||
onlyandfunctional operation ofthedeviceattheseoratanyothercondition abovethoseindicated intheoperational sectionsofthisspecifi
|
||
cationsisnotimplied.Exposure toabsolute maximum ratingsforextended periodsmayaffectdevicereliability.
|
||
Symbol ParameterLimitsUnit ConditionsMin.Typ.£1] Max.
|
||
Vc InputClampVoltage(allinputs) -1.0 VIc=-5mA
|
||
IF InputForwardCurrent: ETLGinput -.15 -0.5rnAVF=0.45V
|
||
allotherinputs -.08 -0.25 rnA
|
||
IR InputReverseCurrent: ETLGinput 80IlAVR=5.25V
|
||
allotherinputs 40IlA
|
||
Vil InputLOWVoltage: allinputs 0.8 VVcc=5.0V
|
||
VIH InputHIGHVoltage: allinputs 2.0 VVcc=5.0V
|
||
Icc PowerSupplyCurrent 90 130rnA SeeNote2.
|
||
Val OutputLOWVoltage: alloutputs .3 .45VIOl=15mA
|
||
VOH OutputHIGHVoltage: ENLGoutput 2.4 3.0 VIOH=-1mA
|
||
los ShortCircuitOutputCurrent: ENLGoutput -20 -35 -55rnAVOs=OV, Vcc=5.0V
|
||
ICEX OutputLeakageCurrent: INTandAo-A2 100IlAVCEx=5.25V
|
||
NOTES:
|
||
1.TypicalvaluesareforTA=25°C,VCC=5.0V.
|
||
2.80-82,SGS,elK,RO-R4grounded, allotherinputsandalloutputsopen.
|
||
5-160
|
||
|
||
===PAGE 231===
|
||
SCHOTTKY BIPOLAR 8214
|
||
A.C.CHARACTERISTICS ANDWAVEFORMS TA=o°cto+70°C,vcc=+5V±5%
|
||
Limits
|
||
Symbol Parameter Min. Typ.[1] Max. Unit
|
||
tCY ClKCycleTime 80 50 ns
|
||
tpw ClK,ECS,INTPulseWidth 25 15 ns
|
||
tlSS INTESetupTimetoClK 16 12 ns
|
||
t,SH INTEHoldTimeafterClK 20 10 ns
|
||
tETCS[2] ETlGSetupTimetoClK 25 12 ns
|
||
tETCH[2] ETlGHoldTimeAfterClK 20 10 ns
|
||
tECCS[2] ECSSetupTimetoClK 80 50 ns
|
||
tECCH[3] ECSHoldTimeAfterClK 0 ns
|
||
tECRS[3] ECSSetupTimetoClK 110 70 ns
|
||
tECRH[3] ECSHoldTimeAfterClK 0
|
||
tECSS[2] ECSSetupTimetoClK 75 70 ns
|
||
tECSH[2] ECSHoldTimeAfterClK 0 ns
|
||
tOCS[2] SGSand80-82SetupTimetoClK 70 50 ns
|
||
tOCH[2] SGSand80-82HoldTimeAfterClK 0 ns
|
||
tRCS[31 Ro-R7SetupTimetoClK 90 55 ns
|
||
tRCH[3] Ro-R7HoldTimeAfterClK 0 ns
|
||
tiCS INTSetupTimetoClK 55 35 ns
|
||
tCI ClKtoINTPropagation Delay 1525 ns
|
||
tRIS[41 Ro-R7SetupTimetoINT 10 0 ns
|
||
tRIH[4] Ro-R7HoldTimeAfterINT 35 20 ns
|
||
tRA Ro-R7toAo·A2Propagation Delay 80100 ns
|
||
tELA ElRtoAo-A2Propagation Delay 4055 ns
|
||
tECA ECStoAo-A2Propagation Delay 100120 ns
|
||
tETA ETlGtoAo-A2Propagation Delay 3570 ns
|
||
tOECS[41 SGSand80-82SetupTimetoECS 15 10 ns
|
||
tOECH[4] SGSand80-82HoldTimeAfterECS 15 10 ns
|
||
tREN Ro-R7toENlGPropagation Delay 4570 ns
|
||
tETEN ETlGtoENlGPropagation Delay 2025 ns
|
||
tECRN ECStoENlGPropagation Delay 8590 ns
|
||
tECSN ECStoENlGPropagation Delay 3555 ns
|
||
CAPACITANCE [5]
|
||
Limits
|
||
Symbol Parameter Min. TypJ1] Max Unit
|
||
C,N InputCapacitance 5 10 pF
|
||
COUT OutputCapacitance 7 12 pF
|
||
TESTCONDITIONS: VBIAS=2.5V,Vce=5V,TA=25°C,f=1MHz
|
||
NOTE5.Thisparameter isperiodically sampledandnot100%tested.
|
||
5·161
|
||
|
||
===PAGE 232===
|
||
SCHOTTKY BIPOLAR 8214
|
||
WAVEFORMS
|
||
ENLG-----------------"'j(-------- -J.\ _
|
||
NOTES:
|
||
(1)TypicalvaluesareforTA=25°C,Vee=5.0V.
|
||
(2)Required forproperoperation ifISEisenabledduringnextclockpulse.
|
||
(3)Thesetimesarenotrequired forproperoperation butfordesiredchangeininterrupt flip-flop.
|
||
(4)Required fornewrequestorstatustobeproperly loaded.
|
||
aUTO-....----.----------.TESTCONDITIONS:
|
||
Inputpulseamplitude: 2.5volts.
|
||
Inputriseandfalltimes:5nsbetween 1and2volts.
|
||
Outputloadingof15rnAand30pf.
|
||
Speedmeasurements takenatthe1.5Vlevels.
|
||
5-162TESTLOADCIRCUIT
|
||
==30pfVee
|
||
)
|
||
300n
|
||
600n
|
||
|
||
===PAGE 233===
|
||
SchottkyBipolar8216/8226
|
||
4BITPARALLEL BIDIRECTIONAL BUSDRIVER
|
||
•DataBusBufferDriverfor8080CPU
|
||
•LowInputLoadCurrent-.25mA
|
||
Maximum
|
||
•HighOutputDriveCapability for
|
||
DrivingSystemDataBus•3.65VOutputHighVoltageforDirect
|
||
Interface to8080CPU
|
||
•ThreeStateOutputs
|
||
•Reduces SystemPackage Count
|
||
The8216/8226 isa4-bitbi-directional busdriver/receiver.
|
||
AllinputsarelowpowerTTLcompatible. FordrivingMOS,theDOoutputsprovideahigh3.65VVOH,andforhighcapaci
|
||
tanceterminated busstructures, theDBoutputsprovideahigh50mAIOlcapability.
|
||
Anon-inverting (8216)andaninverting (8226)areavailable tomeetawidevarietyofapplications forbuffering inmicro
|
||
computer systems.
|
||
PINCONFIGURATION
|
||
cs 16Vee
|
||
0°0 2 15 OlEN010
|
||
OBo3 14 0°3
|
||
0°0
|
||
01048216/ 13OB3
|
||
DO, 58226 12 013 01,
|
||
DB, 6 11 0°2
|
||
DO,
|
||
01, 7 10 OB2
|
||
GND 8 9 O~ 012
|
||
0°2
|
||
PINNAMES013
|
||
OBO·OB3DATABUS
|
||
BI-OIRECTIONAL
|
||
0'o.0~ DATAINPUT
|
||
000.0°3DATAOUTPUT
|
||
OlENDATAINENABLE
|
||
DIRECTION CONTROL
|
||
cs CHIPSELECTLOGICDIAGRAM
|
||
8216
|
||
010
|
||
OBo
|
||
0°0
|
||
01,,
|
||
DB,
|
||
DO,
|
||
012
|
||
OB2
|
||
0°2
|
||
013
|
||
OB3
|
||
0°3
|
||
------+- ......----n csLOGICDIAGRAM
|
||
8226
|
||
_----oOBO
|
||
_----0 DB,
|
||
------+ .......----0 cs
|
||
OlENo---_e_------J
|
||
5-163OlEN0--- .......------1
|
||
|
||
===PAGE 234===
|
||
SCHOTTKY BIPOLAR 8216/8226
|
||
FUNCTIONAL DESCRIPTION
|
||
DB,DB,
|
||
----OOBO------oOBO
|
||
'--------1- ----0 cs
|
||
OlENcs
|
||
00Ol~DB
|
||
10OB~DO
|
||
01}HIGH IMPEDANCE110130-------+----1 >--+--..01,0-------+---1 "--4--..
|
||
DO,o------t--~ I--~---'
|
||
OlEN~-------- ......003o------t-----c: 1-----+- ......0100----- ...."---1---..
|
||
OOoo------t-----c: 1-------1- ___'
|
||
(b)8226OlEN
|
||
(a)8216
|
||
010
|
||
0°0
|
||
01,
|
||
DO,
|
||
012
|
||
0°2
|
||
013
|
||
0°3ControlGatingOlEN,CS
|
||
TheCSinputisactually adeviceselect.Whenitis"high"
|
||
theoutputdriversareallforcedtotheirhigh-impedance
|
||
state.Whenitisat"zero"thedeviceisselected (enabled)
|
||
andthedirection ofthedataflowisdetermined bythe
|
||
DIENinput.
|
||
TheDIENinputcontrols thedirection ofdataflow(see
|
||
Figure1)forcomplete truthtable.Thisdirection control
|
||
isaccomplished byforcingoneofthepairofbuffersintoits
|
||
highimpedance stateandallowing theothertotransmit its
|
||
data.Asimpletwogatecircuitisusedforthisfunction.
|
||
The8216/8226 isadevicethatwillreducecomponent count
|
||
inmjcrocomputer systems andatthesametimeenhance
|
||
noiseimmunity toassurereliable, highperformance op
|
||
eration.Bi-Directional Driver
|
||
Eachbuffered Iineofthefourbitdriverconsists oftwo
|
||
separate buffersthataretri-stateinnaturetoachievedirect
|
||
businterface andbi-directional capability.Ononesideof
|
||
thedrivertheoutputofonebufferandtheinputofanother
|
||
aretiedtogether (DB),thissideisusedtointerface tothe
|
||
systemsidecomponents suchasmemories, I/O,etc.,be
|
||
causeitsinterface isdirectTTLcompatible andithashigh
|
||
drive(50mA). Ontheothersideofthedrivertheinputs
|
||
andoutputsareseparated toprovidemaximum flexibility.
|
||
Of·course,theycanbetiedtogether sothatthedrivercan
|
||
beusedtobufferatruebi-directional bussuchasthe8080
|
||
DataBus.TheDOoutputsonthissideofthedriverhavea
|
||
specialhighvoltageoutputdrivecapability (3.65V)sothat
|
||
directinterface tothe8080and8008CPUsisachieved with
|
||
anadequate amountofnoiseimmunity (350mV worstcase).Microprocessors likethe8080areMOSdevicesandare
|
||
generally capableofdrivingasingleTTLload.Thesameis
|
||
trueforMOSmemory devices. Whilethistypeofdriveis
|
||
sufficient insmallsystemswithfewcomponents, quiteoften
|
||
itisnecessary tobufferthemicroprocessor andmemories
|
||
whenaddingcomponents orexpanding toamulti-board
|
||
system.
|
||
The8216/8226 isafourbitbi-directional busdriverspecif
|
||
icallydesigned tobuffermicrocomputer systemcomponents.
|
||
Figure1.8216/8226 LogicDiagrams
|
||
5-164
|
||
|
||
===PAGE 235===
|
||
SCHOTTKY BIPOLAR 8216/8226
|
||
APPLICATIONS OF8216/8226 .
|
||
15
|
||
401OlEN300 2DODB OBo
|
||
7
|
||
016OB1 5
|
||
98216
|
||
822610D211 OB2
|
||
12
|
||
13DB303 14
|
||
cs
|
||
SYSTEM
|
||
8080OATA
|
||
15BUS
|
||
01OlEN3D4OB OB4DO
|
||
6
|
||
Os DBs8216
|
||
82261006OB6
|
||
0713DB7
|
||
CSThe8216/8226 canbeusedinawidevarietyofotherbuf
|
||
feringfunctions inmicrocomputer systemssuchasAddress
|
||
BusDrivers, Driverstoperipheral devicessuchasprinters,
|
||
andasDriversforlonglengthcablestootherperipherals or
|
||
systems.8080DataBusBuffer
|
||
The8080CPUDataBusiscapableofdrivingasingleTTL
|
||
loadandismorethanadequate forsmall,singleboardsys
|
||
tems.Whenexpandingsuchasystemtomorethanoneboard
|
||
toincrease I/OorMemory size,itisnecessary toprovidea
|
||
buffer.The8216/8226 isadevicethatisexactlyfittedto
|
||
thisapplication.
|
||
ShowninFigure2areapairof8216/8226 connected di
|
||
rectlytothe8080DataBusandassociated controlsignals.
|
||
Thebufferisbi-directional innatureandservestoisolatethe
|
||
CPUdatabus.
|
||
Onthesystemside,theDBlinesinterface withstandard
|
||
semiconductor I/OandMemory components andarecom-
|
||
pletelyTTLcompatible. TheDBlinesalsoprovideahigh
|
||
drivecapability (50mA) sothatanextremely largesystem
|
||
canbedirvenalongwithpossiblebustermination networks.
|
||
Onthe8080sidethe01andDOlinesaretiedtogether and
|
||
aredirectlyconnected tothe8080DataBusforbi-directional
|
||
operation. TheDOoutputsofthe8216/8226 haveahigh
|
||
voltageoutputcapability of3.65voltswhichallowsdirect
|
||
connection tothe8080whoseminimum inputvoltageis
|
||
3.3volts.Italsogivesaveryadequate noisemarginof
|
||
350mV(worstcase).
|
||
TheDIENinputsto8216/8226 isconnected directlytothe
|
||
8080.OlENistiedtoDBINsothatproperbusflowis
|
||
maintained, andCSistiedtoBUSEN sothatthesystem
|
||
sideDataBuswillbe3-statedwhenaHoldrequesthasbeen
|
||
acknowledged duringaDMAactivity.
|
||
I/O
|
||
01 DO
|
||
OlEN (2)CS
|
||
8216
|
||
8226(2)
|
||
BUSEN........----~MEMORY
|
||
01 DO
|
||
OlEN (2)CS
|
||
8216
|
||
8226(2)Figure2.8080DataBusBuffer.Memoryand1/0InterfacetoaBi-directional Bus
|
||
Inlargemicrocomputer systemsitisoftennecessary topro
|
||
videMemoryandI/Owiththeirownbuffersandatthesame
|
||
timemaintain adirect,common interface toabi-directional
|
||
DataBus.The8216/8226 hasseparated datainanddata
|
||
outlinesononesideandacommon bi-directional setonthe
|
||
othertoaccomodate suchafunction.
|
||
ShowninFigure3isanexample ofhowthe8216/8226 is
|
||
usedinthistypeofapplication.
|
||
Theinterface toMemory issimpleanddirect.Thememories
|
||
usedaretypically Intel®8102,8102A,8101or8107B-4 and
|
||
haveseparate datainputsandoutputs. TheDIandDOlines
|
||
ofthe8216/8226 tietothemdirectlyandundercontrolof
|
||
theMEMRsignal,whichisconnected totheDIENinput,
|
||
aninterface tothebi-directional DataBusismaintained.
|
||
Theinterface toI/OissimilartoMemory. TheI/Odevices
|
||
usedaretypically Intel®8255s,andcanbeusedforboth
|
||
inputandoutputports.TheI/ORsignalisconnected di
|
||
rectlytotheDIENinputsothatproperdataflowfromthe
|
||
I/OdevicetotheDataBusismaintained.
|
||
Figure3.Memory andI/OInterface toaBi-Directional Bus.
|
||
5-165
|
||
|
||
===PAGE 236===
|
||
SCHOTTKY BIPOLAR 8216/8226
|
||
D.C.ANDOPERATING CHARACTERISTICS
|
||
ABSOLUTE MAXIMUM RATINGS*
|
||
Temperature UnderBias ' O°Cto70°C
|
||
StorageTemperature -6SoCto+150°C
|
||
AllOutputandSupplyVoltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..-O.5Vto+7V
|
||
AllInputVoltages -1.0Vto+5.5V
|
||
OutputCurrents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..125rnA
|
||
*COMMENT: Stressesabovethoselistedunder"Absolute Maximum Rating"maycausepermanent damagetothedevice.Thisisastressrating
|
||
onlyandfunctional operation ofthedeviceattheseoratanyothercondition abovethoseindicated intheoperational sectionsofthisspecifi
|
||
cationisnotimplied.
|
||
Limits
|
||
Symbol Parameter Min. Typ. Max. Unit Conditions
|
||
IF1 InputLoadCurrentOlEN,CS -0.15 -.5mA VF=0.45
|
||
IF2 InputLoadCurrentAllOtherInputs -0.08 -.25 mA VF=0.45
|
||
IR1 InputLeakageCurrentOlEN,CS 20p.A VR=5.25V
|
||
IR2 InputLeakageCurrent01Inputs 10p.A VR=5.25V
|
||
Vc InputForward VoltageClamp -1 Vle=-5mA
|
||
Vil Input"Low"Voltage .95 V
|
||
VIH Input"High"Voltage 2.0 V
|
||
1101OutputLeakageCurrent DO 20p.A Vo=0.45V/5.25V
|
||
(3-State) DB 100
|
||
8216 95130 rnA
|
||
IcC PowerSupplyCurrent
|
||
8226 85120 rnA
|
||
VOl1 Output" Low"Voltage 0.3 .45 VDOOutputs IOl=15rnA
|
||
DBOutputs IOl=25rnA
|
||
8216 0.5 .6 V DBOutputs IOl=55mA
|
||
VOl2 Output"Low"Voltage
|
||
8226 0.5 .6 V DBOutputs IOL=50mA
|
||
VOH1 Output"High"Voltage 3.65 4.0 V DOOutputs IOH=-1mA
|
||
VOH2 Output"High"Voltage 2.4 3.0 V DBOutputs 10H=-1OmA
|
||
'OSOutputShortCircuitCurrent -15 -35 -65mA DOOutputs Vo==OV,
|
||
-30 -75-120 rnA DBOutputs Vee=5.0V
|
||
NOTE:TypicalvaluesareforTA=25°C,Vee=5.0V.
|
||
5-166
|
||
|
||
===PAGE 237===
|
||
SCHOTTKY BIPOLAR 8216/8226
|
||
WAVEFORMS
|
||
INPUTS -'X'-:,_5V _
|
||
l--tFD
|
||
OUTPUT
|
||
ENABLE
|
||
.5V
|
||
---+---V OH
|
||
fVOL
|
||
.5V
|
||
A.C.CHARACTERISTICS
|
||
TA= O°Cto+70°C,Vcc=+5V±5%
|
||
Limits
|
||
Symbol Parameter Min. Typ,£1] Max. Unit Conditions
|
||
TpD1 InputtoOutputDelayDOOutputs 15 25 nsCL=30pF,R 1=300n
|
||
R2=600n
|
||
TpD2 InputtoOutputDelayDBOutputs
|
||
8216 20 30 nsCL=300pF,R 1=90n
|
||
8226 16 25 nsR2=180n
|
||
TE OutputEnableTime
|
||
8216 45 65 ns(Note2)
|
||
8226 35 54 ns(Note3)
|
||
To Output DisableTime 20 35 ns(Note4)
|
||
TESTCONDITIONS:
|
||
Inputpulseamplitude of2.5V.
|
||
Inputriseandfalltimesof5nsbetween 1and2volts.
|
||
Output loadingis5rnAand10pF.
|
||
Speedmeasurements aremadeat1.5voltlevels.
|
||
Capacitance [5]TESTLOADCIRCUIT
|
||
OUT0---.......------ ......
|
||
Limits
|
||
Symbol Parameter Min. Typ'£1] Max. Unit
|
||
CIN InputCapacitance 4 8 pF
|
||
COUT1 Output Capacitance 6 10 pF
|
||
COUT2 OutputCapacitance 13 18 pF
|
||
TESTCONDITIONS: VB1AS=2.5V,Vcc=5.0V,TA=25°C,f=1MHz.
|
||
NOTES: 1.TvpicalvaluesareforTA=25°C,VCC=5.0V.
|
||
2.DOOutputs, CL=30pF,R1=300/10Kil,R2=180/1Kil;DBOutputs, CL=300pF,Rl=90/10Kil,R2=180/1Kil.
|
||
3.DOOutputs, CL=30pF,Rl=300/10Kil,R2=600/1K;DBOutputs, CL=300pF,Rl=90/10Kfl,R2=180/1Kil.
|
||
4.DOOutputs, CL=5pF,Rl=300/10Kil,R2=600/1Kil;DBOutputs, CL=5pF,R1=90/10Kil,R2=180/1Kil.
|
||
5.Thisparameter isperiodically sampled andnot100%tested.
|
||
5-167
|
||
|
||
===PAGE 238===
|
||
|
||
|
||
===PAGE 239===
|
||
ComingSoon
|
||
8253
|
||
8257
|
||
8259
|
||
|
||
===PAGE 240===
|
||
|
||
|
||
===PAGE 241===
|
||
SiliconGateMOS8253
|
||
PROGRAMMABLE INTERVAL TIMER
|
||
GATE0ItusesnMOStechnology
|
||
~----"OUT2ClKO
|
||
ClK2ClK1...------..OUT 0
|
||
COU':;TER 14'-_ GATE2COUNTER
|
||
#1 GATE1
|
||
.....---. OUT1z.~Jmodes'of operation arev"'."-
|
||
~O
|
||
S",9•CountBinaryorBCD
|
||
•Single+5VSUPR
|
||
•24PinDual-in-li
|
||
CONTROL
|
||
WORD
|
||
REGISTER
|
||
AND
|
||
MODE
|
||
SELECTIONPINCONFIGURATION• 3Independent 16-Bit
|
||
Counters
|
||
•DCto3MHz
|
||
•Programmable Counter
|
||
Modes
|
||
The8253isaprogrammable counter/timer chipdesigned foruseasan8080(or
|
||
withasingle+5Vsupplyandispackaged ina24-pinplasticDIP.
|
||
Itisorganized asthreeindependent 16-bitcounters, eachwithacountrat
|
||
software programmable bythe8080.
|
||
INTERNAL BUS/
|
||
5-169
|
||
|
||
===PAGE 242===
|
||
SILICON GATEMOS8253
|
||
8253PRELIMINARY
|
||
FUNCTIONAL DESCRIPTION
|
||
GATE2GATE0
|
||
ClK1CLKO
|
||
CLK2
|
||
OUT2OUT1GATE1
|
||
COUNTER
|
||
#2READ/
|
||
WRITE
|
||
lOGICDATA
|
||
BUS
|
||
BUFFER
|
||
INTERNAL BUScs-------'AD--___.a
|
||
WR-----+C11
|
||
8253BlockDiagram.InMicrocomputer-based systems themostcommon inter
|
||
faceistoamechanical devicesuchasaprinterheadorstep
|
||
permotor.Allsuchdeviceshaveinherent delaysthatmust
|
||
beaccounted forifaccurate andreliableperformance isto
|
||
beachieved. Thesystemssoftware allowsforsuchdelaysby
|
||
programmed timingloops.Thistypeofprogramming re
|
||
quiressignificant ov~rhead andmaintenance ofmultiple
|
||
loopsgetsextremely complicated.
|
||
The8253Programmable IntervalTimerisasinglechipso
|
||
lutiontosystemtimingproblems. Inessence, itisagroupof
|
||
three16-bitcounters thatareindependent innaturebut
|
||
drivencommonly asI/Operipheral ports.Insteadofsetting
|
||
uptimingloopsinthesystemsoftware, theprogrammer
|
||
configures the8253tomatchhisrequirements. Thepro
|
||
grammer initializes oneofthethreecounters ofthe8253
|
||
withthequantity andmodedesiredthen,uponcommand,
|
||
the8253willcountoutthedelayandinterrupt themicro
|
||
computer whenithasfinished itstask.Itiseasytoseethat
|
||
thesoftware overhead isminimal andthatmultiple delays
|
||
canbeeasilymaintained byassigned interrupt levelstodif
|
||
ferentcounters. Otherfunctions thatarenon-delay innature
|
||
andrequirecounters canalsobeimplemented withthe8253.
|
||
•Programmable BaudRateGenerator
|
||
•EventCounter
|
||
•BinaryRateMultiplier
|
||
•RealTimeClock
|
||
SystemInterface
|
||
The8253isacomponent oftheMC5-80systemandinter
|
||
facesinthesamemannerasallotherperipherals ofthe
|
||
family.Itistreatedbythesystems software asanarrayof
|
||
I/Oports;threearecounters andthefourthisacontrol
|
||
registerforprogramming. TheOUTlinesofeachcounter
|
||
wouldnormally betiedtotheinterrupt requestinputsof
|
||
the8259.
|
||
The8253represents asignificant improvement forsolving
|
||
oneofthemostcommon problems insystemdesignand
|
||
reducing software overhead.ADDRESS BUS(16)
|
||
A1An 00.07
|
||
8253
|
||
COUNTER COUNTER COUNTER 012
|
||
I I I
|
||
lOUTGATEClKIlOUTGATEClKIlOUTGATEClKI
|
||
8253SystemInterface.
|
||
5..170
|
||
|
||
===PAGE 243===
|
||
SiliconGateMOS8257
|
||
PROGRAMMABLE DMACONTROLLER
|
||
ORO3oACK2
|
||
OACK3ORO2OACK1OACK0
|
||
+--ORO1cl}mputer systems. Itspri
|
||
allowtheperipheral toac
|
||
;thesystembus.Italsokeeps
|
||
"grar11mable terminal counthas
|
||
~<,amon9,$fl'e fourchannels, program-
|
||
fors~~tbred datatransfers, anauto
|
||
/'dur!~:~i)DMA cycles.Therearethree
|
||
PRIORITY
|
||
RESOLVERe¢2,.JJTL) clockofthe8080system.Itis
|
||
'"Mulff;J3I'e DMAchipscanbeusedtoexpand
|
||
~..,.::-,/
|
||
c~::~"t•AutoLoadMode
|
||
•SingleTTLClock«(/)21TTL)
|
||
•Single+5VSUR~~
|
||
~~:W~l~\:~~ '.'.,
|
||
•Expandable
|
||
•40PinDu
|
||
A4----1
|
||
As----1
|
||
A6----1
|
||
A7----1
|
||
CONTROL
|
||
HOLD..........---1 LOGIC
|
||
HLDA----..
|
||
MEMR ---ClIII
|
||
MEMW ----<...JI
|
||
AEN----1
|
||
AoSTB ----1cs-----
|
||
REAoY----.tI•FourChannelDMAController
|
||
•PriorityDMARequestLogic
|
||
•ChannelInhibitLogic
|
||
•Terminal andModulo256/128
|
||
Outputs
|
||
The8257isaDirectMemory Access(DMA)Chipwhichhasfourchannels forusei
|
||
maryfunction istogenerate, uponaperipheral request,asequential memory aress
|
||
cessordepositdatadirectlyfromortomemory. ItusestheHoldfeatureofth
|
||
countofthenumberofDMAcyclesforeachchannelandnotifiestheperiphe
|
||
beenreached. Otherfeaturesthatithasaretwomodeprioritylogictores/
|
||
mabiechannelinhibitlogic,anearlywritepulseoption,amodulo256/1
|
||
maticloadmode,aterminal countstatusregister,andcontrolsignaL;:-· .
|
||
typesofDMAcycles:ReadDMACycle,WriteDMACycleandVerify,/,t
|
||
The8257isa40-pin,N-channel MOSchipwhichusesasingle ~;
|
||
designed toworkinconjunction withasingle82128-bit, thr~
|
||
thenumberofchannelswiththeaidofthe8214PriorityInter'
|
||
TC..........----'"
|
||
128/256..----------'INTERNAL
|
||
BUS
|
||
5-171
|
||
|
||
===PAGE 244===
|
||
SILICON GATEMOS8257
|
||
8257PRELIMINARY FUNCTIONAL DESCRIPTION
|
||
Thetransfer ofdatabetween amassstoragedevicesuchas
|
||
afloppydiskormagcassette andsystemRAMmemory is
|
||
oftenlimitedbythespeedofthemicroprocessor. Removing
|
||
theprocessor duringsuchatransferandlettinganauxiliary
|
||
devicemanagethetransfer inamoreefficient mannerwould
|
||
greatlyimprove thespeedandmakemassstoragedevices
|
||
moreattractive, eventothesmallsystemdesigner.
|
||
Thetransfertechnique iscalledDMA(DirectMemory Ac
|
||
cess);inessencetheCPUisidledsothatitnolongerhas
|
||
controlofthesystembusandaDMAcontroller takesover
|
||
tomanagethetransfer.
|
||
The8257Programmable DMAController isasinglechip,
|
||
fourchanneldevicethatcanefficiently manageDMAactiv
|
||
ities.Eachchannel isassigned apriority levelsothatif
|
||
multi-DMA activities arerequired eachmassstoragedevice
|
||
canbeserviced, basedonitsimportance inthesystem. Inoperation, arequestismadefromaperipheraIdevicefor
|
||
accesstothesystembus.Afteritspriorityisaccepted a
|
||
HOLDcommand isussuedtotheCPU,theCPUissues
|
||
aHLDAandthatDMAchannel hascomplete controlofthe
|
||
systembus.Transfers canbemadeinblocks,suspending
|
||
theprocessors operation duringtheentiretransfer or,the
|
||
transfer canbemadeafewbytesatatime,hiddeninthe
|
||
execution statesofeachinstruction cycle,(cycle-stealing).
|
||
Themodesandpriority resolving aremaintained bythe
|
||
systemsoftware aswellasinitializing eachchannelastothe
|
||
startingaddressandlengthoftransfer.
|
||
Thesysteminterface issimilartotheotherperipheraIsof
|
||
theMCS-80 butanadditional 8212isnecessary tocontrol
|
||
theentireaddress bus.Aspecialcontrol signalBUSEN is
|
||
connected directly tothe8228sothatthedatabusand
|
||
controlbuswillbereleasedatthepropertime.
|
||
ADDRESS BUS\ ADDRESS BUS(16) \
|
||
~ CONTROL BUS \
|
||
flOW ilOR HOLD RESET
|
||
~ DATABUS(8) \
|
||
As-A,54:/'\~MEMR MEMW READY
|
||
1/V8
|
||
/ Ao-A3/A4-A7
|
||
'---l/L-- 88212['r-
|
||
92(TTL)ttHLDA
|
||
BUSEN
|
||
8228I1 "',/7
|
||
CSAo·A3A4-A7AOSTB AEN 07-00I/O MEM HOLDHLOA CLK ROYIN RESET
|
||
WRifW
|
||
8257
|
||
128/256 DACK ORO DACK ORO DACK ORO DACK ORO
|
||
MODTC 3 3 2 2 1 1 0 0
|
||
~! ~tltl1lf
|
||
I
|
||
OMACHANNEL REOUESTS ANDACKNOWLEDGES
|
||
SystemInterface 8257.
|
||
8257
|
||
AND
|
||
8212ORO0......-----11
|
||
DACK01------..
|
||
ORO11..-----1
|
||
DACK1I___-----.t
|
||
ORO2......----11
|
||
DACK21------...
|
||
ORO31+------1
|
||
DACK31--------..DISK1
|
||
DISK2SYSTEM
|
||
RAM
|
||
MEMORY
|
||
OMACONTROLLER
|
||
SystemApplication of8257.DUALFLOPPYDISKCONTROLLER
|
||
5-172
|
||
|
||
===PAGE 245===
|
||
SiliconGateMOS8259
|
||
PROGRAMMABLE INTERRUPT CONTROLLER
|
||
rupto64vectored priority
|
||
technology andrequiresa
|
||
IR0
|
||
4---IR 1
|
||
REQUEST IR2
|
||
LATCH4---IR3INTERRUPT
|
||
MASK.--IR4REQUESTS
|
||
REGISTER 4---IR5
|
||
"'-IR6
|
||
"'-IR7READ!
|
||
WRITE
|
||
LOGIC•Individual RequestMask
|
||
Capability
|
||
•Single+5VSup
|
||
(NoClocks)
|
||
•28PinDua ckage
|
||
o
|
||
CS-------It
|
||
CASO~--.nI
|
||
CAS1....--....n
|
||
CAS2"""---.nII
|
||
SP~--.nII CONTROL
|
||
LOGICPINCONFIGURATION•EightLevelPriorityController
|
||
•Expandable to64Levels
|
||
•Programmable Interrupt
|
||
Modes(Algorithms)
|
||
The8259handlesuptoeightvectored priorityinterrupts forthe8080ACPU.I
|
||
interrupts, without additional circuitry. Itwillbe,packaged ina28-pinplasf
|
||
single+5Vsupply.Circuitry isstatic,requiring noclockinput.
|
||
The8259isdesigned tominimize thesoftware andrealtimeoverhead in
|
||
modes,permitting optimization foravarietyofsystemrequirements.
|
||
INT......----I
|
||
INTA---.nI~INTERNALBUS
|
||
5-173
|
||
|
||
===PAGE 246===
|
||
SILICON GATEMOS8259
|
||
8259PRELIMINARY
|
||
FUNCTIONAL DESCRIPTION
|
||
I
|
||
INTERRUPT
|
||
REQUESTS8259
|
||
IRQIRQIRQIRQIRQ IRQ IRQIRQ765 4~2 1 0
|
||
SLAVE
|
||
PROG.ADDRESS BUS(16)
|
||
8259SystemInterface.Inmicrocomputer systems, therateatwhichaperipheral
|
||
deviceordevicescanbeserviceddetermines thetotalamount
|
||
ofsystem tasks thatcanbeassigned tothecontrolofthe
|
||
microprocessor. Thehigherthethroughput themorejobs
|
||
themicrocomputer candoandthemorecosteffective itbe
|
||
comes.Interrupts havelongbeenaccepted asakeytoim
|
||
provingsystemthroughput byservicing aperipheral device
|
||
onlywhenthedevicehasrequested ittodoso.Efficient
|
||
managing oftheinterrupt requeststotheCPUwillhavea
|
||
significant effectontheoverallcosteffectiveness ofthe
|
||
microcomputer system.
|
||
The8259Programmable Interrupt Controller isasingle-chip
|
||
devicethatcanmanageeightlevelsofrequestsandhasbuilt
|
||
infeaturesforexpandability toother8259s(upto64levels).
|
||
Itisprogrammed bythesystemssoftware asanI/Operiphe
|
||
ral.Aselection ofpriorityalgorithms isavailable tothepro
|
||
grammer sothatthemannerinwhichtherequests arepro
|
||
cessedbythe8259canbeconfigured tomatchhissystem
|
||
requirements. Thepriorityassignments andalgorithms can
|
||
bechanged orreconfigured dynamically atanytimeduring
|
||
themainprogram. Thismeansthattheoomplete interrupt
|
||
structure canbedefinedasrequired, basedonthetotalsys
|
||
temenvironment.
|
||
Thesysteminterface isthesameasotherperipheral devices
|
||
intheMC5-80. Aspecialinputisprovided (SP)toprogram
|
||
the8259asaslaveormasterdevicewhenexpanding to
|
||
morethaneightlevels.Basically themasteracceptsINTin
|
||
putsfromtheslavesandissuesacomposite requesttothe
|
||
8080A;whenitreceivestheINTAfromthe8228itputs
|
||
thefirstbyteontheCALLonthebus.Onsubsequent
|
||
INTAstheinterrupting slaveputsouttheaddressofthe
|
||
vector.
|
||
~ ADDRESSBUS(16)~
|
||
\CONTROL BUS \
|
||
INTREQ
|
||
\ DATABUS(8) \
|
||
.",-to/'.. ,t./'..,t.:lo------------ I------ ~-1-----~---I- ~-- I---I-------I-- I----
|
||
(~v'7 ~V7r-- ~,7"''...1''1~v'7 "'v'7
|
||
""''"
|
||
82598259 8259
|
||
SLAVE2p.-I--SLAVE1 '" MASTER
|
||
p...t-""''"
|
||
Sf SP SP
|
||
G!O1fIllf11 G!Of f ffIlIIlJJJ1111,
|
||
21201918171615 14 13 12 11109 8 7 6 5 4 3 2 1 0
|
||
I
|
||
INTERRUPT REQUESTS
|
||
Cascading the825922LevelController (Expandable to64levels).
|
||
5-174
|
||
|
||
===PAGE 247===
|
||
CPU
|
||
GROUP
|
||
ROMs
|
||
RAMs
|
||
I/O
|
||
PERIPHERAL
|
||
COMING
|
||
SOONIntel StandardNumberProduct PackageOfPinsComments
|
||
Number Type
|
||
8224 C0P 16
|
||
-8228 C0P 28
|
||
8080A C 40Including 8080A-1,
|
||
8080A-2 andM8080A
|
||
8702A C 24
|
||
8708/4 C 24
|
||
-8302 C P 24
|
||
8308 C P 24
|
||
8316A C P 24
|
||
8101-2 C P 22
|
||
8111-2 C P 18
|
||
8102-2 C P 16
|
||
8102A-4 C P 16-
|
||
81078-4 C P 22
|
||
5101 C P 22
|
||
8210 0P 18
|
||
8222 D 22 NewProduct
|
||
8212 0P 24
|
||
-8255 C 40
|
||
8251 C P 28
|
||
8205 C0P 16
|
||
-8214 C0P 24
|
||
8216/26 0P 16
|
||
8253 24 ComingSoon
|
||
-8257 40 ComingSoon
|
||
8259 28 ComingSoon
|
||
C=Ceramic 0=Cerdip P=Plastic
|
||
6·1
|
||
|
||
===PAGE 248===
|
||
PACKAGING INFORMATIONDimensions ininchesand(millimeters).
|
||
16-LEAD CERAMIC DUALIN-LINE PACKAGE (C) 16-LEAD CerDIPDUALIN-LINE PACKAGE (D)
|
||
I---l-~ ~TYP.
|
||
.11012,7941~:[O:::JJ
|
||
I .735~ I
|
||
.830121,0821
|
||
~!2.ill1_
|
||
.02310,5841
|
||
:Q!Q~-
|
||
.06511.651~~.070(1,778)
|
||
16-LEAD PLASTIC DUALIN-LINE PACKAGE (P) 1a-LEAD CERAMIC DUALIN-LINE PACKAGE (C)
|
||
f----- ----~lli!.mlI _ .855121,7171
|
||
.05011,271
|
||
MAX.I1-.290~-l
|
||
?ml17'~741~
|
||
-II-,~-1I-
|
||
~~TYP .
|
||
•012(0,3051.-r--t==:I..lI::t.~....:::::::Io.I:=--e::s...c:~::::IiIloI~.,
|
||
I~~
|
||
.29517,493)ALTERNATE PIN;:1IDENT.
|
||
(IFNONOTCHATENDOFPKG.I
|
||
rr~:~':~:1
|
||
.0751t.9051 .02510,6351lREF'r-IREF.
|
||
R,~t
|
||
.OO8~
|
||
:Di210,3051
|
||
I~~II---.410110.41414
|
||
1a-LEAD CerDIPDUALIN-LINE PACKAGE (D) 1a-LEAD PLASTIC DUALIN-LINE PACKAGE (P)
|
||
I,B50~I.930123,62)C:=§'.240~:'L1
|
||
I ,905~ I
|
||
.925(23,495)
|
||
11-.045/1,141 .07011,7B}
|
||
- I :07011,7BI :i1ii112..l91
|
||
i'i=i::::i"=i:=i=1 =i:::1
|
||
::;::::;i::::i=:::;::::::j;:::::=c::::;=;::::;::::=;=;:=r~-+ll~~')MAX
|
||
I t!JIO,511--r- .05011,27}
|
||
.100(2,541
|
||
:;so13,81)f20015,~ .140~
|
||
~ T.2~l~~'.-_.._----- ----_.-LL
|
||
~ I • ].075/1,905)
|
||
!IJL REF.
|
||
,057~~i4611 -l~~~
|
||
•~~~~ .032(0,8131' 1·15013,Bl}
|
||
.11012,794} .065/1,6511 REF.:21§~
|
||
.024IO,610}.10012,54}
|
||
REF,
|
||
It-j
|
||
22-LEAD CERAMIC DUALIN-LINE PACKAGE (C)
|
||
114·-------~:~~e------- ....·1
|
||
PIN#lIDr
|
||
~lMW ............25R.REF
|
||
.4~[Lr-__.....,--,.....,--,. ,..........,.....,--,-.....,........,......,......,.-.,.......,. (NOTCHOPTIONAl)
|
||
~~
|
||
.040/1,016) ,054~
|
||
t* :oso(r0321
|
||
200Is,oa;f ~
|
||
MAX, L...i.
|
||
L
|
||
1Jl IIL/If.39Ol!.!!!!L
|
||
:~:~. ~~ -.jf4-~=, Ji50/1,271-.ff.-.010(()~:10,414)
|
||
~,.----- 10Ea.SPACES@.10012,540)
|
||
6-2
|
||
|
||
===PAGE 249===
|
||
PACKAGING INFORMATION Dimensions ininchesand(millimeters).
|
||
22-LEAD PLASTIC DUALIN-LINE PACKAGE (P)
|
||
PIN1
|
||
~
|
||
I·34o~
|
||
.36019.144)
|
||
.12613.175)I
|
||
1;r==i="-.=:::::p;;;;;r==:p;;;;r=;~==p:;r=::::p;:;;;;r=:::;;:::;;r==Fr===r;;;;;:;==;:;:or="'~
|
||
.02510,635)
|
||
I. 1.090~) II RjF.
|
||
1.110128.194) ---l-
|
||
.02010,508) - --- -::r~ :t
|
||
MIN. .16014,0641-L -.L
|
||
--r-Il.~II .15013,81)~--==l O'
|
||
\.--.J..'~~~lj~-jhj -L-i~.•,~~::~,•.'.1 ...
|
||
~= .03~~p~'3) .06~~p~24)
|
||
24-LEAD CERAMIC DUALIN-LINE PACKAGE (C) 24-LEAD CerDIPDUALIN-LINE PACKAGE (D)
|
||
~:::::::------h
|
||
.550113.97)
|
||
..................................................................... ,..,.l1'u, IPIN1-----.JL:Qg~ TYP11.060 (1,624) .NOTE1.0.126(3.176)MAX.
|
||
NOTE2.0.05011,279)MAX.
|
||
~~
|
||
.012(0,305)NOTE1
|
||
I1.175~U .050llJ1IDREF
|
||
·D4~~F·'i 1.300133.0'01~ _~3.D481 #:."'"r-------.
|
||
~~~~~ Tt11~~l\
|
||
-r-::..Ih .032(O,813)--1h 0"-/ ~~I'1 TYP.I 15°/~=
|
||
:~g~TYP. ~~TYP. BENDLINEI__ '~112.701__1
|
||
.800115,241.07011.78)
|
||
.110,12.79)
|
||
...--.....-----------.... I120
|
||
-liIS.59) MAX."..__.........__..n
|
||
-+tt__ .~(0.20)
|
||
.020(0.511 .012(0.30)
|
||
.05011.27) 1_~115,24)-1
|
||
.~12,54) .730118,64) I
|
||
.150(3,81).015(0,38)
|
||
:023(0,581 I
|
||
.0076(0.19)I I
|
||
.0116(0.29)-rI
|
||
~.090(2.29)
|
||
r-r:iiO(2.79)
|
||
24-LEAD PLASTIC DUALIN-LINE PACKAGE (P) 28-LEAD CERAMIC DUALIN-LINE PACKAGE (C)
|
||
I.... ~:=~-----.I
|
||
I'1.4013.556)
|
||
'1MAX.
|
||
Dt
|
||
,ill1.!.M§§J
|
||
.588(14.735)
|
||
~
|
||
j~"30(&'''')~ MAX.-,-- -
|
||
.020(0,508) ~
|
||
MIN. I~~I :1Q:Q~.015~_ .090~ .150(3.8101m10.584) -:roo 12.6401TYP.(REF)
|
||
•19014,826)-. REF.
|
||
----l.
|
||
.150(3.81)
|
||
REF.
|
||
.250(6,35)
|
||
REF•
|
||
•200'&,081. .07011.n8) "-MAX. REF.I-±-If ---- .145~Y *~(4,'9')
|
||
I'IJL ---.~ .020(0,508)
|
||
I . .032(0,813)II-..j"MIN.
|
||
-1f-.06011,524) REF.r-l~ .100(2,64)
|
||
REF.~~ TYP.
|
||
•023(0,684)
|
||
40-LEAD CERAMIC DUALIN-LINE PACKAGE (C)
|
||
2·,c:l~,34}- 1
|
||
PIN1-r
|
||
~~
|
||
.,..,,..,..,,..,..,l"T"'ll"T"'lrT"'ll"T"'l,.,..,r-r;p:iiiiii~;:;;::;~~"I""'I'''I'''''I'''I'''''W'''I'''''W' ...........~••361
|
||
I ~230 1&.6421..i- MAX.
|
||
..o,.r::- jt
|
||
MIN.ILIL --t...1oo~1
|
||
_&!§~ _ ~~TYP :16013.81)
|
||
.02310.5841 .11012.7941'
|
||
6-3
|
||
|
||
===PAGE 250===
|
||
SALESANDMARKETING OFFICES
|
||
U.S.SALESANDMARKETING OFFICES
|
||
U.S.MARKETING HEADQUARTERS NATIONAL SALESMANAGER
|
||
3065BowersAvenue HankO'Hara
|
||
SantaClara,California 95051' 3065BowersAvenue
|
||
Tel(408)246-7501 SanlaClara.California 95051'
|
||
TWX:910-338-0026 Tel(408)246·7501
|
||
TELEX:34-6372 TWX910-338·0026
|
||
TELEX'34-6372
|
||
U.S.REGIONAL SALESMANAGERS' OFFICES
|
||
WESTERN MID-AMERICA
|
||
WilliamT.O'Brien MickCarrier
|
||
1651East4thStreet 6350LBJ.Freeway
|
||
Suite228 SUIte178
|
||
SantaAna,California 92701· Dallas.Texas75240'
|
||
Tel(714)835-9642 Tel(214)661-8829
|
||
TWX.910-595-1114 TWX910-860-5487NATIONAL DISTRIBUTOR MANAGER
|
||
JamieKirk
|
||
3065BowersAvenue
|
||
SantaClara.California 95051•
|
||
Te/'(408)246-7501
|
||
TWX910·338-0026
|
||
TELEX34-6372
|
||
GREATLAKESREGION
|
||
HankJosefczyk
|
||
8312NorthMainStreet
|
||
Dayton.Ohio45415
|
||
Tel(513)890-5350
|
||
TELEX288-004EASTERN
|
||
JimSaxton
|
||
187Billerica Road
|
||
Chelmsford. MassaChusetts 01824
|
||
Tel(617)861-1136
|
||
TWX.710-321-0187
|
||
INTERNATIONAL DISTRIBUTORSEUROPEAN MARKETING OFFICES
|
||
EUROPEAN MARKETING HEADQUARTERS
|
||
BELGIUM FRANCE
|
||
TomLawrence Bernard Giroud
|
||
IntelOffice IntelOffice
|
||
216AvenueLouise CidexR-141
|
||
Brussels B-l050 F-94534 Rungis
|
||
Tel:(02)649-20-03 Tel:(1)677-60-75
|
||
TELEX:24814 TELEX:27475U.S.SALESOFFICES
|
||
ALABAMA
|
||
BarnhillandAssociates
|
||
7844Horseshoe Trail
|
||
Huntsville 35802
|
||
Tel:(205)883-9394
|
||
ARIZONA
|
||
SalesEngineering, Inc.
|
||
7155E.Thomas Road.No.6
|
||
Scottsdale 85252
|
||
Tel:(602)945-5781
|
||
TWX910-950-1288
|
||
CALIFORNIA
|
||
IntelCorp.
|
||
3065BowersAvenue
|
||
SantaClara95051
|
||
Tel:(408)246-7501
|
||
TWX:910-338-0026
|
||
Mac-I
|
||
PO.Box1420
|
||
Cupertino 95014
|
||
Tel(408)257-9880
|
||
EarleAssociates, Inc.
|
||
4433ConvoyStreet
|
||
SuiteA
|
||
SanDiego92111
|
||
Tel:(714)278-5441
|
||
TWX:910-335-1585
|
||
InleiCorp.
|
||
1651East4thSireel
|
||
Suite228
|
||
SantaAna92701
|
||
Tel:(714)835-9642
|
||
TWX:910-595-1114
|
||
COLORADO
|
||
IntelCorp.
|
||
12075East45thAvenue
|
||
Suite310
|
||
Denver80239
|
||
Tel:(303)373-4920
|
||
FLORIDA
|
||
IntelCorp.
|
||
1090NE27thTerrace
|
||
Pompano Beach33062
|
||
Tel:(305)781-7450
|
||
TWX:510-956-9407
|
||
IntelCorp.
|
||
5151Adanson Street,Suite200-3
|
||
Orlando 32804
|
||
Tel:(305)628-2393
|
||
AUSTRALIA
|
||
A.JFerguson (Adelaide) PTY,Ltd.
|
||
44Prospect Rd.
|
||
Prospect 50822
|
||
Tel:269-1244
|
||
TELEX:82635
|
||
AUSTRIA
|
||
BacherElektronische GerateGmbH
|
||
Meidlinger Hauptstrasse 78
|
||
A1120Vienna
|
||
Tel:(0222)836396
|
||
TELEX:(01)1532
|
||
BELGIUM
|
||
InelcoBelgiumSA
|
||
AvenueValOuchesse, 3
|
||
B-1160Bruxelles
|
||
Tel:(02)600012
|
||
TELEX:25441
|
||
ENGLAND
|
||
G.E.C.Semiconductors ltd.
|
||
EastLane
|
||
Wembley
|
||
Middlesex HA97PP
|
||
Tel:(01)904-9303
|
||
TELEX:923429ILLINOIS
|
||
InlelCorp.
|
||
900JorieBoulevard
|
||
SUite138
|
||
Oakbrook 60521
|
||
Tel(312)325-9510
|
||
TWX910-222-2710
|
||
INDIANA
|
||
Sheridan Associates. Inc.
|
||
4002Meadows Drive
|
||
Indianapolis 46205
|
||
Tel:(317)547-7777
|
||
KANSAS
|
||
Sherrdan Associates. Inc.
|
||
10100SantaFeDr.
|
||
Mark1Bldg..Suite101
|
||
Overland Park66212
|
||
Tel:(913)383-1636
|
||
MARYLAND
|
||
BarnhillandAssociates
|
||
57WestTimonium Road
|
||
Timonium 21093
|
||
Tel(301)252-7742
|
||
BarnhillandAssociales
|
||
PO.Box251
|
||
GlenArm21057
|
||
Tel:(301)252-5610
|
||
IntelCorp.
|
||
57WestTimonium Road
|
||
Suite307
|
||
Timonium 21093
|
||
Tel(301)252-7742
|
||
MASSACHUSETS
|
||
Dalcom
|
||
55MoodyStreet
|
||
Waltham 02154
|
||
Tel:(617)891-4600
|
||
TELEX92-3462
|
||
IntelCorp.
|
||
187Billerica Road
|
||
Chelmsford 01824
|
||
Tel:(617)861-1136
|
||
TWX:710-321-0187
|
||
MICHIGAN
|
||
Sheridan Associates. Inc.
|
||
24543Indoplex Drixe
|
||
Farmington Hills48024
|
||
Tel.(313)477-3800
|
||
DENMARK
|
||
Scandinavian Semiconductor
|
||
SupplyA/S
|
||
20.Nannasgade
|
||
DK-2200 Copenhagen N
|
||
Tel:(01)935090
|
||
TelEX:19037
|
||
FINLAND
|
||
Havulinna Oy
|
||
P.O.Box468
|
||
SF00100Helsinki 10
|
||
Tel:(90)664451
|
||
TELEX:12426
|
||
FRANCE
|
||
TekelecAirtronic
|
||
CitedesBruyeres
|
||
RueCarleVernet
|
||
92Sevres
|
||
Tel(01)626-02-35
|
||
TELEX:25997IntelCorp.
|
||
725SouthAdamsRoad
|
||
Suile288
|
||
BirminQham 48011
|
||
Tel:(313)642·7018
|
||
MINNESOTA
|
||
IntelCorp.
|
||
475Southgate OfficePlaza
|
||
5001West80thStreet
|
||
Bloomington 55437
|
||
Tel(612)835-6722
|
||
TWX:910-576-2867
|
||
MISSOURI
|
||
Sheridan Associates. Inc.
|
||
110SHighway 140
|
||
Suite10
|
||
Florissant 63033
|
||
Tel(314)837·5200
|
||
NEWYORK
|
||
Ossmann Components SalesCorp.
|
||
395Cleveland Drive
|
||
Buffalo14215
|
||
Tel(716)832-4271
|
||
Ossmann Components SalesCorp.
|
||
280MetroPark
|
||
Rochester 14623
|
||
Tel(716)442-3290
|
||
Ossmann Components SalesCorp.
|
||
1911VestalParkway E
|
||
Veslal13850
|
||
lei(607)785-9949
|
||
Ossmann Components SalesCorp.
|
||
132PickardBuilding
|
||
Syracuse 13211
|
||
Tel(315)454-4477
|
||
TWX710-541-1522
|
||
Ossmann Components SalesCorp.
|
||
140PineStreet
|
||
Kingston 12401
|
||
Tel:(914)338·5505
|
||
SCANDINAVIA
|
||
JohnJohansen
|
||
IntelOffice
|
||
Lingbyvej 322ndFI
|
||
DK2100Copenhagen East
|
||
Denmark
|
||
Tel:(01)182000
|
||
TELEX:19567
|
||
LennartErikkson
|
||
IntelOffice
|
||
Box86
|
||
S-16212 Vallingby 1
|
||
Sweden
|
||
Tel:(08)375370
|
||
TELEX:13164(ABCENT)
|
||
GERMANY
|
||
AlfredNeyeEnatachnik GmbH
|
||
Schillerstrasse 14
|
||
2085Ouickborn-Hamburg
|
||
Tel:(04106) 612-1
|
||
TELEX:02-13590
|
||
ISRAEL
|
||
Telsysltd.
|
||
54.Jabolinsky Road
|
||
Ramat•Gan52464
|
||
Tel:(3)-739865
|
||
TELEX:32392
|
||
ITALY
|
||
Eledra3S
|
||
ViaLudovico daViadana 9
|
||
20122Milano
|
||
Tel:(02)860307
|
||
TelEX:32027
|
||
SPAIN
|
||
Interface
|
||
RondaGeneralMitre::7
|
||
Barcelona 17
|
||
Tel:(93)203-53·30
|
||
TELEX:54713NORTH CAROLINA
|
||
BarnhillandAssociales
|
||
913PlateauLane
|
||
Raleigh27609
|
||
Tel.(919)876·5617
|
||
OHIO
|
||
Sheridan Associates. Inc
|
||
23224Commerce ParkRd.
|
||
Beachwood 44122
|
||
Tel.(216)831-0130
|
||
Sheridan Associates. Inc.
|
||
ShilohBldg.
|
||
SUite250
|
||
5045NorthMainStreet
|
||
Dayton45405
|
||
Tel(513)277-8911
|
||
Sheridan Associates, Inc.
|
||
10Knollcresl Drive
|
||
Cincinnati 15237
|
||
Tel(513)761-5432
|
||
TWX810·461-2670
|
||
IntelCorp.
|
||
8312NorlhMainStreet
|
||
Dayton45415
|
||
Tel(513)890-5250
|
||
TELEX.288-004
|
||
OREGON
|
||
ES/Chase Co.
|
||
POBox 626
|
||
Beaverton 97005
|
||
Tel(503)649·6177
|
||
PENNSYLVANIA
|
||
Vantage SalesCompany
|
||
21BalaAvenue
|
||
BalaCynwyd 19004
|
||
Tel(215)667-0990
|
||
TWX.510-662-5846
|
||
Sheridan Associates, Inc.
|
||
1717PennAvenue
|
||
SUite5009
|
||
Plllsburgh 15221
|
||
Tel(412)244·1640
|
||
InlelCorp.
|
||
520Pennsylvania Ave.Suite102
|
||
FortWashington 19034
|
||
Tel(215)542-9444
|
||
TWX510-661-3055
|
||
EUROPEAN MARKETING OFFICES
|
||
ENGLAND
|
||
KeithChapple
|
||
InlelOffice
|
||
Broadlield House
|
||
4Between TownsRoad
|
||
Cowley, OxfordOX43NB
|
||
Tel(0865)771431
|
||
TELEX.837203
|
||
NETHERLANDS
|
||
InelcoNederland BV
|
||
AFDElektronic
|
||
JoanMuyskenweg 22
|
||
Amsterdam 1006
|
||
Tel:(020)93-48-24
|
||
TELEX:14622
|
||
NORWAY
|
||
NordiskElektronik (Norge)A/S
|
||
Muslads Vei1
|
||
Oslo2
|
||
Tel.(02)553893
|
||
TELEX:16963
|
||
SOUTHAFRICA
|
||
Electronic Building Elements
|
||
P,O.Box4609
|
||
Pretoria
|
||
Tel:78-9221
|
||
TELEX:30181SATENNESSEE
|
||
BarnhillandAssociates
|
||
206Croicasaw Drive
|
||
Johnson City37601
|
||
Tel:(615)928-0184
|
||
TEXAS
|
||
Evans&McDowell Associates
|
||
13777N.CentralExpressway
|
||
Suite405
|
||
Dallas75231
|
||
Tel(214)238-7157
|
||
TWX910-867-4763
|
||
Evans&McDowell Associales
|
||
6610HarwlnAvenue, Suite125
|
||
Houston 77036
|
||
Tel.(713)783-2900
|
||
IntelCorp.
|
||
6350LBJ.Freeway
|
||
Suite178
|
||
Dallas75240
|
||
Tel(214)661-8829
|
||
TWX.910-860-5487
|
||
VIRGINIA
|
||
BarnhIll andAssociates
|
||
P.O.Box1104
|
||
2532Langhorne Road
|
||
Lynchburg 24501
|
||
Tel(703)846-4624
|
||
WASHINGTON
|
||
ES/Chase Co.
|
||
P.O.Box249
|
||
Edmonds 98020
|
||
Tel.(206)774-3586
|
||
CANADA
|
||
Multrlek. Inc.
|
||
4BarranStreet
|
||
Ottawa.OntarioK2JlG2
|
||
Tel(613)825-4695
|
||
TELEX053-4585
|
||
GERMANY
|
||
ErlingHolst
|
||
IntelOffice
|
||
Wolfratschauserstrasse 169
|
||
08Munchen 71
|
||
Tel:(089)798923
|
||
TELEX:5-212870
|
||
KlausKottenbrink
|
||
IntelOflice
|
||
0-6272Niedernhauser
|
||
Wiesenweg 26
|
||
W.Germany
|
||
Tel:6127/2314
|
||
SWEDEN
|
||
NordiskElectronik AS
|
||
Fack
|
||
S-103Stockholm 7
|
||
Tel:(08)-24-83-40
|
||
TELEX:10547
|
||
SWITZERLAND
|
||
Industrade AG
|
||
Gemsenstrasse 2
|
||
Postcheck 80-21190
|
||
8021Zurich
|
||
Tel:(01)602230
|
||
TELEX:56788
|
||
UNITED KINGDOM
|
||
RapidRecall.Ltd.
|
||
11-14Betterton Street
|
||
DruryLane
|
||
LondonWC2H9BS
|
||
Tel:(01)379-6741
|
||
TELEX:28752
|
||
ORIENT MARKETING OFFICES
|
||
ORIENT MARKETING HEADQUARTERS ORIENT DISTRIBUTORS
|
||
JAPAN JAPAN
|
||
T.Kama PanElektron Inc.
|
||
/nlelJapanCorporation No.1Higashikala-Machi
|
||
Kasahara Bldg. Midori-Ku. Yokohama 226
|
||
1-6-10.Uchikanda Tel:(045) 471·8321
|
||
Chiyoda-ku TelEX:781·4773
|
||
Tokyo101
|
||
Tel:(03)295-5441
|
||
TELEX:781-28426
|
||
|
||
===PAGE 251===
|
||
u.s.DISTRIBUTORS
|
||
u.s.DISTRIBUTORS
|
||
WEST
|
||
ARIZONA
|
||
Cramer/Arizona
|
||
2643EastUniversity Drive
|
||
Phoenix85034
|
||
Tel:(602)263·1112
|
||
Hamilton/Avnet Electronics
|
||
2615South21stStreet
|
||
Phoenix85034
|
||
Tel:(602)275·7851
|
||
CALIFORNIA
|
||
Hamilton/Avnet Electronics
|
||
575E.Middlefield Road
|
||
Mounlain View94040
|
||
Tel:(415)961·7000
|
||
Hamillon/Avnet Electronics
|
||
8917Complex Drive
|
||
SanDiego92123
|
||
Tel:(714)279·2421
|
||
Hamilton ElectroSales
|
||
10912W.Washington Boulevard
|
||
CulverCity90230
|
||
Tel:(213)558-2121
|
||
Cramer/San Francisco
|
||
720Palomar Avenue
|
||
Sunnyvale 94086
|
||
Tel:(408)739-3011
|
||
Cramer/los Angeles
|
||
17201DaimlerStreet
|
||
Irvine92705
|
||
Tel:(714)979-3000
|
||
Cramer/San Diego
|
||
8975Complex Drive
|
||
SanDiego92123
|
||
Tel:(714)565·1881
|
||
COLORADO
|
||
Cramer/Denver
|
||
5465E.EvansPI.atHudson
|
||
Denver80222
|
||
Tel:(303)758-2100
|
||
Hamilton/Avnet Electronics
|
||
5921No.Broadway
|
||
Denver80216
|
||
Tel:(303)534-1212
|
||
NEWMEXICO
|
||
Hamilton/Avnet Electronics
|
||
2450BaylorDrive.S.E.
|
||
Albuquerque 87119
|
||
Tel:(505)765·1500
|
||
Cramer/New Mexico
|
||
137Vermont, N.E.
|
||
Albuquerque 87108
|
||
Tel:(505)265-5767
|
||
OREGON
|
||
Almac/Stroum Electronics
|
||
4475S.W.SchollsFerryRd.
|
||
Portland 97225
|
||
Tel:(503)292-3534
|
||
UTAH
|
||
Cramer/Utah
|
||
391W.2500South
|
||
SaltLakeCity84115
|
||
Tel:(801)487-4131
|
||
Hamilton/Avnet Electronics
|
||
647W.BillinisRoad
|
||
SaltLakeCity84119
|
||
Tel:(801)262-8451
|
||
WASHINGTON
|
||
Hamilton/Avnet Electronics
|
||
13407Northrup Way
|
||
Bellevue 98005
|
||
Tel:(206)746·8750
|
||
Almac/Stroum Electronics
|
||
5811SixthAve.South
|
||
Seattle98108
|
||
Tel:(206)763-2300
|
||
Cramer/Seattle
|
||
5602SixthAve.South
|
||
Seattle98108
|
||
Tel:(206)762·5755MID-AMERICA
|
||
INDIANA
|
||
Sheridan Associates. Inc.
|
||
4002Medows Dr.
|
||
Indianapolis 46205
|
||
Tel:(317)547-7777
|
||
ILLINOIS
|
||
Cramer/Chicago
|
||
1911So.BusseRd.
|
||
Mt.Prospect 60056
|
||
Tel:(312)593-8230
|
||
Hamilton/Avnet Electronics
|
||
3901No.25thAve.
|
||
SchillerPark60176
|
||
Tel:(312)678-6310
|
||
KANSAS
|
||
Hamilton/Avnet Electronics
|
||
37lenexaIndustrial Center
|
||
9900PlIummRoad
|
||
Lenexa66215
|
||
Tel:(913)888-8900
|
||
Sheridan Associates. Inc.
|
||
10100SantaFeDr.
|
||
Mark1Bldg.•Suite101
|
||
Overland Park66212
|
||
Tel:(913)383·1636
|
||
MICHIGAN
|
||
Sheridan SalesCo.
|
||
24543Indoplex Drive
|
||
Farmington Hills48024
|
||
Tel:(313)477-3800
|
||
Cramer/Detroit
|
||
13193WayneRoad
|
||
Livonia48150
|
||
Tel:(313)425·7000
|
||
TWX:810-242-2985
|
||
Hamilton/Avnet Electronics
|
||
12870Farmington Road
|
||
Livonia48150
|
||
Tel:(313)522-4700
|
||
TWX:810-242-8775
|
||
MINNESOTA
|
||
Industrial Components. Inc.
|
||
5280West74thStreet
|
||
Minneapolis 55435
|
||
Tel:(612)831-2666
|
||
Cramer/Bonn
|
||
7275BushLakeRoad
|
||
Edina55435
|
||
Tel:(612)835-7811
|
||
Hamilton/Avnet Electronics
|
||
7683Washington AvenueSo.
|
||
Edina55435
|
||
Tel:(612)941-3801
|
||
MISSOURI
|
||
Hamilton/Avnet Electronics
|
||
364Brookes Lane
|
||
Hazelwood 63042
|
||
Tel(314)731-1144
|
||
Sheridan SalesCo.
|
||
110SouthHighway 140,Suite10
|
||
Florissant 63033
|
||
Tel:(314)837·5200
|
||
OHIO
|
||
Hamilton/Avnet Electronics
|
||
118Westpark Road
|
||
Dayton45459
|
||
Tel:(513)433-0610
|
||
TWX:810-450-2531
|
||
Sheridan SalesCo.
|
||
10Knollcrest Drive
|
||
Cincinnati 45222
|
||
Tel:(513)761-5432
|
||
TWX:810-461-2670
|
||
Cramer/Cleveland
|
||
5835HarperRoad
|
||
Cleveland 44139
|
||
Tel:(216)248·8400
|
||
TWX:810-427-9407
|
||
Hamilton/Avnet Electronics
|
||
761BetaDrive
|
||
Cleveland 44143
|
||
Tel:(216)461-1400
|
||
Cramer/Tri States.Inc.
|
||
666RednaTerrace
|
||
Cincinnati 45215
|
||
Tel.(513)771-6441
|
||
TWX:810-461-2882
|
||
Sheridan SalesCo.
|
||
23224Commerce ParkRoad
|
||
Beachwood 44122
|
||
Tel:(216)831-0130
|
||
Sheridan SalesCo.
|
||
ShilohBuilding, Suite250
|
||
5045NorthMainStreet
|
||
Dayton45405
|
||
Tel:(513)277-8911
|
||
TEXAS
|
||
CramerElectronics
|
||
2970Blystone
|
||
Dallas75220
|
||
Tel:(214)350-1355
|
||
Hamilton/Avnet Electronics
|
||
4445SigmaRoad
|
||
Dallas75240
|
||
Tel:(214)661-8661
|
||
Hamilton/Avnet Electronics
|
||
1216W.Clay
|
||
Houston 77019
|
||
Tel:(713)526-4661
|
||
Component Specialties, Inc.
|
||
10907ShadyTrail,Suite101
|
||
Dallas75220
|
||
Tel:(214)357-4576
|
||
Component Specialties, Inc.
|
||
7313Ashcroft Street
|
||
Houston 77036
|
||
Tel:(713)771-7237
|
||
WISCONSIN
|
||
Cramer/Wisconsin
|
||
430WestRawsonAvenue
|
||
OakCreek53154
|
||
Tel:(414)764-1700NORTHEAST
|
||
CONNECTICUT
|
||
Cramer/Connecticut
|
||
35DodgeAvenue
|
||
NorthHaven06473
|
||
Tel:(203)239-5641
|
||
Hamilton/Avnet Electronics
|
||
643Danbury Road
|
||
Georgetown 06829
|
||
Tel:(203)762-0361
|
||
MARYLAND
|
||
Cramer/EWBaltimore
|
||
7255Standard Drive
|
||
Hanover 21076
|
||
Tel:(301)796-5790
|
||
Cramer/EWWashington
|
||
16021Industrial Drive
|
||
Gaithersburg 20760
|
||
Tel:(301)948-0110
|
||
Hamilton/Avnet Eleclronics
|
||
7255Standard Drive
|
||
Hanover 21076
|
||
Tel:(301)796-5000
|
||
MASSACHUSETTS
|
||
CramerElectronics Inc.
|
||
85WellsAvenue
|
||
Newton02159
|
||
Tel:(617)969-7700
|
||
Hamilton/Avnet Electronics
|
||
185Cambridge Street
|
||
Burlington 01803
|
||
Tel:(617)273-2120
|
||
NEWJERSEY
|
||
Cramer/Pennsylvania, Inc.
|
||
12Springdale Road
|
||
CherryHillIndustrial Center
|
||
CherryHill08003
|
||
Tel:(609)424-5993
|
||
TWX:710-896-0908
|
||
Hamilton/Avnet Electronics
|
||
218LittleFallsRoad
|
||
CedarGrove07009
|
||
Tel:(201)239-0800
|
||
TWX:710-994-5787
|
||
Cramer/New Jersey
|
||
No.1BarrettAvenue
|
||
Moonachie 07074
|
||
Tel:(201)935-5600
|
||
Hamilton/Avnet Electronics
|
||
113GaitherDrive
|
||
EastGateIndustrial Park
|
||
Mt.Laurel08057
|
||
Tel:(609)234-2133
|
||
TWX:710-897-1405
|
||
NEWYORK
|
||
Cramer/Binghamton
|
||
3220WatsonBoulevard
|
||
Endwell13760
|
||
Tel.(607)754-6661
|
||
Cramer/Rochester
|
||
3000WintonRoadSouth
|
||
Rochester 14623
|
||
Tel:(716)275-0300
|
||
Hamilton/Avnet Electronics
|
||
167ClayRoad
|
||
Rochester 14623
|
||
Tel:(716)442-7820
|
||
Cramer/Syracuse
|
||
6716JoyRoad
|
||
EastSyracuse 13057
|
||
Tel:(315)437-6671
|
||
Hamilton/Avnet Electronics
|
||
6500JoyRoad
|
||
E.Syracuse 13057
|
||
Tel:(315)437-2642
|
||
Cramer/Long Island
|
||
29OserAvenue
|
||
Hauppauge, L.J.11787
|
||
Tel:(516)231-5600
|
||
TWX:510-227-9863
|
||
Hamilton/Avnet Electronics
|
||
70StateStreet
|
||
Westbury, L.I.11590
|
||
Tel:(516)333-5800
|
||
TWX:510-222-8237
|
||
PENNSYLVANIA
|
||
Sheridan SalesCo.
|
||
1717PennAvenue, Suite5009
|
||
Pittsburgh 15221
|
||
Tel:(412)244-1640
|
||
CramerElectronics
|
||
616BeattyDrive
|
||
Monroeville 15146
|
||
Tel:(412)242-7410SOUTHEAST
|
||
ALABAMA
|
||
Cramer/EW Huntsville. Inc.
|
||
2310BobWallace Avenue.S.W.
|
||
Huntsville 35805
|
||
Tel:(205)539-5722
|
||
Hamilton/Avnet Electronics
|
||
805OsterDriveNW
|
||
Huntsville 35805
|
||
Tel:(205)533-1170
|
||
FLORIDA
|
||
Cramer/E.W. Hollywood
|
||
4035No.29thAvenue
|
||
Hollywood 33020
|
||
Tel:(305)923·8181
|
||
Hamilton/Avnet Electronics
|
||
4020No.29thAve.
|
||
Hollywood 33021
|
||
Tel:(305)925-5401
|
||
Cramer/E.W.Orlando
|
||
345No.GrahamAve.
|
||
Orlando 32814
|
||
Tel:(305)894-1511
|
||
GEORGIA
|
||
Cramer/EW Atlanta
|
||
3923OakcliffIndustrial Center
|
||
Atlanta30340
|
||
Tel:(404)448-9050
|
||
Hamilton/Avnet Electronics
|
||
6700I85.AccessRoad,Suite2B
|
||
Norcross 30071
|
||
Tel:(404)448-0800
|
||
NORTH CAROLINA
|
||
CramerElectronics
|
||
938BurkeStreet
|
||
Winston-Salem 27102
|
||
Tel:(919)725-8711
|
||
CANADA
|
||
ALBERTA
|
||
L.A.VarahLtd.
|
||
474214thStreetN.E.
|
||
CalgaryT2E6LT
|
||
Tel:(403)276-8818
|
||
Telex:138258977
|
||
BRITISH COLUMBIA
|
||
L.A.VarahLtd.
|
||
2077AlbertaStreet
|
||
Vancouver 10
|
||
Tel:(604)873·3211
|
||
ONTARIO
|
||
Cramer/Canada
|
||
920AlnessAvenue, UnitNo.9
|
||
Downsview
|
||
Toronto392
|
||
Tel:(416)661-9222
|
||
TWX:610-492-6210
|
||
Hamilton/Avnet Electronics
|
||
6291-16DormanRoad
|
||
Mississauga l4V1H2
|
||
Tel:(416)677-7432
|
||
TWX:610-492·8867
|
||
Hamilton! AvnetElectronics
|
||
1735CourtwOOd Cresco
|
||
OttawaK2C3J2
|
||
Tel:(613)226-1700
|
||
TWX:610562-1906
|
||
QUEBEC
|
||
Hamilton/Avnet Electronics
|
||
2670Paulus
|
||
SI.LaurentH451G2
|
||
Tel:(514)331-6443
|
||
TWX:610-421-3731
|
||
|
||
===PAGE 252===
|
||
|
||
|
||
===PAGE 253===
|
||
NOTES: _
|
||
|
||
===PAGE 254===
|
||
|
||
|
||
===PAGE 255===
|
||
NOTES: _
|
||
|
||
===PAGE 256===
|
||
|
||
|
||
===PAGE 257===
|
||
NOTES: _
|
||
|
||
===PAGE 258===
|
||
INSTRUCTION SET
|
||
Summary ofProcessor Instructions
|
||
Instruction Code11J Clock(2) Instruction Code11J Clock(2)Mnemonic Description 0706Os0403020,DoCycles Mnemonic Description 0706Os04 03 02 0,DoCycles
|
||
MOVr1•r2Moveregistertoregister 0 1 0 0 0 S S S 5 RZ Returnonzero 0 0 '10 0 0 5/11MOVM.r Moveregistertomemory 01110SS S 7 RNZ Returnonnozero 0 0 0 0C05/11MOVr.M Movememorytoregister 0 1 0 0 0 1107 RP Returnonpositive 1100005/11HLT Halt 01 1 101107 RM Returnonminus 11 10 0 0 5/11MVIrMoveimmediate register 0000 01 107 RPE Returnonparityeven 1010 0 0 5/11MVIM Moveimmediate memory 0 0 1 1 011010 RPO Returnonparityodd 10 0 0 0 05/11tNRrIncrement register 000 0 0 10 0 5 RST Restart A A A 1 1111OCRrDecrement register 000 0 0 10 1 5 IN Input 01 101 1 10INRMIncrement memory 0 0 1 1 010010 OUT Output 0 1 0 01110
|
||
OCRMDecrement memory 0 0 1 1 0 1 0110 LXIBLoadImmediate register 0 0 0 0 0110AOOr AddregistertoA 10 0 0 0 S S S 4 PairB&C
|
||
AOCr AddregistertoAwithcarry 10 0 0 1 SSS4 LXIO Loadimmediate register 10
|
||
SUBrSubtractregisterfromA 10010S S S 4 Pair0 &E
|
||
SBBrSubtractregisterfromA 1001 1SS S 4 LXIHLoadimmediate register 10
|
||
withborrow PairH&L
|
||
ANAr AndregisterwithA 0 SS LXISPLoadimmediate stackpointer 10
|
||
XRArExclusive OrregisterwithA 0 S S PUSHBPushregisterPairB&Con 11
|
||
ORArOrregisterwithA 0 S S stack
|
||
CMPr CompareregisterwithA 0 S S PUSH0PushregisterPair0 &Eon 11
|
||
ADOMAddmemorytoA 0 1 0 stack
|
||
AOCMAddmemorytoAwithcarry 0 10 PUSHHPushregisterPairH&Lon 11
|
||
SUBMSubtractmemoryfromA 0 10 stack
|
||
SBBMSubtractmemoryfromA 0 10 PUSHPSWPushAandFlags 11
|
||
withborrow onstack
|
||
ANAMAndmemorywithA POPBPopregisterpairB&Coff 10
|
||
XRAMExclusive OrmemorywithA stack
|
||
ORAMOrmemorywithA POP0Popregisterpair0 &Eoff 10
|
||
CMPM ComparememorywithA stack
|
||
AOI Addimmediate toA POPHPopregisterpairH&Loff 10
|
||
ACI Addimmediate toAwith stack
|
||
carry POPPSWPopAandFlags 10
|
||
SUI Subtractimmediate fromA offstack
|
||
SBI Subtractimmediate fromA STA StoreAdirect 0 13
|
||
withborrow LOA LoadAdirect 0 13
|
||
ANI Andimmediate withA XCHG Exchange 0 &E.H&L 0 4
|
||
XRI Exclusive Orimmediate with Registers
|
||
A XTHL Excnangetopofstack,H&L 11 1 0 0 0 1 1 18
|
||
ORI Orimmediate withA 11 1 0 7 SPHL H&Ltostackpointer 1 1 1 1 1 00 1 5
|
||
CPt Compareimmediate withA1 1 1 1 7 PCHL H&Ltoprogramcounter 11 1 0 1 0 0 1 5
|
||
RLC RotateAleft 0 0 0 0 4 DADBAddB&CtoH&L 0 0 0 0 10 0 1 10
|
||
RRC RotateAright 0 0 0 1 4 DAD0AddD&EtoH&L (l0 0 1 1 0 0 1 10
|
||
RAL RotateAleftthroughcarry 00 0 0 4 DADHAddH&LtoH&L 0010 1 0 0 1 10
|
||
RAR RotateArightthrough 0 0 0 1 4 DADSPAddstackpointertoH&L 0 0 1 1 1 0 0110
|
||
carry STAXBStoreAindirect 000 0 0 0 107
|
||
JMP Jumpunconditional 00001110 STAX0StoreAindirect 00 0 10 0107
|
||
JC Jumponcarry 01 101010 LOAXBLoadAindirect 0 0 0 0 10 1 0 7
|
||
JNC Jumponnocarry 01001 0 10 LOAX0LoadAindirect 0 0 0 1 1 0107
|
||
JZ Jumponzero 0 0 1 0 1 010 INXBIncrement B&Cregisters 0 0 0 0 0 01 1 5
|
||
JNZ Jumponnozero 0 0 0 01 0 10 INX0Increment 0 &Eregisters 0 0 0 1 0 0 1 1 5
|
||
JP Jumponpositive 110 01010 INXHIncrement H&Lregisters 00 1 0 0 0 1 1 5
|
||
JM Jumponminus 11101010 INXSPIncrement stackpointer 0 0 110 0115
|
||
JPE Jumponparityeven 1 0 101 0 10 OCXBDecrement B&C 00 0 0 101 1 5
|
||
JPO Jumponparityodd 10 001010 OCX0Decrement 0 &E 0 0 0 110115
|
||
CALL Callunconditional 0 0 110117 OCXHDecrement H&L 0 0 1010115
|
||
CC Calloncarry 01 1 1 0 0 11/17 OCXSPDecrement stackpointer 0 0 1 1 1. 0115
|
||
CNC "Callonnocarry 01010 0 11/17 CMA Complement A 001011114
|
||
CZ Callonzero 0 0 110011/17 STC Setcarry 001 1 0 1 1 1 4
|
||
CNZ Callonnozero 0 0 0 10011/17 CMC Complement carry 001 1 1 11 1 4
|
||
CP Callonpositive 1 1 01 0011/17 OAA DecimaladjustA 00100 1114
|
||
CM Callonminus 11110 0 11/17 SHLO StoreH&Ldirect 0 010 0 0 1016
|
||
CPE Callonparityeven 101 10 0 11/17 LHLO LoadH&Ldirect 0 0 10101016
|
||
CPO Callonparityodd 10010 0 11/17 EI EnableInterrupts 1111 101 1 4
|
||
RET Return 0010 0110 01 Disableinterrupt 11110 01 1 4
|
||
RC Returnoncarry 01 10 005/11 NOP No-operation 00 0 0 0 0 0 04
|
||
RNC Returnonnocarry 0100005/11
|
||
NOTES: 1.DODorSSS-000B -001C -0100 -011E -100H -101L -110Memory -111A.
|
||
2.Twopossiblecycletimes,(5/11)indicateinstruction cyclesdependent oncondition flags.
|
||
|
||
===PAGE 259===
|
||
~
|
||
INSTRUCTION SET
|
||
Summary ofProcessor Instructions
|
||
ByAlphabetical Order
|
||
Instrumon Cod.lll Clock121 Illstrudion Cod.(1) C1cckl2J
|
||
Mnemonic Desaiptioll 07060504030201DOCychs Mn.mollie Description 070605 04 03 02 01DoCychs
|
||
ACI Addimmediate toAwith MVIM Moveimmediate memory 1 1 0 1 1 010
|
||
tarry MVlr Moveimmediate register D D 01107
|
||
AOCM AddmemorytoAwithtarry10 0 01 1 7 MOVM.r Moveregistertomemory 11 0 S S S 7
|
||
ADCr AddregistertoAwithcarry 10 0 D1S 4 MOVr,M Movememorytoregister 0 D 0 1 1 07
|
||
ADDM AddmemorytoA 10 0 0 0 1 7 MOVrt,r2Moveregistertoregister 0 D 0 SS S 5
|
||
AOOr AddregistertoA 100 0 0 S 4 NOP No-operation 0 0 0 0 0 0 4
|
||
AOI Addimmediate toA 1 1 0 0 0 1 7 DRAM OrmemorywithA 1 1 0 1 1 0 7
|
||
ANAM AndmemorywithA 1 0 1 001 7 ORAr OrregisterwithA 1 1 0 S S S 4
|
||
ANAr AndregisterwithA 10100 S 4 ORI Orimmediate withA 1 1 0 1 1 07
|
||
ANI Andimmediate withA 1 1 10 0 1 7 OUT Output 010 0 1110
|
||
CALL CallullCondi1ional 1 1 0 0 1 1 17 PCHL H&Ltoprogramcounter 1010015
|
||
CC Calloncarry 1 1 011 1 11/17 POP8 Popregi$terpaira&Coff 00 0 0 0 1 10
|
||
CM Callonminus 1 1 1 1 1 I 11/17 stick
|
||
Cl1A Compliment A 0 0 10 1 1 4 pop0 Popregisterpair0&Eoff 10
|
||
CMC Compliment carry 00111 1 4 stack
|
||
CMPM ComparememorywithA 101 1 I1 7 POPH PopregisterpairH&Loff 10
|
||
CMPr CompareregisterwithA 1011 1 S 4 stack
|
||
CNC Callonnocarry 11010 1 11/17 POPPSW PopAandFlags 10
|
||
CNZ Callonnolero 1 1 00 0 1 11/17 allstack
|
||
CP Callonpositive 1 1 1 1 01 11/17 PUSH8 PushregisterPair8&Con 11
|
||
CPE Callonparityeven 1 1 1 011 11/17 stack
|
||
CPI Compareimmediate withA11 1 1 1 1 7 PUSH0 PushregisterPair0&Eon 11
|
||
CPO Callonparityodd 11 1 001 11/17 stack
|
||
CZ CallOnltrO 110 0 1 1 11/17 PUSHH PushregisterPairH&Lon 11
|
||
DAA DecimaladjustA 0 0 1 0 01 4 stack
|
||
DADa Adda&CtoH&L 00 0 0 1 0 10 PUSHPSW PushAandFlags 11
|
||
DAD0 Add0&EtoH&L 0 0 0 1 1 0 10 onstack
|
||
DADH AddH&LtoH&L 0010 1 0 10 RAL RotlleAleftthroughcarry
|
||
DADSP AddstackpointertoH&L001 1 10 10 RAR RolateArightthrough
|
||
OCRM Decrement memory 0 0 1101 10 carry
|
||
OCRr Decrement register 0 0 0 D 0 1 5 RC Returnoncarry 011 0 5'11
|
||
DCX8 Decrement B&C 00 0 010 5 RET Return 00I 0 10
|
||
DCXD Decrement 0&E 0 0 0 1 10 5 RLC RotateAleft 00 0 1 4
|
||
OCXH Decrement H&L 0 0 1 0 1 0 5 RM Returnonminus 11 1 0 5'11
|
||
OCXSP Decrement stackpointer 0011 1 0 5 RNC Returnonnocarry 0 1 0 0 5'11
|
||
01 DisableInterrupt 11 1 10 0 4 RNZ Returnonnolero 00 0 0 5'11
|
||
EI EnableInterrupts I11 1 1 0 4 RP Relurnonpositive 110 0 5111
|
||
HLT Halt 011 1 0 1 0 7 RPE Returnonparityeven 10 1 0 5'11
|
||
IN Input 11 0 1 10 110 RPO Returnonparityodd 10 0 0 5'11
|
||
INRM Increment memory 001 1 0 1 010 RRC RotateAright 0 0 1 1 4
|
||
INRr Incrementregister 000 0 D 1 0 5 RST Restart A A A 1 11
|
||
INX8 Increment a&Cregisters 0 0 0 0 0 0 1 5 RZ Returnonlero 0 0 1 0 5'11
|
||
INX0 Increment 0&Eregisters 0 0 0 100 15 SaBM SubtractmemoryIromA 0 1 1 1 7
|
||
INXH Increment H&Lregisters 0010 0 0 1 5 withborrow
|
||
INXSP Increment stackpointer 0 0 1 1 0 0 1 5 SBar SubtractregisterfromA
|
||
JC Jumponcarry 1 1 0110 0 10 withborrow
|
||
JM Jumponminus 1I11 1 0 0 10 S81 Subtractimmediate fromA
|
||
JMP Jumpunconditional 1 1 0 0 0 0 110 withborrow
|
||
JNC Jumponnocarry 1 1 010 0 0 10 SHLO SloreH&Ldirect 0 016
|
||
JNZ Jumponnolero 1 1 00 0 0 0 10 SPHL H&Ltostackpointer 0 1 5
|
||
JP Jumponpositive 1 1 1 1 0 0 0 10 STA StoreAdirect 0 013
|
||
JPE Jumponparityeven 11 1 010 0 10 STAX8SloreAindirect 0 07
|
||
JPO Jumponparityodd 1 1 100 0 0 10 STAX0 StoreAindirect 0 07
|
||
JZ Jumponlero 1100 1 0 0 10 STC SelClIrry 1 14
|
||
LOA LoadAdirect 0 0 1 1 10 0 13 SUBM SubtractmemoryfromA 1 0 7
|
||
LOAXa LoadAindirect 0 0 00 1 0 0 7 SU8r SubtractregisterIramA S S 4
|
||
LOAX0 LoadAindirect 00 0 1 10 07 SUI Subtrlctimmediate fromA 1 07
|
||
LHLD LoadH&Ldinct 00 1 010 0 16 XCHG Exchange0&E.H&L 0 14
|
||
LXI8 Loadimmediate register 00 0 0 0 0 110 Registers
|
||
Paira&C XRAM Exclusive OrmemorywithA
|
||
LXIO Loadimmediate register 10 XRAr Exclusive OrregisterwithA
|
||
Pair0&E XRI Exclusive Orimmediate with
|
||
LXIH Loadimmediate register 10 A
|
||
PairH&L XTHL Exchange top01stack,H&L 18
|
||
LXISP Loadimmediatesteckpointer 10
|
||
NOTES:1.0DOorSSS-000B-001C -0100 -011E -1OOH-101L-110Memory -111A.
|
||
2.Twopossiblecycletimes,(5/11)indicate instruction cyclesdependent oncondition flags.
|
||
|
||
===PAGE 260===
|
||
DearCustomer,
|
||
Pleasefilloutthecardbelowcompletely tomake
|
||
sureyournameisenteredaccurately ontheMCS-BO
|
||
Registered UsersList.Thisassuresyouofgettingthe
|
||
latestinformation onallnewMCS-BOProductDevelop
|
||
mentsandApplication Literature.
|
||
Anycomments orsuggestions regarding
|
||
MCS-BOwouldbeappreciated.
|
||
Sincerely,
|
||
KenMcKenzie
|
||
MCS-BOProductManager
|
||
8080 MICROCOMPUTER SYSTEM
|
||
USERSREGISTRATION CARD
|
||
(PleasePrint)
|
||
Name .,..-__
|
||
Title _
|
||
Company ~__---------_
|
||
Address -"'- --==__
|
||
City _
|
||
MailStop _
|
||
ApplicationState _
|
||
ZipCode _
|
||
Peripherals
|
||
DFloppyDiskDLinePrinter DStepper
|
||
DMagCassette DKeyboard DServo
|
||
DPaperTape Other:
|
||
ROM kBytes RAM kBytes
|
||
Inports Outports
|
||
DMAChan~els# Interrupts#
|
||
Communication InterfaceD
|
||
ASYNCD BaudRate
|
||
SYNCD BaudRate
|
||
SDLCD BaudRate
|
||
OTHERD BaudRate
|
||
|
||
===PAGE 261===
|
||
··1cc
|
||
@BJ
|
||
lt~.-eE
|
||
.S=!~:s..c
|
||
LCINTELCORPORATION
|
||
Microcomputer Systems
|
||
3065BowersAvenue
|
||
SantaClara,CA95051PLACE
|
||
STAMP
|
||
HERE
|
||
|
||
===PAGE 262===
|
||
inter
|
||
INTELCORPORATION 3065BowersAvenue, SantaClara.California 95051(408)246-7501
|
||
PrimedinU.5.A.fMC5-662-Q975/40K |