# Intel 8282 / 8283 Octal Latch — Pinout

Source: Intel datasheet reproduced as **Appendix B of *The 8086 Family
User's Manual*, October 1979** (`pdfs/iapx_86_88_users_manual.pdf`,
PDF pp.601-604, manual pp.B-59 to B-62). 8-bit bipolar latch with 3-state
output buffer; 20-pin DIP, 0.3" centers. **8282 = non-inverting**, **8283
= inverting**; pin compatible.

## Pin Table (20-pin DIP)

| Pin | Name | I/O | Pin | Name | I/O |
|----:|------|-----|----:|------|-----|
| 1   | DI0  | In  | 20  | Vcc  | +5V |
| 2   | DI1  | In  | 19  | DO0  | Out |
| 3   | DI2  | In  | 18  | DO1  | Out |
| 4   | DI3  | In  | 17  | DO2  | Out |
| 5   | DI4  | In  | 16  | DO3  | Out |
| 6   | DI5  | In  | 15  | DO4  | Out |
| 7   | DI6  | In  | 14  | DO5  | Out |
| 8   | DI7  | In  | 13  | DO6  | Out |
| 9   | OE̅  | In (active LOW) | 12 | DO7 | Out |
| 10  | GND  | 0V  | 11  | STB  | In (active HIGH) |

Pin order taken from the "PIN CONFIGURATIONS" diagram on PDF p.601 / manual
p.B-59. The figure labels DI0-DI7 along the left edge (pins 1-8), OE̅ at pin 9,
GND at pin 10, STB at pin 11, DO7-DO0 going up the right edge.

## Truth Table (manual pp.B-59 to B-60, "OPERATIONAL DESCRIPTION")

| OE̅ | STB | DO0-DO7 (8282) | Notes |
|----|-----|----------------|-------|
| L  | H   | = DI0-DI7 (transparent) | Latch follows input |
| L  | H→L | = DI at falling edge (latched) | Data captured on H→L of STB |
| L  | L   | = last latched value | Hold |
| H  | x   | Hi-Z | Output buffers tristated |

The 8283 is identical except DOn = NOT(DIn). Setup time DI→STB↓ = 0 ns,
hold = 25 ns, STB high time ≥ 15 ns; STB→DO 35/45 ns (8282/8283), input→DO
in transparent mode 25/45 ns; OE̅↓→DO ≤ 50 ns; OE̅↑→Hi-Z ≤ 25 ns
(A.C. table, PDF p.603 / manual p.B-61).

In an 8086 minimum-mode system, STB ties to ALE and OE̅ ties to GND so the
latch is always enabled and captures AD15-AD0 + A19-A16 + BHE on the trailing
edge of ALE in T1 (per iAPX manual fig. 4-11, PDF p.247).