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Commit Graph

Author	SHA1	Message	Date
David Montero	7ac17ff2b6	test_intel: fix 8086 MOV r/m,imm encoding (0xC6/0xC7) Root cause of the deferred CALL/RET test: my chip was missing the 0xC6 / 0xC7 (Group 11 — MOV r/m, imm) opcodes. Bytes like the test's "MOV byte [0x8002], 0x55" (0xC6 0x06 0x02 0x80 0x55) fell through to the default NOP, then the chip decoded the residual 0x06 0x02 0x80 0x55 as PUSH ES + ADD r/m + ... taking SP into unpredictable territory. Implementation: - 0xC6 (8-bit) and 0xC7 (16-bit) variants added. - The encoding is opcode + modrm + disp + imm. Critically the disp bytes (consumed by calc_ea) come BEFORE the immediate, so we compute EA first, then fetch imm. Earlier draft had imm fetched before disp — that had imm winning the disp slot and disp becoming the next instruction's bytes. Caught only after wiring CALL+RET. Tests: 8086 10→11 passing. Total test_intel: 93→94 passing, 0 failed, 11 todo. CALL/RET integration test now active and green. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>	2026-04-30 20:44:17 +02:00
David Montero	d2118b298e	test_intel: phase E — 8086 ISA expansion Adds ~600 LOC to 8086.c bringing the chip from ~50 opcodes to a near-complete subset of the iAPX 86 ISA: - Shift/rotate Group 2 (D0..D3) — ROL/ROR/RCL/RCR/SHL/SHR/SAR with imm-1 or CL count, full CF + OF + S/Z/P semantics. - String ops MOVS/CMPS/SCAS/LODS/STOS (byte + word) with REP/REPE/ REPNE prefix loop; DF-respecting SI/DI advance. - MUL/IMUL/DIV/IDIV (Group 3 sub-opcodes 4-7) with divide-error halt. - BCD: DAA/DAS/AAA/AAS/AAM/AAD with manual-canonical algorithms. - Port I/O: IN/OUT byte+word, immediate or DX-indexed. - Hardware interrupts: NMI rising → vector 2, INTR + IF → INTA cycle reading vector byte from data bus, INT imm8/3, INTO, IRET. - LDS/LES, LAHF/SAHF, XCHG byte+word, XLAT. - Group 4 (FE) INC/DEC r/m8 (was missing). - PUSH/POP segment regs (06/0E/16/1E + 07/17/1F). - Undocumented: POP CS (0F), SALC (D6). - TEST r/m,r and TEST AL/AX,imm (84/85/A8/A9 — also missing baseline). New harness: - BoardHarness.installFake8086Bus() — full 8086 minimum-mode bus responder: ALE-snapshot + RD-drive + WR-latch. - boot8086() helper in 8086.test.js placing test bytes at physical 0xF0100 with reset-vector JMP-FAR stub. Tests: 8086 3→10 passing (+7: MOV imm16, ADD, JMP near, SHL, MUL, REP MOVSB, segment override). Total test_intel: 86→93 passing, 0 failed, 12 todo. CALL/RET test deferred to it.todo — chip takes an unintended path after the CALL push (debug ongoing). Master plan doc updated. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>	2026-04-30 20:44:17 +02:00
David Montero	a8c25a8f5a	autosearch — Research notes for Intel + Z80 custom-chip emulation	2026-04-30 00:27:39 -03:00

Author

SHA1

Message

Date

David Montero

7ac17ff2b6

test_intel: fix 8086 MOV r/m,imm encoding (0xC6/0xC7)

Root cause of the deferred CALL/RET test: my chip was missing the
0xC6 / 0xC7 (Group 11 — MOV r/m, imm) opcodes. Bytes like the
test's "MOV byte [0x8002], 0x55" (0xC6 0x06 0x02 0x80 0x55) fell
through to the default NOP, then the chip decoded the residual
0x06 0x02 0x80 0x55 as PUSH ES + ADD r/m + ... taking SP into
unpredictable territory.

Implementation:
- 0xC6 (8-bit) and 0xC7 (16-bit) variants added.
- The encoding is opcode + modrm + disp + imm. Critically the disp
  bytes (consumed by calc_ea) come BEFORE the immediate, so we
  compute EA first, then fetch imm. Earlier draft had imm fetched
  before disp — that had imm winning the disp slot and disp becoming
  the next instruction's bytes. Caught only after wiring CALL+RET.

Tests: 8086 10→11 passing. Total test_intel: 93→94 passing,
0 failed, 11 todo. CALL/RET integration test now active and green.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

2026-04-30 20:44:17 +02:00

David Montero

d2118b298e

test_intel: phase E — 8086 ISA expansion

Adds ~600 LOC to 8086.c bringing the chip from ~50 opcodes to a
near-complete subset of the iAPX 86 ISA:
- Shift/rotate Group 2 (D0..D3) — ROL/ROR/RCL/RCR/SHL/SHR/SAR with
  imm-1 or CL count, full CF + OF + S/Z/P semantics.
- String ops MOVS/CMPS/SCAS/LODS/STOS (byte + word) with REP/REPE/
  REPNE prefix loop; DF-respecting SI/DI advance.
- MUL/IMUL/DIV/IDIV (Group 3 sub-opcodes 4-7) with divide-error halt.
- BCD: DAA/DAS/AAA/AAS/AAM/AAD with manual-canonical algorithms.
- Port I/O: IN/OUT byte+word, immediate or DX-indexed.
- Hardware interrupts: NMI rising → vector 2, INTR + IF → INTA cycle
  reading vector byte from data bus, INT imm8/3, INTO, IRET.
- LDS/LES, LAHF/SAHF, XCHG byte+word, XLAT.
- Group 4 (FE) INC/DEC r/m8 (was missing).
- PUSH/POP segment regs (06/0E/16/1E + 07/17/1F).
- Undocumented: POP CS (0F), SALC (D6).
- TEST r/m,r and TEST AL/AX,imm (84/85/A8/A9 — also missing baseline).

New harness:
- BoardHarness.installFake8086Bus() — full 8086 minimum-mode bus
  responder: ALE-snapshot + RD-drive + WR-latch.
- boot8086() helper in 8086.test.js placing test bytes at physical
  0xF0100 with reset-vector JMP-FAR stub.

Tests: 8086 3→10 passing (+7: MOV imm16, ADD, JMP near, SHL, MUL,
REP MOVSB, segment override). Total test_intel: 86→93 passing,
0 failed, 12 todo.

CALL/RET test deferred to it.todo — chip takes an unintended path
after the CALL push (debug ongoing). Master plan doc updated.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

2026-04-30 20:44:17 +02:00

David Montero

a8c25a8f5a

autosearch — Research notes for Intel + Z80 custom-chip emulation

2026-04-30 00:27:39 -03:00

3 Commits