From 9d5d2e8a4af54ba062e7b26a93de7fc52c57618c Mon Sep 17 00:00:00 2001 From: davidmonterocrespo24 Date: Thu, 7 May 2026 21:56:29 +0200 Subject: [PATCH] fix(docs): RISC-V emulation goes through QEMU, not a TypeScript browser core MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The marketing copy and docs claimed ESP32-C3 / XIAO-C3 / SuperMini / CH32V003 ran on a "browser-native RV32IMC core written in TypeScript", but production runs through QEMU lcgamboa (libqemu-riscv32) with the esp32c3-picsimlab machine — same backend pattern as Xtensa ESP32, just a different libqemu binary. The TypeScript ISA layer (RiscVCore.ts / Esp32C3Simulator.ts / RiscVSimulator.ts) is kept only as Vitest unit-test infrastructure for RV32IMC instruction decoding; it cannot handle the 150+ ROM functions ESP-IDF needs at boot and is not wired into the production emulation path. Files updated: Marketing pages - LandingPage: board-group label, FAQ answer, architecture description no longer claim "browser-native" or "no backend needed" for RISC-V. - AboutPage: arch card retitled "RISC-V via QEMU", body explains the libqemu-riscv32 / lcgamboa backend. - Velxio2Page: arch group engine label, multi-board feature item, competitive-comparison card all corrected. - ArduinoEmulatorPage: two RISC-V cards corrected. - ESP32SimulatorPage: ESP32-C3 cross-link card corrected. - ESP32C3SimulatorPage: hero subtitle, trust strip, supported-boards intro, JSON-LD description corrected. - ElectronicsSimulatorPage: install-needed FAQ corrected. - examples.ts: c3-blink description and code-comment corrected. SEO surfaces - index.html: JSON-LD SoftwareApplication description, OS-fallback FAQ body, supported-boards