test(chipbus): live proof - a real Z80 boots from a ROM over the bus
End-to-end validation of Phases 0-2 on an actual CPU. The real Z80 (examples/intel/z80.c) and a 32K EPROM (z80-boot-rom.c, a rom-32k variant holding JP 0x0006 / HALT) are wired chip-to-chip over a shared address + data bus with no board. RD drives the ROM's OE; CE is left enabled. Booting exercises all three phases at once: the Z80 drives the address -> the ROM reacts on the shared net key (Phase 0); asserts RD -> the ROM tri-state-drives the data bus while the Z80 released it (Phase 1); and reads the data bus in the SAME tickTimers step, getting the settled byte (Phase 2 settle-before-read). The Z80 fetches C3,06,00, jumps to 0x0006, fetches 76, and HALTs -> drives HALT low, which the test observes. z80.wasm is compiled from the committed examples/intel/z80.c; the boot ROM source + chip.json live in test_custom_chips/sdk/examples. All 36 chipbus tests pass. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
David Montero Crespo
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3137c40a90
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/**
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* Phase 0-2 LIVE end-to-end proof on a REAL CPU (project/multichip-bus/).
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*
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* A real Z80 (examples/intel/z80.c) and a 32K EPROM (z80-boot-rom.c, a rom-32k
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* variant) are wired chip-to-chip over a shared address + data bus, NO board.
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* The ROM holds `JP 0x0006 / HALT`. Booting it requires the Z80 to:
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* - drive the address bus -> ROM reacts (shared net key, Phase 0);
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* - assert RD -> ROM tri-state-drives the data bus while the Z80 released it
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* (Phase 1 drive resolution);
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* - read the data bus IN THE SAME tickTimers step and get the settled byte
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* (Phase 2 settle-before-read);
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* fetch C3,06,00 (the JP + target), jump, fetch 76 at 0x0006, and HALT — which
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* drives HALT low. Observing HALT go low is the proof the whole bus works.
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*
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* Fixtures compiled with wasi-sdk (see test_intel/scripts/compile-chip.sh flags);
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* skips cleanly if absent. z80.wasm from examples/intel/z80.c; z80-boot-rom.wasm
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* from project/multichip-bus research (rom-32k with a boot image).
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*/
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import { describe, it, expect, beforeEach, afterEach } from 'vitest';
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import { readFileSync, existsSync } from 'node:fs';
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import { fileURLToPath } from 'node:url';
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import { PinManager } from '../simulation/PinManager';
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import { ChipInstance } from '../simulation/customChips/ChipRuntime';
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import {
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resolveChipNetKey,
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setChipBusEnabledForTest,
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resetChipNetIndexForTest,
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type ChipNetState,
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} from '../simulation/customChips/chipNets';
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import { syntheticChipPin } from '../simulation/customChips/syntheticPins';
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import { resetBusNets } from '../simulation/customChips/busNets';
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const z80Path = fileURLToPath(new URL('./fixtures/chipbus/z80.wasm', import.meta.url));
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const romPath = fileURLToPath(new URL('./fixtures/chipbus/z80-boot-rom.wasm', import.meta.url));
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const haveFixtures = existsSync(z80Path) && existsSync(romPath);
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const range = (n: number, from = 0) => Array.from({ length: n }, (_, i) => i + from);
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const Z80_PINS = [
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...range(16).map((i) => `A${i}`),
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...range(8).map((i) => `D${i}`),
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'M1', 'MREQ', 'IORQ', 'RD', 'WR', 'RFSH', 'HALT', 'WAIT',
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'INT', 'NMI', 'RESET', 'BUSREQ', 'BUSACK', 'CLK', 'VCC', 'GND',
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];
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const ROM_PINS = [
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...range(15).map((i) => `A${i}`),
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...range(8).map((i) => `D${i}`),
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'CE', 'OE', 'VCC', 'GND',
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];
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// The schematic: address A0..A14 and data D0..D7 straight across, plus the Z80's
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// RD strobe into the ROM's OE so the ROM only drives during reads. CE is left
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// unwired (reads 0 = always enabled).
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const STATE: ChipNetState = {
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wires: [
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...range(15).map((i) => ({
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start: { componentId: 'z80', pinName: `A${i}` },
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end: { componentId: 'rom', pinName: `A${i}` },
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})),
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...range(8).map((i) => ({
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start: { componentId: 'z80', pinName: `D${i}` },
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end: { componentId: 'rom', pinName: `D${i}` },
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})),
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{ start: { componentId: 'z80', pinName: 'RD' }, end: { componentId: 'rom', pinName: 'OE' } },
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],
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components: [
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{ id: 'z80', metadataId: 'custom-chip' },
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{ id: 'rom', metadataId: 'custom-chip' },
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],
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boards: [],
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};
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function pinKey(chipId: string, pin: string): number {
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return resolveChipNetKey(STATE, chipId, pin) ?? syntheticChipPin(chipId, pin);
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}
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function wiresFor(chipId: string, pins: string[]): Map<string, number> {
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return new Map(pins.map((p) => [p, pinKey(chipId, p)] as [string, number]));
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}
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describe.skipIf(!haveFixtures)('chipbus Phase 0-2 — a real Z80 boots from a ROM over the bus', () => {
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beforeEach(() => {
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setChipBusEnabledForTest(true);
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resetChipNetIndexForTest();
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resetBusNets();
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});
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afterEach(() => {
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setChipBusEnabledForTest(null);
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resetChipNetIndexForTest();
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resetBusNets();
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});
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it('fetches JP+HALT from the ROM across the bus and drives HALT low', async () => {
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const z80Wasm = new Uint8Array(readFileSync(z80Path));
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const romWasm = new Uint8Array(readFileSync(romPath));
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const pm = new PinManager();
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const z80 = await ChipInstance.create({
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wasm: z80Wasm, componentId: 'z80', pinManager: pm, wires: wiresFor('z80', Z80_PINS),
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});
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z80.start();
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const rom = await ChipInstance.create({
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wasm: romWasm, componentId: 'rom', pinManager: pm, wires: wiresFor('rom', ROM_PINS),
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});
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rom.start();
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const halt = pinKey('z80', 'HALT');
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// At power-on the Z80 holds HALT high (running, registered OUTPUT_HIGH).
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expect(pm.getPinState(halt)).toBe(true);
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// on_clock bails while BUSREQ/WAIT read low (unwired inputs default 0), so
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// deassert them, then release RESET (rising edge) to start the CPU.
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pm.triggerPinChange(pinKey('z80', 'BUSREQ'), true);
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pm.triggerPinChange(pinKey('z80', 'WAIT'), true);
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pm.triggerPinChange(pinKey('z80', 'RESET'), true);
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// Run the 4 MHz pseudo-clock (250 ns period) for ~200 ticks — far more than
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// the 2 instructions to reach HALT.
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z80.tickTimers(50_000n);
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// HALT went low: the Z80 executed JP 0x0006 then HALT, having correctly read
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// every byte from the ROM over the shared chip-to-chip bus.
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expect(pm.getPinState(halt)).toBe(false);
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z80.dispose();
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rom.dispose();
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});
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});
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Binary file not shown.
Binary file not shown.
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/*
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* z80-boot-rom — a rom-32k variant whose image is a tiny Z80 boot program,
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* for the Phase 0-2 live proof (project/multichip-bus/). Identical to
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* examples/intel/rom-32k.c except for rom_image, which holds:
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*
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* 0000: C3 06 00 JP 0x0006 ; requires reading C3,06,00 over the bus
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* 0003: 00 00 00 NOP x3 ; jumped over
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* 0006: 76 HALT ; Z80 drives HALT low here -> observable
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*
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* Reaching HALT proves the Z80 fetched the multi-byte JP and its target from
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* this ROM across the shared data bus and executed it.
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*/
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#include "velxio-chip.h"
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#include <stdint.h>
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#include <stdbool.h>
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#define ROM_SIZE 0x8000 /* 32 KB */
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static const uint8_t rom_image[ROM_SIZE] = {
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[0x0000] = 0xC3, [0x0001] = 0x06, [0x0002] = 0x00, /* JP 0x0006 */
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[0x0003] = 0x00, [0x0004] = 0x00, [0x0005] = 0x00, /* NOP NOP NOP */
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[0x0006] = 0x76, /* HALT */
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};
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typedef struct {
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vx_pin a[15];
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vx_pin d[8];
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vx_pin ce;
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vx_pin oe;
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vx_pin vcc;
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vx_pin gnd;
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bool driving;
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} chip_t;
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static chip_t G;
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static uint16_t read_addr(void) {
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uint16_t v = 0;
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for (int i = 0; i < 15; i++) if (vx_pin_read(G.a[i])) v |= (1u << i);
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return v;
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}
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static uint8_t image_byte(uint16_t addr) {
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if (addr >= ROM_SIZE) return 0xFF;
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/* honour the programmed low bytes; an erased EPROM reads 0xFF elsewhere */
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if (addr >= 0x10) return 0xFF;
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return rom_image[addr];
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}
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static void drive_data(uint8_t v) {
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for (int i = 0; i < 8; i++) {
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vx_pin_set_mode(G.d[i], VX_OUTPUT);
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vx_pin_write(G.d[i], (v >> i) & 1);
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}
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G.driving = true;
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}
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static void release_data(void) {
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if (!G.driving) return;
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for (int i = 0; i < 8; i++) vx_pin_set_mode(G.d[i], VX_INPUT);
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G.driving = false;
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}
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static void update_outputs(void) {
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int ce_low = (vx_pin_read(G.ce) == 0);
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int oe_low = (vx_pin_read(G.oe) == 0);
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if (ce_low && oe_low) {
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drive_data(image_byte(read_addr()));
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} else {
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release_data();
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}
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}
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static void on_pin_change(void* user_data, vx_pin pin, int value) {
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(void)user_data; (void)pin; (void)value;
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update_outputs();
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}
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void chip_setup(void) {
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char name[4];
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for (int i = 0; i < 15; i++) {
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name[0]='A';
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if (i<10) { name[1]='0'+i; name[2]=0; }
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else { name[1]='1'; name[2]='0'+(i-10); name[3]=0; }
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G.a[i] = vx_pin_register(name, VX_INPUT);
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}
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for (int i = 0; i < 8; i++) {
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name[0]='D'; name[1]='0'+i; name[2]=0;
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G.d[i] = vx_pin_register(name, VX_INPUT);
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}
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G.ce = vx_pin_register("CE", VX_INPUT);
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G.oe = vx_pin_register("OE", VX_INPUT);
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G.vcc = vx_pin_register("VCC", VX_INPUT);
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G.gnd = vx_pin_register("GND", VX_INPUT);
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G.driving = false;
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for (int i = 0; i < 15; i++) {
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vx_pin_watch(G.a[i], VX_EDGE_BOTH, on_pin_change, 0);
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}
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vx_pin_watch(G.ce, VX_EDGE_BOTH, on_pin_change, 0);
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vx_pin_watch(G.oe, VX_EDGE_BOTH, on_pin_change, 0);
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update_outputs();
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}
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{
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"schema": "velxio-chip/v1",
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"name": "Z80 Boot ROM (JP+HALT)",
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"author": "Velxio",
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"license": "MIT",
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"description": "A rom-32k variant holding a tiny Z80 boot program (JP 0x0006; HALT). Fixture for the Phase 0-2 live proof that a real Z80 boots from a ROM over a chip-to-chip bus.",
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"pins": ["A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "A8", "A9", "A10", "A11", "A12", "A13", "A14", "D0", "D1", "D2", "D3", "D4", "D5", "D6", "D7", "CE", "OE", "VCC", "GND"],
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"attributes": []
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}
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