test_intel: status doc — 113/124 passing across all 14 chips

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

test/test_intel/00_README.md

@@ -117,25 +117,35 @@ address and data pins, just like in a real PCB.
 | **test_8086/**| ✅ 13  | ✅    | **🎯 3 passing + 10 todo. ~750 LOC clean-room from Intel iAPX 86,88 User's Manual (Oct 1979).** Bus protocol + reset to 0xFFFF0 + ModR/M decode + ~50 opcodes (MOV/ALU/Jcc/CALL/RET/LOOP/etc.). Deferred: string ops, MUL/DIV, BCD, port I/O, interrupts. |
 | **test_z80/**| ✅ 13  | ✅    | **🎯 11 passing + 2 todo (IM 2 vectoring, ZEXDOC). ~600 LOC clean-room from Zilog UM008003 + Sean Young's "Undocumented Z80 Documented" v0.91.** Full bus + ISA + INT + NMI + LDIR + IX/IY + EXX + IM 0/1/2. Deferred: undocumented X/Y flags, MEMPTR, full DAA, CB-prefix bit ops. |
 
-Total: **109 tests authored, 98 passing** (8080: 18 + 2 ROM-validation,
-Z80: 21 + 1 ZEXDOC + 1 hello, 4004: 9, 4040: 5, 8086: 11, rom-32k: 6,
-ram-64k: 7, latch-8282: 4, rom-1m: 4, 8255-ppi: 5, 8251-usart: 4),
-0 skipping, 11 todo, 0 failed. **All 5 retro Intel/Zilog CPUs + 6 bus
-device chips implemented and validated against public-domain test
-ROMs:**
+Total: **124 tests authored, 113 passing** across 19 test files,
+0 skipping, 11 todo, 0 failed.
 
-- **8080**: passes `8080PRE.COM` and `TST8080.COM` (Microcosm 1980 —
-  prints "CPU IS OPERATIONAL").
-- **Z80**: runs Frank Cringle's `ZEXDOC` (1994) — prints the
-  "Z80 instruction exerciser" banner and produces no ERROR within a
-  time-bounded budget.
+| Chip | Type | Tests | LOC | Validation |
+| --- | --- | --- | --- | --- |
+| **8080** | CPU | 20 | 470 | ✅ TST8080.COM (Microcosm CPUDIAG 1980) prints "CPU IS OPERATIONAL"; 8080PRE.COM passes |
+| **Z80**  | CPU | 23 | 800 | ✅ ZEXDOC (Frank Cringle 1994) prints "Z80 instruction exerciser" banner |
+| **4004** | CPU | 9  | 470 | ISA passes 9 tests; integration with real 4001 ROM passes |
+| **4040** | CPU | 5  | 500 | ISA + INT vectoring passes |
+| **8086** | CPU | 12 | 800 | ISA + 8259 PIC interrupt-routing integration passes |
+| `rom-32k` | bus | 6 | 80 | EPROM-style 32 KB ROM |
+| `ram-64k` | bus | 7 | 110 | SRAM with R/W |
+| `latch-8282` | bus | 4 | 80 | 8086 address demux |
+| `rom-1m` | bus | 4 | 100 | 64 KB ROM mapped at 0xF0000 (8086 boot) |
+| `8255-ppi` | bus | 5 | 200 | 3 × 8-bit parallel ports, Mode 0 |
+| `8251-usart` | bus | 4 | 200 | Async UART via vx_uart_attach |
+| **`4001-rom`** | bus | 1 | 140 | ROM partner for 4004; integrates over multiplexed nibble bus |
+| **`4002-ram`** | bus | 2 | 150 | RAM partner for 4004 (skeleton; full I/O cycle pending) |
+| **`8259-pic`** | bus | 7 | 280 | Interrupt controller, single-master, full ICW/OCW |
+| **`8253-pit`** | bus | 4 | 210 | Programmable timer, Modes 0/2/3 |
 
-These are the canonical historical diagnostics that real Altair/IMSAI
-8080 systems and Sinclair/MSX/CP/M Z80 systems used to validate their
-CPUs. Our chips run them.
+All 5 retro Intel/Zilog CPUs + 9 bus/peripheral chips, all
+clean-room from manufacturer datasheets. **8080 runs the canonical
+1980 Microcosm CPU Diagnostic to "CPU IS OPERATIONAL"; Z80 runs
+Frank Cringle's ZEXDOC; 8086 takes hardware interrupts from a real
+8259 PIC chip on the same board.**
 
 Phase plan in `autosearch/18_complete_emulation_plan.md` tracks
-remaining work: 4001/4002/8253/8259 chips for canvas demos;
-8088 V2 SingleStepTests for 8086; Busicom 141-PF for 4004; full
-ZEXDOC validation. No velxio core source has been modified. Run
-`npm test` from `test/test_intel/` to confirm.
+remaining work: 4004 SRC/I/O wiring to exchange data with the 4002,
+Busicom 141-PF integration, full ZEXDOC validation, 8088 V2
+SingleStepTests, Phase G cycle accuracy. No velxio core source has
+been modified. Run `npm test` from `test/test_intel/` to confirm.