89 lines
3.5 KiB
Markdown
89 lines
3.5 KiB
Markdown
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# test_8080 — Intel 8080 as a velxio custom chip
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See [../autosearch/02_intel_chips_overview.md](../autosearch/02_intel_chips_overview.md#intel-8080-1974)
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for the spec.
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## Status
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✅ **Implemented.** 18/20 tests passing. ~470 LOC clean-room C in
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`8080.c` compiled to `fixtures/8080.wasm`.
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Validated against:
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- Intel 8080 Microcomputer Systems User's Manual (Sept 1975, doc 98-153B)
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- Intel 8080/8085 Assembly Language Programming Manual (May 1981, doc 9800301D)
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- Cross-checked AC flag rules, DAA, status bytes, and CALL/RST stack
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ordering against `superzazu/8080` (MIT, passes 8080EXM) and
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`mayawarrier/intel8080-emulator` (MIT). No code was copied — only
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authoritative spec consultation.
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The 2 remaining `it.todo` tests are integration milestones (hand-built
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loop, CPUDIAG ROM run) deferred until a generic `rom-32k` chip exists.
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## Pin contract (40-pin DIP)
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Power simplified: real 8080 needed +12 V / +5 V / −5 V; we collapse to
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single `VCC` / `GND`. Documented under
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[../autosearch/05_open_questions.md](../autosearch/05_open_questions.md#q6-power-pins--collapse-or-model).
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| Group | Pins | Dir |
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| ------------ | ----------------------------------- | --- |
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| Address bus | `A0..A15` | out |
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| Data bus | `D0..D7` | I/O |
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| Status/ctl | `SYNC`, `DBIN`, `WR̅`, `INTE` | out |
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| Inputs | `RESET`, `READY`, `HOLD`, `INT` | in |
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| Outputs | `WAIT`, `HLDA` | out |
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| Clock | `φ1`, `φ2` | in |
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| Power | `VCC`, `GND` | power |
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Total registered pins: 16 (addr) + 8 (data) + 4 (status) + 4 (inputs) +
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2 (outputs) + 2 (clock) + 2 (power) = **38**. Two real-silicon pins
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(`+12`, `−5`) are dropped.
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## Bus cycle reference
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For each machine cycle:
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```
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T1: drive A0..A15 with target address.
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Drive D0..D7 with status byte (memory read = 0x82, etc.).
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Pulse SYNC high.
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T2: deassert SYNC. Switch D0..D7 to input (for reads) or hold them
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as data output (for writes). Assert DBIN (read) or WR̅ (write).
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T3: sample D0..D7 (read) or hold (write).
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TW: optional, while READY is low.
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T4..T5: instruction-internal work, no bus activity.
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```
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In the timer-driven model we collapse all five T-states into a single
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"step one instruction" callback that internally walks T1→T3 and emits
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the pin events in order. A faithful single-step mode driven by an
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external clock chip is a follow-up.
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## Target demo sketch
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CP/M-style "hello world" via memory-mapped UART: 8080 wired to a
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ROM chip (program), a RAM chip (stack/heap), and a UART chip
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(velxio's `uart-rot13.c` example shows that custom UARTs work).
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Program prints to UART; user sees output in the velxio serial monitor.
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This is a real, recognisable retro-computing demo.
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## Implementation plan
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1. Spike a minimal 8080 chip that runs MOV / ADD / JMP only,
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driving an LED off `D0` of a memory-mapped output port. Confirms
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the bus state machine works.
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2. Port the full ISA from a permissively-licensed reference (see
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`autosearch/04`) into `8080.c`.
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3. Run CPUDIAG (the standard 8080 self-test program) — load it as
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ROM, verify it prints "CPU IS OPERATIONAL" via the UART.
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4. Add interrupt support (8259-style PIC is out of scope; just `INT`
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pin → fixed RST vector for the first cut).
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## Files to create later
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- `8080.chip.json`
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- `8080.c` (or split into `8080.c` + `8080_decode.h` if it gets large)
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- `roms/cpudiag.bin` (public-domain test ROM)
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- `8080.test.ts`
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