176 lines
7.2 KiB
Markdown
176 lines
7.2 KiB
Markdown
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# Per-chip overview (4004, 4040, 8080, 8086, Z80)
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These are well-documented chips with public-domain datasheets mirrored
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in many places (Intel archives, Wikipedia, CPU-world.com, datasheet
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archives). Numbers below are common-knowledge from the original
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datasheets; anything I am not sure about is marked **[verify]**.
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---
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## Intel 4004 (1971)
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- **Package:** 16-pin DIP.
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- **Word size:** 4-bit.
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- **Address space:** 12 bits → 4 KB program ROM, 1280 nibbles RAM
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organised across up to 4 banks of 4 chips of 4 registers of 20
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characters (data is nibble-addressed, not byte-addressed).
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- **Bus:** Heavily multiplexed. The 4 data pins `D0–D3` carry, in
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successive cycles within an 8-cycle "instruction cycle":
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- A1, A2, A3 — three nibbles of address (12 bits total),
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- M1, M2 — two nibbles of opcode/operand,
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- X1, X2, X3 — three execution sub-cycles.
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- **Control pins:** `SYNC` (cycle marker), `CM-ROM`, `CM-RAM0..3`
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(chip-select to ROMs and RAMs), `RESET`, `TEST`, `CLK1`, `CLK2`
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(two-phase clock), `VDD`, `VSS`.
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- **Clock:** 740 kHz typical (dual-phase). Instruction cycle = 8 clock
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phases ≈ 10.8 µs.
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- **Registers:** 16 × 4-bit index registers (R0–R15), 4-bit
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accumulator, carry, 12-bit program counter, 3-deep PC stack.
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- **Instruction count:** 46 instructions, all 1 or 2 bytes.
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### Implementation note
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The 4004 is the *easiest* CPU semantically — small ISA, tiny register
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file — but the *most awkward* electrically because everything is
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multiplexed onto 4 pins across an 8-cycle frame. The chip would have
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to drive `SYNC` and walk through the A1/A2/A3/M1/M2/X1/X2/X3 phases
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each instruction.
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---
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## Intel 4040 (1974)
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- **Package:** 24-pin DIP.
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- **Word size:** 4-bit.
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- **Compatibility:** Superset of the 4004; same instruction format
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with additions.
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- **Additions over 4004:**
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- Interrupt input (`INT`) and interrupt acknowledge.
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- Single-step / `STOP` / `STOP ACK`.
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- 8 extra index registers (24 total: R0–R23).
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- PC stack expanded to 7-deep.
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- 14 additional instructions for interrupt and stack handling.
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- **Bus:** Same nibble-multiplexed scheme as 4004 plus the new control
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signals.
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- **Clock:** 740 kHz, same dual-phase scheme. **[verify exact pin-to-pin
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pinout from a 4040 datasheet before committing the .chip.json]**
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### Implementation note
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Reusing the 4004 emulator core and adding the new opcodes + interrupt
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handling is the obvious path. Most of the new work is the bigger
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register file and the interrupt vector logic.
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---
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## Intel 8080 (1974)
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- **Package:** 40-pin DIP.
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- **Word size:** 8-bit.
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- **Address bus:** 16 bits, **separate** pins `A0–A15` → 64 KB.
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- **Data bus:** 8 bits, separate pins `D0–D7`. During T1 of each machine
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cycle the data bus carries a *status byte* (memory read, I/O write,
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interrupt acknowledge, etc.); this is normally latched by an external
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8228 system controller. We can either model that internally or expose
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a `SYNC`/`DBIN`/`WR` triplet and let the user wire an 8228-equivalent.
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- **Control pins:** `SYNC`, `DBIN`, `WR̅`, `READY`, `WAIT`, `HOLD`,
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`HLDA`, `INT`, `INTE`, `RESET`. Plus power: `+12 V`, `+5 V`, `−5 V`,
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`GND` (the real chip needed three rails — we will collapse this to a
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single `VCC`/`GND` pair since velxio is digital).
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- **Clock:** External 2-phase clock, normally generated by an 8224.
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Typical instruction rate: 2 MHz φ.
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- **Registers:** A, B, C, D, E, H, L (six 8-bit + accumulator), 16-bit
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SP, 16-bit PC, flags (S, Z, AC, P, CY).
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- **Instruction count:** 244 opcodes (78 base instructions, many
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register variants).
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### Implementation note
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Cleanest of the bunch electrically — separate address/data buses and
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a small set of control signals. `superzazu/8080` (MIT-licensed
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single-file C emulator that passes the standard CPUDIAG test) is a
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strong porting candidate.
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---
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## Zilog Z80 (1976)
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- **Package:** 40-pin DIP.
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- **Word size:** 8-bit.
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- **Compatibility:** Binary-compatible with 8080 + extensions.
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- **Address bus:** 16 bits, separate `A0–A15`.
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- **Data bus:** 8 bits, separate `D0–D7`.
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- **Control pins:** `M1` (opcode fetch marker), `MREQ`, `IORQ`, `RD`,
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`WR`, `RFSH` (DRAM refresh), `HALT`, `WAIT`, `INT`, `NMI`, `RESET`,
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`BUSREQ`, `BUSACK`, `CLK`, `+5 V`, `GND` — a single 5 V rail, single
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clock phase. Much friendlier than the 8080 in this respect.
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- **Clock:** Single-phase. Common rates 2.5 / 4 / 6 / 8 MHz.
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- **Registers:** A, F, B, C, D, E, H, L (main set) + identical shadow
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set (A', F', …); IX, IY (16-bit index); SP, PC; I (interrupt vector);
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R (memory refresh, 7-bit increments each M1).
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- **Interrupt modes:** IM0, IM1 (RST 38h), IM2 (vectored via I).
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- **Instruction count:** ~700 effective opcodes including CB, ED, DD,
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FD, DDCB, FDCB prefix tables.
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### Implementation note
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The Z80 is the **best documented** of the lot: Andre Weissflog's
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`floooh/chips/z80.h` is a single-header MIT-licensed cycle-accurate
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emulator. Porting it as-is (or close to as-is) into a velxio chip is
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the most credible "first instruction-level CPU" milestone.
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---
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## Intel 8086 (1978)
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- **Package:** 40-pin DIP.
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- **Word size:** 16-bit.
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- **Address bus:** 20 bits → 1 MB (with segment:offset addressing,
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segments are 16-bit shifted left 4 = 64 KB windows in 1 MB).
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- **Data bus:** 16-bit, **multiplexed** with the low 16 address bits
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on pins `AD0–AD15`. The high 4 address bits share with status pins
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`A16/S3 .. A19/S6`. Demultiplexing is normally done by an 8282/8283
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latch driven by `ALE`.
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- **Operating modes:** Minimum mode (MN/MX̅ tied high) and maximum
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mode (tied low), which remap several control pins for use with the
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8288 bus controller. We will start with minimum mode.
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- **Control pins (min mode):** `ALE`, `RD`, `WR`, `M/IO`, `DT/R`, `DEN`,
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`HOLD`, `HLDA`, `INTR`, `NMI`, `INTA`, `TEST`, `READY`, `RESET`,
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`CLK`. Plus the multiplexed AD bus.
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- **Clock:** External, generated by 8284A. Rates: 5, 8, 10 MHz.
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- **Registers:** AX/BX/CX/DX (each split into high/low), SP, BP, SI,
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DI; CS, DS, SS, ES segment registers; IP; flags.
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- **Instruction set:** Variable-length 1–6 byte instructions. Prefetch
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queue (6 bytes on 8086, 4 on 8088) — emulators usually skip
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micro-architectural prefetch and just decode at IP, which is fine for
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most software.
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### Implementation note
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The 8086 is the most ambitious target. The killer features versus the
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8080/Z80:
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- AD bus multiplexing — the chip has to drive `ALE` to latch addresses
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and then either drive or read 16 data bits in the same pin group.
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- 20-bit physical addresses from 16-bit segment + 16-bit offset.
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- Variable-length decode and a much bigger ISA (effective addressing
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modes, ModR/M byte).
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Adrian Cable's `8086tiny` (\~4 KB of dense C, MIT-style) is the canonical
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small-footprint 8086 emulator and a credible porting source. License
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needs review before vendoring into the repo.
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---
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## Pin-count budget summary
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| Chip | Real pin count | Pins we need to register in velxio |
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| ---- | -------------- | ----------------------------------- |
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| 4004 | 16 | 16 (or fewer if we collapse the two unused VDD/VSS) |
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| 4040 | 24 | 24 |
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| 8080 | 40 | ~38 (collapse the 3 power rails into one VCC) |
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| Z80 | 40 | 40 |
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| 8086 | 40 | 40 |
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All within the runtime's per-chip pin table. Nothing here is a blocker.
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