53 lines
2.4 KiB
Markdown
53 lines
2.4 KiB
Markdown
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# 64 KB SRAM — pinout reference for `ram-64k.c`
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The closest real-world part to the 64 KB byte-wide SRAM we want is
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the **HM628512 / HM6264** family from Hitachi (later Renesas), or the
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**Cypress CY62256** (which is 32 KB) scaled up. For the velxio model
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we use an idealised 64 KB part: 16 address pins, 8 data pins, three
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control signals.
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## Package: 32-pin DIP-equivalent (logical model)
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| Group | Pins | Direction | Notes |
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|-------|------|-----------|-------|
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| Power | VCC, GND | power | +5 V |
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| Address | A0..A15 (16) | input | Selects byte at offset `addr` |
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| Data | D0..D7 (8) | bidirectional | Output during read, input during write |
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| Chip enable | CE̅ | input | Active-low |
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| Output enable | OE̅ | input | Active-low |
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| Write enable | WE̅ | input | Active-low |
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## Read / write logic
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| CE̅ | WE̅ | OE̅ | Mode | Action |
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|-----|-----|-----|----------------------|--------|
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| H | x | x | **Not selected** | D pins high-Z; mem unchanged |
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| L | H | L | **Read** | Drive `mem[addr]` onto D pins |
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| L | H | H | **Output disable** | D pins high-Z; mem unchanged |
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| L | L | x | **Write** | Latch `mem[addr] := data` on WE̅ rising edge |
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The "rising-edge latches" convention matches every common SRAM
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datasheet and is what `ram-64k.test.js`'s `writeCycle()` helper
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asserts: drop WE̅ low, hold for a setup time, raise WE̅ → cell is
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written. Real SRAMs latch at end-of-WE per the part's `t_DH` (data
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hold) timing; we model that as instantaneous on the rising edge.
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## Power-on state
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Real SRAM is volatile and powers up with **indeterminate** contents.
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The `ram-64k.test.js` blank-state assertion (`reads 0x00 from
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never-written addresses`) relies on our model zero-initialising mem at
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chip_setup. This is a deliberate simplification — easier to test
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against, and matches what most simulators do (Wokwi, ASIC Verilog
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sims, etc.).
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## Why no PCB-realistic 28-pin layout
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The HM62256 (32 KB, 28-pin) was the real-world workhorse and a
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faithful "32-pin equivalent of 62256" doesn't exist as a single chip
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historically. For 64 KB on a single chip, the practical options are
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the HM628128 (16 KB? no — 128 Kbit = 16 KB) family up through
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HM628512 (512 Kbit = 64 KB, 32-pin DIP). We adopt the HM628512 pin
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philosophy without modelling its precise pin ordering, since velxio
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doesn't enforce DIP-package physical layout.
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